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Author SHA1 Message Date
Masa Bence 1420479be7 std: update Arraylist in unicode.zig to unmanaged 2026-10-27 19:37:22 +01:00
Krzysztof Wolicki cb98d75813 Remove usage of array_list.Managed from tools (#37419) 
Reviewed-on: https://codeberg.org/ziglang/zig/pulls/37419
Reviewed-by: Ryan Liptak <squeek502@noreply.codeberg.org>
 2026-10-27 19:09:02 +01:00
Francisco Nevitt Gonçalves a8165f8e8d Add missing flush in FuzzTestRunner.saveCrash 
This was causing crash files to be truncated, preventing users from
reproducing fuzzing crashes.
 2026-10-27 17:37:42 +01:00
akbarhusain 167a8f987f std.Io: fix flush spin on failing io 2026-10-27 17:35:34 +01:00
Lwazi Dube 6b685a440e Fix invalid bx instuction error when building for strongarm 
The following command was used for building:
zig build -Dtarget=arm-freestanding -Dcpu=strongarm1110 --release=safe
 2026-10-27 17:34:13 +01:00
mlugg cb6f0c25f1 Merge pull request 'compiler: add testing for Air.Legalize pass' (#37410) from mlugg/legalize-tests into master 
Reviewed-on: https://codeberg.org/ziglang/zig/pulls/37410
 2026-10-26 15:18:03 +01:00
Matthew Lugg f6751410e9 build: run some tests with -flegalize-all 
It's useful to run both a little-endian and a big-endian target here,
because some legalizations are susceptible to endianness bugs, e.g. any
related to bitwise operations or to `packed` (aka `bitpack`) types.

When modifying legalizations or adding new ones, they can be tested by
running `zig build test-modules -Donly-legalize` to limit to the targets
which pass `-flegalize-all`.

This makes it much easier to facilitate external contributions towards
https://codeberg.org/ziglang/zig/issues/36719, and will prevent
legalization passes from bit-rotting in the future.
 2026-10-26 14:17:03 +00:00
Matthew Lugg 405cc93b89 compiler: add -flegalize-all option 
This option is intended for compiler development and testing. It forces
all `Air.Legalize` passes to be enabled, so we can exhaustively test the
functionality of legalization passes even before any backend enables
them. The option is limited to the LLVM backend, because enabling
legalizations often requires some level of backend support (e.g. support
for the `legalize_compiler_rt_call` instruction tag), and it's usually
fairly simple to support these in the LLVM backend *and* gets us a lot
of test coverage (in particular, it lets us test on both big-endian and
little-endian targets).
 2026-10-26 14:17:03 +00:00
Matthew Lugg 9ebba3b64d llvm: fix bugs in lowering of legalized vector operations 
Includes a workaround for an upstream LLVM bug tracked at
https://github.com/llvm/llvm-project/issues/235439.
 2026-10-26 14:17:03 +00:00
Matthew Lugg 285eabdd95 Air: update .legalize_compiler_rt_call symbol names 
The names of the f128 exports in compiler_rt were changed recently, but
since no backend currently uses the soft-float legalizations, they were
missed in the update.
 2026-10-26 14:17:03 +00:00
Ali Cheraghi fa7d3ebac4 Merge pull request 'spirv: don't unroll all vector operation + bug fixes' (#37409) from alichraghi/zig:spirv-vec into master 
Reviewed-on: https://codeberg.org/ziglang/zig/pulls/37409
 2026-10-26 13:33:05 +01:00
Alex Rønne Petersen ae9a8acc7f Merge branch 'target-stuff' 2026-10-26 11:11:12 +01:00
Alex Rønne Petersen cc5976f9b2 stage1: update zig1.wasm 
Signed-off-by: Alex Rønne Petersen <alex@alexrp.com>
 2026-10-26 11:10:48 +01:00
Alex Rønne Petersen 2d6ff903a1 std.Target: add z80 arch tag and ABI info 
Also fix cCharSignedness() for ez80.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 3237f171fd update_cpu_features: populate z80 data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 9c3ad8e457 gen_spirv_spec: remove broken version field in generated spec 
There's no patch field on the Version struct. We also don't use this field
anywhere because it represents the version the spec happened to be generated
from, which is not very useful for the compiler.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen f2140c7cfb gen_spirv_spec, update_cpu_features: fix some accidentally omitted capabilities 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 6ba6a19a8b gen_spirv_spec, update_cpu_features: fix capabilities missing implied capabilities 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 38186a3cfe std.Target: update some baseline() CPU models 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 1ee1c9b1c0 gen_spirv_spec, update_cpu_features: omit provisional spirv features 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen da74d9df7f update_cpu_features: omit SPV_EXT_physical_storage_buffer 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen ea23fdce37 gen_spirv_spec, update_cpu_features: omit v1_0 spirv feature 
It's always implied so it's just a waste of bytes.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 93e6194050 codegen.spirv.spec, std.Target.spirv: regenerate from 1.6.7 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen c41d12dee7 update_cpu_features: remove some legacy leftover spirv features 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 820ee28df0 update_cpu_features: omit matrix spirv feature 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 766840daf1 std.Target: remove the kalimba arch tag 
What little target info we had for this was incomplete/wrong, and it's
annoyingly difficult to get reliable information about it because Qualcomm
doesn't publish the documentation. So just delete it.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen c7716c1212 update_cpu_features: populate microblaze data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0bb7fc0cd0 update_cpu_features: populate sh data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 2d2de5f69e std.Target: fix Abi.default() for sh-openbsd and sh(eb)-netbsd 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 8df29bb518 update_cpu_features: populate or1k data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen beadbc63ec update_cpu_features: map cell powerpc model to LLVM's 970 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 1bd2abaf53 update_cpu_features: map e6500 powerpc model to LLVM's e5500 
This is the closest sensible thing for scheduling purposes.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0f100d1987 update_cpu_features: map r3000a and allegrex mips models to mips1/mips2 in LLVM 
Otherwise Clang misclassifies them as mips32r2.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0892046a15 update_cpu_features: map some arm and aarch64 models to LLVM's generic 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen f759705998 update_cpu_features: populate m88k data 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 06555e298d update_cpu_features: rename generic xtensa model to xtensa 
Since it's just the base Xtensa ISA.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 4449211074 update_cpu_features: rename generic arc model to arcv2 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen e80dcf3474 update_cpu_features: rename generic csky model to e2 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen a78fcdb756 compiler: work around crbits bug in LLVM's powerpc backend 
https://github.com/llvm/llvm-project/issues/235393
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 4d94cf182f std.hash.crc: fix x86_64 + crc32 feature check 
The 64bit feature just indicates that the model has long mode support; it does
not necessarily mean that we are compiling for 64-bit.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen f542e8050e update_cpu_features: rename 64bit_support powerpc feature to 64bit 
For consistency with x86.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 51fdb7063e update_cpu_features: add riscv profile models and flatten the profile features 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 104652f6c6 update_cpu_feature: replace generic/baseline riscv models with common arch combos 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen dd949d3153 update_cpu_features: don't map generic csky model to LLVM's generic 
Clang doesn't recognize it.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen b012a84c34 std.Target: pick better baseline models for spirv 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen cdadcb2e1d std.Target: adjust OS min/max version ranges for GPU targets 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 020aa22288 update_cpu_features: flesh out spirv models a bit 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 1b0ce53885 compiler: don't pass CPU model name to clang for spirv 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 2361de28fd update_cpu_features: don't map generic_la32 loongarch model to LLVM's generic-la32 
Clang doesn't recognize it.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 1e440e14ef update_cpu_feature: replace generic aarch64 model with architecture level models 
And use armv8a as the generic model.

The old generic model was incoherent; it didn't even have v8a.
 2026-10-26 11:02:43 +01:00