mirrors/zig
0
0 Fork 0
mirror of https://codeberg.org/ziglang/zig.git synced 2026-10-28 10:45:48 +08:00
Code Activity

update_cpu_features: map some arm and aarch64 models to LLVM's generic

Browse Source
This commit is contained in:
Alex Rønne Petersen committed 2026-10-26 11:02:44 +01:00
1 parent f759705998
commit 0892046a15
3 files changed
+12 -12
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

lib/std/Target/aarch64.zig
+4 -4
View File
@@ -3361,7 +3361,7 @@ pub const cpu = struct {
};
pub const emag: CpuModel = .{
.name = "emag",
.llvm_name = null,
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.crc,
.crypto,
@@ -3371,7 +3371,7 @@ pub const cpu = struct {
};
pub const exynos_m1: CpuModel = .{
.name = "exynos_m1",
.llvm_name = null,
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.crc,
.crypto,
@@ -3384,7 +3384,7 @@ pub const cpu = struct {
};
pub const exynos_m2: CpuModel = .{
.name = "exynos_m2",
.llvm_name = null,
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.crc,
.crypto,
@@ -3987,7 +3987,7 @@ pub const cpu = struct {
};
pub const xgene1: CpuModel = .{
.name = "xgene1",
.llvm_name = null,
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.perfmon,
.v8a,
lib/std/Target/arm.zig
+2 -2
View File
@@ -2277,7 +2277,7 @@ pub const cpu = struct {
};
pub const exynos_m1: CpuModel = .{
.name = "exynos_m1",
.llvm_name = null,
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.crypto,
.expand_fp_mlx,
@@ -2298,7 +2298,7 @@ pub const cpu = struct {
};
pub const exynos_m2: CpuModel = .{
.name = "exynos_m2",
.llvm_name = null,
.llvm_name = "generic",
.features = featureSet(&[_]Feature{
.crypto,
.expand_fp_mlx,
tools/update_cpu_features.zig
+6 -6
View File
@@ -861,7 +861,7 @@ const targets = [_]ArchTarget{
},
.{
.llvm_name = null,
.llvm_name = "generic",
.zig_name = "exynos_m1",
.features = &.{
"crc",
@@ -874,7 +874,7 @@ const targets = [_]ArchTarget{
},
},
.{
.llvm_name = null,
.llvm_name = "generic",
.zig_name = "exynos_m2",
.features = &.{
"crc",
@@ -887,7 +887,7 @@ const targets = [_]ArchTarget{
},
},
.{
.llvm_name = null,
.llvm_name = "generic",
.zig_name = "xgene1",
.features = &.{
"perfmon",
@@ -895,7 +895,7 @@ const targets = [_]ArchTarget{
},
},
.{
.llvm_name = null,
.llvm_name = "generic",
.zig_name = "emag",
.features = &.{
"crc",
@@ -1970,12 +1970,12 @@ const targets = [_]ArchTarget{
.features = &.{ "v7a", "vfp3d16" },
},
.{
.llvm_name = null,
.llvm_name = "generic",
.zig_name = "exynos_m1",
.features = &.{ "v8a", "exynos" },
},
.{
.llvm_name = null,
.llvm_name = "generic",
.zig_name = "exynos_m2",
.features = &.{ "v8a", "exynos" },
},