Merge branch 'target-stuff'

CMakeLists.txt

@@ -627,8 +627,8 @@ else()
   set(ZIG2_COMPILE_FLAGS "-std=c99 -Oz -fno-sanitize=undefined -fno-stack-protector -fno-strict-aliasing")
   # Must match the condition in build.zig.
   if(ZIG_HOST_TARGET_ARCH MATCHES "^(arm|thumb)(eb)?$" OR ZIG_HOST_TARGET_ARCH EQUAL "hexagon" OR ZIG_HOST_TARGET_ARCH MATCHES "^powerpc(64)?(le)?$")
-    set(ZIG1_COMPILE_FLAGS "${ZIG1_COMPILE_FLAGS} -ffunction-sections -fdata-sections")
-    set(ZIG2_COMPILE_FLAGS "${ZIG2_COMPILE_FLAGS} -ffunction-sections -fdata-sections")
+    set(ZIG1_COMPILE_FLAGS "${ZIG1_COMPILE_FLAGS} -ffunction-sections")
+    set(ZIG2_COMPILE_FLAGS "${ZIG2_COMPILE_FLAGS} -ffunction-sections")
   endif()
   if (CMAKE_C_COMPILER_ID STREQUAL "GNU")
     # Prevent GCC from miscompiling 'zig2.c'. See also 'GCC_BUG_119085_PRESENT' workaround details in 'bootstrap.c'.

build.zig

@@ -930,24 +930,6 @@ fn addCompilerStep(b: *std.Build, options: AddCompilerModOptions) *std.Build.Ste
     });
     exe.stack_size = stack_size;
 
-    // Must match the condition in CMakeLists.txt.
-    const function_data_sections = switch (options.target.result.cpu.arch) {
-        .arm,
-        .armeb,
-        .thumb,
-        .thumbeb,
-        .hexagon,
-        .powerpc,
-        .powerpcle,
-        .powerpc64,
-        .powerpc64le,
-        => true,
-        else => false,
-    };
-
-    exe.link_function_sections = function_data_sections;
-    exe.link_data_sections = function_data_sections;
-
     return exe;
 }
 

lib/compiler/Maker/Step/Compile.zig

@@ -630,8 +630,8 @@ fn lowerZigArgs(
 
     try addBool(gpa, zig_args, "--eh-frame-hdr", conf_comp.flags.link_eh_frame_hdr);
     try addBool(gpa, zig_args, "--emit-relocs", conf_comp.flags.link_emit_relocs);
-    try addBool(gpa, zig_args, "-ffunction-sections", conf_comp.flags.link_function_sections);
-    try addBool(gpa, zig_args, "-fdata-sections", conf_comp.flags.link_data_sections);
+    try addFlag(gpa, zig_args, "function-sections", conf_comp.flags4.function_sections.toBool());
+    try addFlag(gpa, zig_args, "data-sections", conf_comp.flags4.data_sections.toBool());
 
     if (conf_comp.flags2.link_gc_sections.toBool()) |x|
         try zig_args.append(gpa, if (x) "--gc-sections" else "--no-gc-sections");

lib/compiler/aro/aro/Compilation.zig

@@ -729,10 +729,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
                 try define(w, "__APX_F__");
             }
 
-            if (target.cpu.hasAll(.x86, &.{ .egpr, .inline_asm_use_gpr32 })) {
-                try define(w, "__APX_INLINE_ASM_USE_GPR32__");
-            }
-
             if (target.cpu.has(.x86, .cx8)) {
                 try define(w, "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
             }
@@ -800,18 +796,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
                 try w.print("#define _MIPS_ARCH_{s} 1\n", .{upper});
             }
 
-            if (!target.cpu.has(.mips, .noabicalls)) {
-                try define(w, "__mips_abicalls");
-                if (target.os.tag.isBSD()) {
-                    try define(w, "__ABICALLS__");
-                }
-            }
-
-            if (target.cpu.has(.mips, .soft_float)) {
-                try define(w, "__mips_soft_float");
-            } else {
-                try define(w, "__mips_hard_float");
-            }
             if (target.cpu.has(.mips, .single_float)) {
                 try define(w, "__mips_single_float");
             }
@@ -825,12 +809,9 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
                 const fpset: u8 = if (target.defaultMipsFpMode() == .fp64 or
                     target.cpu.has(.mips, .single_float)) 32 else 16;
                 try w.print("#define _MIPS_FPSET {d}\n", .{fpset});
-                const spfpset: u8 = if (target.cpu.has(.mips, .nooddspreg) or
-                    target.defaultMipsFpMode() == .fpxx) 16 else 32;
+                const spfpset: u8 = if (target.defaultMipsFpMode() == .fpxx) 16 else 32;
                 try w.print("#define _MIPS_SPFPSET {d}\n", .{spfpset});
             }
-            if (target.cpu.has(.mips, .mips16)) try define(w, "__mips16");
-            if (target.cpu.has(.mips, .micromips)) try define(w, "__mips_micromips");
             if (target.cpu.has(.mips, .nan2008)) try define(w, "__mips_nan2008");
             if (target.cpu.has(.mips, .abs2008)) try define(w, "__mips_abs2008");
             if (target.cpu.has(.mips, .dspr3)) {
@@ -918,7 +899,7 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
                 }
             }
 
-            if (target.cpu.has(.arm, .thumb2) or target.cpu.has(.arm, .thumb_mode)) {
+            if (target.cpu.has(.arm, .thumb2) or target.cpu.arch.isThumb()) {
                 try define(w, "__thumb__");
             }
             // ARM ISA means we are not M profile
@@ -1017,7 +998,7 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
                 try w.print("#define __ARM_FEATURE_LDREX 0x{x}\n", .{@as(u4, @bitCast(ldrex))});
             }
 
-            if (!target.cpu.has(.arm, .strict_align)) {
+            if (!target.cpu.has(.arm, .no_unaligned_access)) {
                 try define(w, "__ARM_FEATURE_UNALIGNED");
             }
 
@@ -1136,9 +1117,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
                 try define(w, "__ARM_FEATURE_SME");
                 try define(w, "__ARM_FEATURE_LOCALLY_STREAMING");
             }
-            if (target.cpu.has(.aarch64, .fmv)) {
-                try define(w, "__HAVE_FUNCTION_MULTI_VERSIONING");
-            }
             if (target.cpu.has(.aarch64, .sha3)) {
                 try define(w, "__ARM_FEATURE_SHA3");
                 try define(w, "__ARM_FEATURE_SHA512");
@@ -1147,7 +1125,7 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
                 try define(w, "__ARM_FEATURE_SM3");
                 try define(w, "__ARM_FEATURE_SM4");
             }
-            if (!target.cpu.has(.aarch64, .strict_align)) {
+            if (!target.cpu.has(.aarch64, .no_unaligned_access)) {
                 try define(w, "__ARM_FEATURE_UNALIGNED");
             }
             if (target.cpu.hasAll(.aarch64, &.{ .neon, .fullfp16 })) {
@@ -1228,10 +1206,10 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void {
             try define(w, "__s390x__");
             try define(w, "__zarch__");
 
-            if (target.cpu.has(.s390x, .transactional_execution)) {
+            if (target.cpu.has(.s390x, .te)) {
                 try define(w, "__HTM__");
             }
-            if (target.cpu.has(.s390x, .vector)) {
+            if (target.cpu.has(.s390x, .vx)) {
                 try define(w, "__VX__");
             }
         },

lib/compiler/aro/aro/Target.zig

@@ -116,7 +116,6 @@ pub const SubArch = enum {
         } else if (arch.isSpirv()) {
             const spirv = std.Target.spirv.Feature;
             return @backingInt(switch (sub) {
-                .spirv_v10 => spirv.v1_0,
                 .spirv_v11 => spirv.v1_1,
                 .spirv_v12 => spirv.v1_2,
                 .spirv_v13 => spirv.v1_3,
@@ -1085,6 +1084,7 @@ pub fn get32BitArchVariant(target: *const Target) ?Target {
         .s390x,
         .spork8,
         .ve,
+        .z80,
         => return null,
 
         .arc,
@@ -1094,7 +1094,6 @@ pub fn get32BitArchVariant(target: *const Target) ?Target {
         .csky,
         .hexagon,
         .hppa,
-        .kalimba,
         .lanai,
         .loongarch32,
         .m68k,
@@ -1152,7 +1151,6 @@ pub fn get64BitArchVariant(target: *const Target) ?Target {
         .csky,
         .ez80,
         .hexagon,
-        .kalimba,
         .lanai,
         .m68k,
         .m88k,
@@ -1167,6 +1165,7 @@ pub fn get64BitArchVariant(target: *const Target) ?Target {
         .xcore,
         .xtensa,
         .xtensaeb,
+        .z80,
         => return null,
 
         .aarch64_be,
@@ -1274,7 +1273,6 @@ pub fn toLLVMTriple(target: *const Target, buf: []u8) []const u8 {
         .ez80 => "ez80",
         .hppa => "hppa",
         .hppa64 => "hppa64",
-        .kalimba => "kalimba",
         .kvx => "kvx",
         .microblaze => "microblaze",
         .microblazeel => "microblazeel",
@@ -1286,13 +1284,13 @@ pub fn toLLVMTriple(target: *const Target, buf: []u8) []const u8 {
         .spork8 => "spork8",
         .x86_16 => "i86",
         .xtensaeb => "xtensaeb",
+        .z80 => "z80",
     };
     writer.writeAll(llvm_arch) catch unreachable;
     writer.writeByte('-') catch unreachable;
 
     const llvm_os = switch (target.os.tag) {
         .amdhsa => "amdhsa",
-        .amdpal => "amdpal",
         .cuda => "cuda",
         .dragonfly => "dragonfly",
         .driverkit => "driverkit",
@@ -1307,7 +1305,6 @@ pub fn toLLVMTriple(target: *const Target, buf: []u8) []const u8 {
         .linux => "linux",
         .macos => "macosx",
         .managarm => "managarm",
-        .mesa3d => "mesa3d",
         .netbsd => "netbsd",
         .nvcl => "nvcl",
         .openbsd => "openbsd",
@@ -1410,8 +1407,6 @@ pub fn isPIEDefault(target: *const Target) DefaultPIStatus {
 
         .cuda,
         .amdhsa,
-        .amdpal,
-        .mesa3d,
 
         .ps4,
         .ps5,
@@ -1484,8 +1479,6 @@ pub fn isPICdefault(target: *const Target) DefaultPIStatus {
         .driverkit,
 
         .amdhsa,
-        .amdpal,
-        .mesa3d,
 
         .ps4,
         .ps5,
@@ -1551,7 +1544,7 @@ pub fn isPICdefault(target: *const Target) DefaultPIStatus {
 
 pub fn isPICDefaultForced(target: *const Target) DefaultPIStatus {
     return switch (target.os.tag) {
-        .amdhsa, .amdpal, .mesa3d => .yes,
+        .amdhsa => .yes,
 
         .haiku,
         .dragonfly,

lib/compiler_rt/atomics.zig

@@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) {
     // On SPARC systems that lacks CAS and/or swap instructions, the only
     // available atomic operation is a test-and-set (`ldstub`), so we force
     // every atomic memory access to go through the lock.
-    .sparc => if (builtin.cpu.has(.sparc, .hasleoncasa)) @sizeOf(usize) else 0,
+    .sparc => if (builtin.cpu.hasAny(.sparc, &.{ .hasleoncasa, .v9 })) @sizeOf(usize) else 0,
 
     // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b
     // and set this parameter accordingly.

lib/compiler_rt/elf/tls.zig

@@ -44,8 +44,9 @@ comptime {
 
 /// Represents an ELF TLS variant.
 ///
-/// In all variants, the TP and the TLS blocks must be aligned to the `p_align` value in the
-/// `PT.TLS` ELF program header. Everything else has natural alignment.
+/// In all variants, TLS blocks must be aligned to the `p_align` value in the `PT.TLS` ELF program
+/// header. The TP is usually similarly aligned, with one particular exception for the modified
+/// Variant I noted below. Everything else has natural alignment.
 ///
 /// The location of the DTV does not actually matter. For simplicity, we put it in the TLS area, but
 /// there is no actual ABI requirement that it reside there.
@@ -71,7 +72,8 @@ const Variant = enum {
     ///                               `-- The TP register points here (*inside* the TLS blocks).
     ///
     /// The offset from the start of the TLS blocks to the TP register is `current_tp_offset`. It
-    /// may be zero, in which case the TP register points to the start of the TLS blocks.
+    /// may be zero, in which case the TP register points to the end of the ABI TCB, which is
+    /// usually the start of the TLS blocks, but see `blocksGap`.
     ///
     /// The first (and only) word in the ABI TCB points to the DTV.
     I_modified,
@@ -145,6 +147,20 @@ const current_tp_offset = switch (native_arch) {
     else => 0,
 };
 
+/// Only used by the modified Variant I. Calculates the number of padding bytes between the end of
+/// the ABI TCB and the start of the TLS blocks.
+///
+/// Inline because TLS is not set up yet.
+inline fn blocksGap(alignment: usize) usize {
+    return switch (native_arch) {
+        // https://git.musl-libc.org/cgit/musl/commit/?id=de5536d827114ebc6b6db7800216610385663ad2
+        //
+        // This is arguably a binutils bug, but I guess we all just have to live with it now.
+        .or1k => alignForward(16, alignment) - 16,
+        else => 0,
+    };
+}
+
 /// Usually only used by the modified Variant I.
 const current_dtv_offset = switch (native_arch) {
     .m68k,
@@ -548,16 +564,18 @@ fn computeAreaDesc(phdrs: []elf.ElfN.Phdr) void {
             var l: usize = 0;
             dtv_offset = l;
             l += @sizeOf(Dtv);
-            // In this variant, the TLS blocks must begin immediately after the end of the ABI TCB,
-            // with the TP pointing to the beginning of the TLS blocks. Add padding so that the TP
-            // (`abi_tcb_offset`) is aligned to `align_factor` and the `ZigTcb` structure can be
-            // found by subtracting `@sizeOf(AbiTcb) + @sizeOf(ZigTcb)` from the TP.
-            const delta = (l + @sizeOf(ZigTcb) + @sizeOf(AbiTcb)) & (align_factor - 1);
+            // In this variant, the TLS blocks begin `blocksGap()` bytes (usually zero) after the
+            // end of the ABI TCB. Add padding so that the TLS blocks are aligned to `align_factor`
+            // and the `ZigTcb` structure can be found by subtracting
+            // `@sizeOf(AbiTcb) + @sizeOf(ZigTcb)` from the end of the ABI TCB.
+            const gap = blocksGap(align_factor);
+            const delta = (l + @sizeOf(ZigTcb) + @sizeOf(AbiTcb) + gap) & (align_factor - 1);
             if (delta > 0)
                 l += align_factor - delta;
             l += @sizeOf(ZigTcb);
             abi_tcb_offset = l;
             l += @sizeOf(AbiTcb);
+            l += gap;
             block_offset = l;
             l += block_size;
             break :blk l;
@@ -648,7 +666,8 @@ fn __zig_elf_static_tls_fill(area: [*]u8) callconv(.c) usize {
     // the pointer arithmetic involving the TP is done with wrapping semantics.
     return @intFromPtr(area) +% switch (current_variant) {
         .I_original, .II => area_info.abi_tcb.offset,
-        .I_modified => area_info.block.offset +% current_tp_offset,
+        // This expression must account for the `blocksGap() != 0` possibility.
+        .I_modified => area_info.abi_tcb.offset +% @sizeOf(AbiTcb) +% current_tp_offset,
     };
 }
 
@@ -745,6 +764,9 @@ fn __tls_get_addr(ti: *const TlsIndex) callconv(.c) *anyopaque {
     const tp = getThreadPointer();
     const block = switch (current_variant) {
         .I_original => tp -% area_info.abi_tcb.offset +% area_info.block.offset,
+        // For `blocksGap() != 0`, this intentionally computes the end of the ABI TCB rather than
+        // the beginning of the TLS blocks. The linker will include the `blocksGap()` in the offset
+        // written into `ti.offset`.
         .I_modified => tp -% current_tp_offset,
         // The `.I_original` approach would also work for `.II`, but there is an
         // alternative strategy which is one less operation:

lib/std/Build/Configuration.zig

@@ -1000,8 +1000,6 @@ pub const Step = extern struct {
             shared_memory: bool,
             link_eh_frame_hdr: bool,
             link_emit_relocs: bool,
-            link_function_sections: bool,
-            link_data_sections: bool,
             linker_dynamicbase: bool,
             link_z_notext: bool,
             link_z_relro: bool,
@@ -1012,6 +1010,7 @@ pub const Step = extern struct {
             force_load_objc: bool,
             discard_local_symbols: bool,
             mingw_unicode_entry_point: bool,
+            _: u2 = 0,
         };
 
         pub const Flags2 = packed struct(u32) {
@@ -1077,7 +1076,9 @@ pub const Step = extern struct {
             generated_llvm_ir: bool,
             generated_h: bool,
             incremental: DefaultingBool,
-            _: u7 = 0,
+            function_sections: DefaultingBool,
+            data_sections: DefaultingBool,
+            _: u3 = 0,
         };
 
         pub fn isDynamicLibrary(compile: *const Compile) bool {
@@ -2388,7 +2389,6 @@ pub const TargetQuery = struct {
         hexagon,
         hppa,
         hppa64,
-        kalimba,
         kvx,
         lanai,
         loongarch32,
@@ -2433,6 +2433,7 @@ pub const TargetQuery = struct {
         xcore,
         xtensa,
         xtensaeb,
+        z80,
 
         default,
 
@@ -2488,9 +2489,7 @@ pub const TargetQuery = struct {
         emscripten,
         wasi,
         amdhsa,
-        amdpal,
         cuda,
-        mesa3d,
         nvcl,
         opencl,
         opengl,

lib/std/Build/Serialize.zig

@@ -132,8 +132,6 @@ pub fn write(b: *std.Build, wc: *Configuration.Wip, writer: *std.Io.Writer) !voi
                             .shared_memory = c.shared_memory,
                             .link_eh_frame_hdr = c.link_eh_frame_hdr,
                             .link_emit_relocs = c.link_emit_relocs,
-                            .link_function_sections = c.link_function_sections,
-                            .link_data_sections = c.link_data_sections,
                             .linker_dynamicbase = c.linker_dynamicbase,
                             .link_z_notext = c.link_z_notext,
                             .link_z_relro = c.link_z_relro,
@@ -218,6 +216,8 @@ pub fn write(b: *std.Build, wc: *Configuration.Wip, writer: *std.Io.Writer) !voi
                             .generated_llvm_ir = c.generated_llvm_ir != .none,
                             .generated_h = c.generated_h != .none,
                             .incremental = .init(c.incremental),
+                            .function_sections = .init(c.function_sections),
+                            .data_sections = .init(c.data_sections),
                         },
                         .root_module = try s.addModule(c.root_module),
                         .root_name = try wc.addString(c.name),

lib/std/Build/Step/Compile.zig

@@ -109,11 +109,11 @@ link_emit_relocs: bool = false,
 
 /// Place every function in its own section so that unused ones may be
 /// safely garbage-collected during the linking phase.
-link_function_sections: bool = false,
+function_sections: ?bool = null,
 
-/// Place every data in its own section so that unused ones may be
+/// Place every datum in its own section so that unused ones may be
 /// safely garbage-collected during the linking phase.
-link_data_sections: bool = false,
+data_sections: ?bool = null,
 
 /// Remove functions and data that are unreachable by the entry point or
 /// exported symbols.

lib/std/Target.zig

@@ -62,9 +62,7 @@ pub const Os = struct {
         wasi,
 
         amdhsa,
-        amdpal,
         cuda,
-        mesa3d,
         nvcl,
         opencl,
         opengl,
@@ -171,8 +169,6 @@ pub const Os = struct {
 
                 .emscripten,
 
-                .mesa3d,
-
                 .ashetos,
                 => .none,
 
@@ -205,7 +201,6 @@ pub const Os = struct {
                 .wasi,
 
                 .amdhsa,
-                .amdpal,
                 .cuda,
                 .nvcl,
                 .opencl,
@@ -410,8 +405,6 @@ pub const Os = struct {
 
                 .emscripten,
 
-                .mesa3d,
-
                 .ashetos,
                 => .{ .none = {} },
 
@@ -668,12 +661,6 @@ pub const Os = struct {
                         .max = .{ .major = 7, .minor = 2, .patch = 3 },
                     },
                 },
-                .amdpal => .{
-                    .semver = .{
-                        .min = .{ .major = 1, .minor = 1, .patch = 0 },
-                        .max = .{ .major = 3, .minor = 5, .patch = 0 },
-                    },
-                },
                 .cuda => .{
                     .semver = .{
                         .min = .{ .major = 12, .minor = 5, .patch = 0 },
@@ -684,26 +671,32 @@ pub const Os = struct {
                 .opencl,
                 => .{
                     .semver = .{
-                        .min = .{ .major = 2, .minor = 2, .patch = 0 },
-                        .max = .{ .major = 3, .minor = 0, .patch = 19 },
+                        .min = .{ .major = 2, .minor = 1, .patch = 0 },
+                        .max = .{ .major = 3, .minor = 1, .patch = 19 },
                     },
                 },
                 .opengl => .{
                     .semver = .{
-                        .min = .{ .major = 4, .minor = 5, .patch = 0 },
+                        .min = .{ .major = 4, .minor = 6, .patch = 0 },
                         .max = .{ .major = 4, .minor = 6, .patch = 0 },
                     },
                 },
                 .tios => .{
-                    .semver = .{
-                        .min = .{ .major = 5, .minor = 0, .patch = 0 },
-                        .max = .{ .major = 5, .minor = 8, .patch = 4 },
+                    .semver = switch (arch) {
+                        .z80 => .{
+                            .min = .{ .major = 1, .minor = 3, .patch = 0 },
+                            .max = .{ .major = 4, .minor = 2, .patch = 0 },
+                        },
+                        else => .{
+                            .min = .{ .major = 5, .minor = 0, .patch = 0 },
+                            .max = .{ .major = 5, .minor = 8, .patch = 4 },
+                        },
                     },
                 },
                 .vulkan => .{
                     .semver = .{
-                        .min = .{ .major = 1, .minor = 2, .patch = 0 },
-                        .max = .{ .major = 1, .minor = 4, .patch = 352 },
+                        .min = .{ .major = 1, .minor = 0, .patch = 0 },
+                        .max = .{ .major = 1, .minor = 4, .patch = 366 },
                     },
                 },
             };
@@ -766,22 +759,21 @@ pub const bpf = @import("Target/bpf.zig");
 pub const csky = @import("Target/csky.zig");
 pub const hexagon = @import("Target/hexagon.zig");
 pub const hppa = @import("Target/hppa.zig");
-pub const kalimba = @import("Target/generic.zig");
 pub const kvx = @import("Target/kvx.zig");
 pub const lanai = @import("Target/lanai.zig");
 pub const loongarch = @import("Target/loongarch.zig");
 pub const m68k = @import("Target/m68k.zig");
-pub const m88k = @import("Target/generic.zig");
-pub const microblaze = @import("Target/generic.zig");
+pub const m88k = @import("Target/m88k.zig");
+pub const microblaze = @import("Target/microblaze.zig");
 pub const mips = @import("Target/mips.zig");
 pub const msp430 = @import("Target/msp430.zig");
 pub const nvptx = @import("Target/nvptx.zig");
-pub const or1k = @import("Target/generic.zig");
+pub const or1k = @import("Target/or1k.zig");
 pub const powerpc = @import("Target/powerpc.zig");
 pub const propeller = @import("Target/propeller.zig");
 pub const riscv = @import("Target/riscv.zig");
 pub const s390x = @import("Target/s390x.zig");
-pub const sh = @import("Target/generic.zig");
+pub const sh = @import("Target/sh.zig");
 pub const sparc = @import("Target/sparc.zig");
 pub const spirv = @import("Target/spirv.zig");
 pub const spork8 = @import("Target/generic.zig");
@@ -790,7 +782,7 @@ pub const wasm = @import("Target/wasm.zig");
 pub const x86 = @import("Target/x86.zig");
 pub const xcore = @import("Target/xcore.zig");
 pub const xtensa = @import("Target/xtensa.zig");
-pub const z80 = @import("Target/generic.zig");
+pub const z80 = @import("Target/z80.zig");
 
 pub const Abi = enum {
     none,
@@ -918,6 +910,8 @@ pub const Abi = enum {
                 // Soft float tends to be more common for MIPS.
                 .mips,
                 .mipsel,
+                .sh,
+                .sheb,
                 => .eabi,
                 else => .none,
             },
@@ -925,14 +919,19 @@ pub const Abi = enum {
                 .arm,
                 => .eabi,
                 .powerpc,
+                .sh,
                 => .eabihf,
                 else => .none,
             },
             .windows => .gnu,
             .uefi => .msvc,
+            .gba => .eabi,
             .@"3ds" => .eabihf,
             .wiiu => .eabihf,
-            .gba => .eabi,
+            .@"switch" => switch (arch) {
+                .arm => .eabihf,
+                else => .none,
+            },
             .psx => .eabi,
             .ps3 => .ilp32,
             .psp => .eabihf,
@@ -953,13 +952,10 @@ pub const Abi = enum {
             .tvos,
             .visionos,
             .watchos,
-            .@"switch",
             .ps4,
             .ps5,
             .amdhsa,
-            .amdpal,
             .cuda,
-            .mesa3d,
             .nvcl,
             .opencl,
             .opengl,
@@ -1097,10 +1093,8 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
         .avr => .AVR,
         .bpfeb, .bpfel => .BPF,
         .csky => .CSKY,
-        .ez80 => .Z80,
         .hexagon => .QDSP6,
         .hppa, .hppa64 => .PARISC,
-        .kalimba => .CSR_KALIMBA,
         .kvx => .KVX,
         .lanai => .LANAI,
         .loongarch32, .loongarch64 => .LOONGARCH,
@@ -1116,13 +1110,14 @@ pub fn toElfMachine(target: *const Target) std.elf.EM {
         .riscv32, .riscv32be, .riscv64, .riscv64be => .RISCV,
         .s390x => .S390,
         .sh, .sheb => .SH,
-        .sparc => if (target.cpu.hasAny(.sparc, &.{ .v8plus, .v9 })) .SPARC32PLUS else .SPARC,
+        .sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC,
         .sparc64 => .SPARCV9,
         .ve => .VE,
         .x86_16, .x86 => .@"386",
         .x86_64 => .X86_64,
         .xcore => .XCORE,
         .xtensa, .xtensaeb => .XTENSA,
+        .z80, .ez80 => .Z80,
 
         .nvptx,
         .nvptx64,
@@ -1166,7 +1161,6 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
         .hexagon,
         .hppa,
         .hppa64,
-        .kalimba,
         .kvx,
         .lanai,
         .m88k,
@@ -1190,6 +1184,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
         .sparc64,
         .spirv32,
         .spirv64,
+        .spork8,
         .thumbeb,
         .ve,
         .wasm32,
@@ -1198,7 +1193,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE {
         .xcore,
         .xtensa,
         .xtensaeb,
-        .spork8,
+        .z80,
         => .UNKNOWN,
     };
 }
@@ -1375,7 +1370,6 @@ pub const Cpu = struct {
         hexagon,
         hppa,
         hppa64,
-        kalimba,
         kvx,
         lanai,
         loongarch32,
@@ -1420,6 +1414,7 @@ pub const Cpu = struct {
         xcore,
         xtensa,
         xtensaeb,
+        z80,
 
         /// An architecture family can encompass multiple architectures as represented by `Arch`.
         /// For a given family tag, it is guaranteed that an `std.Target.<tag>` namespace exists
@@ -1435,7 +1430,6 @@ pub const Cpu = struct {
             csky,
             hexagon,
             hppa,
-            kalimba,
             kvx,
             lanai,
             loongarch,
@@ -1472,10 +1466,8 @@ pub const Cpu = struct {
                 .avr => .avr,
                 .bpfeb, .bpfel => .bpf,
                 .csky => .csky,
-                .ez80 => .z80,
                 .hexagon => .hexagon,
                 .hppa, .hppa64 => .hppa,
-                .kalimba => .kalimba,
                 .kvx => .kvx,
                 .lanai => .lanai,
                 .loongarch32, .loongarch64 => .loongarch,
@@ -1493,12 +1485,13 @@ pub const Cpu = struct {
                 .sh, .sheb => .sh,
                 .sparc, .sparc64 => .sparc,
                 .spirv32, .spirv64 => .spirv,
+                .spork8 => .spork8,
                 .ve => .ve,
                 .wasm32, .wasm64 => .wasm,
                 .x86_16, .x86, .x86_64 => .x86,
                 .xcore => .xcore,
                 .xtensa, .xtensaeb => .xtensa,
-                .spork8 => .spork8,
+                .z80, .ez80 => .z80,
             };
         }
 
@@ -1695,6 +1688,13 @@ pub const Cpu = struct {
             };
         }
 
+        pub inline fn isZ80(arch: Arch) bool {
+            return switch (arch) {
+                .z80, .ez80 => true,
+                else => false,
+            };
+        }
+
         pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) ?*const Cpu.Model {
             for (arch.allCpuModels()) |cpu| {
                 if (std.mem.eql(u8, cpu_name, cpu.name)) {
@@ -1713,8 +1713,8 @@ pub const Cpu = struct {
                 .avr,
                 .bpfel,
                 .csky,
+                .ez80,
                 .hexagon,
-                .kalimba,
                 .kvx,
                 .loongarch32,
                 .loongarch64,
@@ -1737,7 +1737,7 @@ pub const Cpu = struct {
                 .x86_64,
                 .xcore,
                 .xtensa,
-                .ez80,
+                .z80,
                 => .little,
 
                 .aarch64_be,
@@ -2027,12 +2027,16 @@ pub const Cpu = struct {
                 .spirv_mesh,
                 => &.{ .spirv32, .spirv64 },
 
+                .spork8,
+                => &.{.spork8},
+
+                .z80_cet,
+                .z80_tiflags,
+                => &.{.z80},
+
                 .ez80_cet,
                 .ez80_tiflags,
                 => &.{.ez80},
-
-                .spork8,
-                => &.{.spork8},
             };
         }
     };
@@ -2057,30 +2061,47 @@ pub const Cpu = struct {
         /// Clang compatibility is important, consider using `baseline` instead.
         pub fn generic(arch: Arch) *const Model {
             return switch (arch) {
+                .aarch64, .aarch64_be => &aarch64.cpu.armv8a,
                 .alpha => &alpha.cpu.ev4,
                 .amdgcn => &amdgcn.cpu.gfx600,
+                .arc, .arceb => &arc.cpu.arcv2,
                 .avr => &avr.cpu.avr1,
+                .bpfel, .bpfeb => &bpf.cpu.v1,
+                .csky => &csky.cpu.e2,
+                .hexagon => &hexagon.cpu.hexagonv60,
                 .hppa => &hppa.cpu.ts_1,
                 .hppa64 => &hppa.cpu.pa_8000,
                 .kvx => &kvx.cpu.coolidge_v1,
+                .lanai => &lanai.cpu.v11,
                 .loongarch32 => &loongarch.cpu.generic_la32,
                 .loongarch64 => &loongarch.cpu.generic_la64,
+                .m68k => &m68k.cpu.m68000,
+                .m88k => &m88k.cpu.m88000,
+                .microblaze, .microblazeel => &microblaze.cpu.v2_00,
                 .mips, .mipsel => &mips.cpu.mips32,
                 .mips64, .mips64el => &mips.cpu.mips64,
+                .msp430 => &msp430.cpu.msp430,
                 .nvptx, .nvptx64 => &nvptx.cpu.sm_20,
-                .powerpc, .powerpcle => &powerpc.cpu.ppc,
+                .or1k => &or1k.cpu.orbis32,
+                .powerpc, .powerpcle => &powerpc.cpu.ppc32,
                 .powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
                 .propeller => &propeller.cpu.p1,
-                .riscv32, .riscv32be => &riscv.cpu.generic_rv32,
-                .riscv64, .riscv64be => &riscv.cpu.generic_rv64,
+                .riscv32, .riscv32be => &riscv.cpu.rv32i,
+                .riscv64, .riscv64be => &riscv.cpu.rv64i,
+                .s390x => &s390x.cpu.arch8,
+                .sh, .sheb => &sh.cpu.sh1,
                 .sparc => &sparc.cpu.v7,
                 .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
+                .spirv32, .spirv64 => &spirv.cpu.v1_0,
                 .ve => &ve.cpu.ve10,
                 .wasm32, .wasm64 => &wasm.cpu.mvp,
                 .x86_16 => &x86.cpu.i86,
                 .x86 => &x86.cpu.i386,
                 .x86_64 => &x86.cpu.x86_64,
                 .xcore => &xcore.cpu.xs1b,
+                .xtensa, .xtensaeb => &xtensa.cpu.xtensa,
+                .z80 => &z80.cpu.z80,
+                .ez80 => &z80.cpu.ez80,
                 inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic,
             };
         }
@@ -2101,6 +2122,7 @@ pub const Cpu = struct {
                     .@"3ds" => &arm.cpu.mpcore,
                     .vita => &arm.cpu.kermit,
                     .gba => &arm.cpu.arm7tdmi,
+                    .@"switch" => &arm.cpu.cortex_a57,
                     else => &arm.cpu.baseline,
                 },
                 .thumb => switch (os.tag) {
@@ -2110,23 +2132,24 @@ pub const Cpu = struct {
                 },
                 .armeb, .thumbeb => &arm.cpu.baseline,
                 .aarch64 => switch (os.tag) {
-                    .haiku => &aarch64.cpu.cortex_a55,
+                    .haiku => &aarch64.cpu.armv8a,
                     .driverkit, .maccatalyst, .macos => &aarch64.cpu.apple_m1,
-                    .ios, .tvos => &aarch64.cpu.apple_a7,
+                    .ios => &aarch64.cpu.apple_a10,
+                    .tvos => &aarch64.cpu.apple_a7,
                     .visionos => &aarch64.cpu.apple_m2,
-                    .watchos => &aarch64.cpu.apple_s4,
+                    .watchos => &aarch64.cpu.apple_s6,
                     .@"switch" => &aarch64.cpu.cortex_a57,
                     else => generic(arch),
                 },
                 .avr => &avr.cpu.avr2,
                 .bpfel, .bpfeb => &bpf.cpu.v3,
-                .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model.
-                .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model.
+                .csky => &csky.cpu.ck810,
+                .hexagon => &hexagon.cpu.hexagonv68,
                 .hppa => &hppa.cpu.pa_7000,
-                .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model.
                 .loongarch32 => &loongarch.cpu.la32v1_0,
                 .loongarch64 => &loongarch.cpu.la64v1_0,
-                .m68k => &m68k.cpu.M68030,
+                .m68k => &m68k.cpu.m68030,
+                .microblaze, .microblazeel => &microblaze.cpu.v7_20,
                 .mips => &mips.cpu.mips32r2,
                 .mipsel => switch (os.tag) {
                     .psx => &mips.cpu.r3000a,
@@ -2138,8 +2161,8 @@ pub const Cpu = struct {
                     else => &mips.cpu.mips64r2,
                 },
                 .mips64el => &mips.cpu.mips64r2,
-                .msp430 => &msp430.cpu.msp430,
                 .nvptx, .nvptx64 => &nvptx.cpu.sm_52,
+                .or1k => &or1k.cpu.mor1kx,
                 .powerpc => switch (os.tag) {
                     .openbsd, .wiiu => &powerpc.cpu.@"750",
                     else => generic(arch),
@@ -2151,18 +2174,32 @@ pub const Cpu = struct {
                     else => generic(arch),
                 },
                 .powerpc64le => &powerpc.cpu.ppc64le,
-                .riscv32, .riscv32be => &riscv.cpu.baseline_rv32,
-                .riscv64, .riscv64be => &riscv.cpu.baseline_rv64,
+                .riscv32, .riscv32be => &riscv.cpu.rv32gc,
+                .riscv64, .riscv64be => &riscv.cpu.rv64gc,
                 .s390x => &s390x.cpu.arch11,
+                .sh, .sheb => switch (os.tag) {
+                    .netbsd => &sh.cpu.sh3,
+                    else => &sh.cpu.sh4,
+                },
                 .sparc => switch (os.tag) {
                     .linux => &sparc.cpu.v9, // glibc does not work with 'plain' v8.
                     else => &sparc.cpu.v8,
                 },
                 .sparc64 => &sparc.cpu.ultrasparc,
+                .spirv32 => switch (os.tag) {
+                    .opencl => &spirv.cpu.opencl_v2_1,
+                    .opengl => &spirv.cpu.opengl_v4_6,
+                    .vulkan => &spirv.cpu.vulkan_v1_0,
+                    else => generic(arch),
+                },
+                .spirv64 => switch (os.tag) {
+                    .opencl => &spirv.cpu.opencl_v2_1,
+                    .vulkan => &spirv.cpu.vulkan_v1_0,
+                    else => generic(arch),
+                },
                 .x86 => &x86.cpu.pentium4,
                 .x86_64 => switch (os.tag) {
-                    .driverkit, .maccatalyst => &x86.cpu.nehalem,
-                    .macos => &x86.cpu.core2,
+                    .driverkit, .maccatalyst, .macos => &x86.cpu.nehalem,
                     .ps4 => &x86.cpu.btver2,
                     .ps5 => &x86.cpu.znver2,
                     else => generic(arch),
@@ -2335,8 +2372,6 @@ pub fn requiresLibC(target: *const Target) bool {
         .gba,
         .psp,
         .vita,
-        .mesa3d,
-        .amdpal,
         .hurd,
         .wasi,
         .uefi,
@@ -2512,9 +2547,7 @@ pub const DynamicLinker = struct {
             .wasi,
 
             .amdhsa,
-            .amdpal,
             .cuda,
-            .mesa3d,
             .nvcl,
             .opencl,
             .opengl,
@@ -2959,9 +2992,7 @@ pub const DynamicLinker = struct {
             .wasi,
 
             .amdhsa,
-            .amdpal,
             .cuda,
-            .mesa3d,
             .nvcl,
             .opencl,
             .opengl,
@@ -2998,8 +3029,9 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
     return switch (cpu_arch) {
         .avr,
         .msp430,
-        .x86_16,
         .spork8,
+        .x86_16,
+        .z80,
         => 16,
 
         .ez80,
@@ -3012,7 +3044,6 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 {
         .csky,
         .hexagon,
         .hppa,
-        .kalimba,
         .lanai,
         .loongarch32,
         .m68k,
@@ -3076,6 +3107,7 @@ pub fn stackAlignment(target: *const Target) u16 {
     switch (target.cpu.arch) {
         .avr,
         .ez80,
+        .z80,
         => return 1,
 
         .m68k => if (target.os.tag != .netbsd) return 2,
@@ -3178,7 +3210,6 @@ pub fn cCharSignedness(target: *const Target) ?std.builtin.Signedness {
             .arc,
             .arceb,
             .csky,
-            .ez80,
             .hexagon,
             .msp430,
             .powerpc,
@@ -3272,6 +3303,12 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 {
                 .long, .ulong, .float => 32,
                 .double, .longdouble, .longlong, .ulonglong => 64,
             },
+            .z80 => switch (c_type) {
+                .char => 8,
+                .short, .ushort, .int, .uint => 16,
+                .long, .ulong, .float, .double => 32,
+                .longlong, .ulonglong, .longdouble => 64,
+            },
             .ez80 => switch (c_type) {
                 .char => 8,
                 .short, .ushort => 16,
@@ -3464,7 +3501,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 {
             },
         },
 
-        .cuda, .amdhsa, .amdpal, .mesa3d, .nvcl, .opencl, .vulkan => switch (c_type) {
+        .cuda, .amdhsa, .nvcl, .opencl, .vulkan => switch (c_type) {
             .char => 8,
             .short, .ushort => 16,
             .int, .uint, .float => 32,
@@ -3482,8 +3519,12 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 {
             .char => 8,
             .short, .ushort => 16,
             .int, .uint, .float => 32,
-            .long, .ulong, .longlong, .ulonglong, .double => 64,
-            .longdouble => 128,
+            .long, .ulong => target.ptrBitWidth(),
+            .longlong, .ulonglong, .double => 64,
+            .longdouble => switch (target.cpu.arch) {
+                .aarch64 => 128,
+                else => 64,
+            },
         },
 
         .psx, .ps3, .psp, .vita => switch (c_type) {
@@ -3511,6 +3552,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) ?u16 {
         .avr,
         .ez80,
         .spork8,
+        .z80,
         => return 1,
         .x86 => switch (target.os.tag) {
             .windows, .uefi => switch (c_type) {
@@ -3548,7 +3590,6 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) ?u16 {
             .arc,
             .arceb,
             .csky,
-            .kalimba,
             .microblaze,
             .microblazeel,
             .or1k,
@@ -3610,6 +3651,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) ?u16 {
             .avr,
             .ez80,
             .spork8,
+            .z80,
             => unreachable, // Handled above.
         }),
     );
@@ -3620,6 +3662,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
         .avr,
         .ez80,
         .spork8,
+        .z80,
         => 1,
 
         .msp430,
@@ -3629,7 +3672,6 @@ pub fn cMaxIntAlignment(target: *const Target) u16 {
         .arc,
         .arceb,
         .csky,
-        .kalimba,
         .microblaze,
         .microblazeel,
         .or1k,
@@ -3742,7 +3784,6 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
         .hexagon => .{ .hexagon_sysv = .{} },
         .hppa => .{ .hppa_elf = .{} },
         .hppa64 => .{ .hppa64_elf = .{} },
-        .kalimba => null,
         .kvx => switch (target.abi) {
             .ilp32 => .{ .kvx_ilp32 = .{} },
             else => .{ .kvx_lp64 = .{} },
@@ -3770,8 +3811,9 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention
         .amdgcn => .{ .amdgcn_device = .{} },
         .nvptx, .nvptx64 => .nvptx_device,
         .spirv32, .spirv64 => .spirv_device,
-        .ez80 => .ez80_cet,
         .spork8 => .spork8,
+        .z80 => .z80_cet,
+        .ez80 => .ez80_cet,
     };
 }
 

lib/std/Target/Query.zig

@@ -669,7 +669,7 @@ test parse {
     {
         const query = try Query.parse(.{
             .arch_os_abi = "aarch64-linux.3.10...4.4.1-gnu.2.27",
-            .cpu_features = "generic+v8a",
+            .cpu_features = "armv8a",
         });
         const target = try std.zig.system.resolveTargetQuery(io, query);
 

lib/std/Target/arc.zig

@@ -31,8 +31,8 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const generic: CpuModel = .{
-        .name = "generic",
+    pub const arcv2: CpuModel = .{
+        .name = "arcv2",
         .llvm_name = "generic",
         .features = featureSet(&[_]Feature{}),
     };

lib/std/Target/arm.zig

@@ -5,9 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature;
 const CpuModel = std.Target.Cpu.Model;
 
 pub const Feature = enum {
-    @"32bit",
     @"8msecext",
-    aapcs_frame_chain,
     aclass,
     acquire_release,
     aes,
@@ -16,7 +14,6 @@ pub const Feature = enum {
     avoid_muls,
     avoid_partial_cpsr,
     bf16,
-    big_endian_instructions,
     branch_align_64,
     cde,
     cdecp0,
@@ -29,17 +26,14 @@ pub const Feature = enum {
     cdecp7,
     cheap_predicable_cpsr,
     clrbhb,
-    cortex_a510,
     crc,
     crypto,
     d32,
     db,
     dfb,
-    disable_postra_scheduler,
     dont_widen_vmovs,
     dotprod,
     dsp,
-    execute_only,
     expand_fp_mlx,
     fix_cmse_cve_2021_35465,
     fix_cortex_a57_aes_1742098,
@@ -57,9 +51,6 @@ pub const Feature = enum {
     fullfp16,
     fuse_aes,
     fuse_literals,
-    harden_sls_blr,
-    harden_sls_nocomdat,
-    harden_sls_retbr,
     has_v4t,
     has_v5t,
     has_v5te,
@@ -96,10 +87,7 @@ pub const Feature = enum {
     iwmmxt,
     iwmmxt2,
     lob,
-    long_calls,
     loop_align,
-    m55,
-    m85,
     mclass,
     mp,
     muxed_units,
@@ -112,9 +100,7 @@ pub const Feature = enum {
     neon_fpmovs,
     neonfp,
     no_branch_predictor,
-    no_bti_at_return_twice,
-    no_movt,
-    no_neg_immediates,
+    no_unaligned_access,
     noarm,
     nonpipelined_vfp,
     pacbti,
@@ -124,10 +110,6 @@ pub const Feature = enum {
     prof_unpr,
     ras,
     rclass,
-    read_tp_tpidrprw,
-    read_tp_tpidruro,
-    read_tp_tpidrurw,
-    reserve_r9,
     ret_addr_stack,
     sb,
     sha2,
@@ -138,14 +120,9 @@ pub const Feature = enum {
     slow_vgetlni32,
     slowfpvfmx,
     slowfpvmlx,
-    soft_float,
     splat_vfp_neon,
-    strict_align,
     thumb2,
-    thumb_mode,
     trustzone,
-    use_mipipeliner,
-    use_misched,
     v2,
     v2a,
     v3,
@@ -218,21 +195,11 @@ pub const all_features = blk: {
     const len = @typeInfo(Feature).@"enum".field_names.len;
     std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
     var result: [len]CpuFeature = undefined;
-    result[@backingInt(Feature.@"32bit")] = .{
-        .llvm_name = "32bit",
-        .description = "Prefer 32-bit Thumb instrs",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.@"8msecext")] = .{
         .llvm_name = "8msecext",
         .description = "Enable support for ARMv8-M Security Extensions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.aapcs_frame_chain)] = .{
-        .llvm_name = "aapcs-frame-chain",
-        .description = "Create an AAPCS compliant frame chain",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.aclass)] = .{
         .llvm_name = "aclass",
         .description = "Is application profile ('A' series)",
@@ -277,11 +244,6 @@ pub const all_features = blk: {
             .neon,
         }),
     };
-    result[@backingInt(Feature.big_endian_instructions)] = .{
-        .llvm_name = "big-endian-instructions",
-        .description = "Expect instructions to be stored big-endian.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.branch_align_64)] = .{
         .llvm_name = "branch-align-64",
         .description = "Prefer 64-bit alignment for branch targets",
@@ -360,11 +322,6 @@ pub const all_features = blk: {
         .description = "Enable Clear BHB instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.cortex_a510)] = .{
-        .llvm_name = "cortex-a510",
-        .description = "Cortex-A510 ARM processors",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.crc)] = .{
         .llvm_name = "crc",
         .description = "Enable support for CRC instructions",
@@ -393,11 +350,6 @@ pub const all_features = blk: {
         .description = "Has full data barrier (dfb) instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.disable_postra_scheduler)] = .{
-        .llvm_name = "disable-postra-scheduler",
-        .description = "Don't schedule again after register allocation",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.dont_widen_vmovs)] = .{
         .llvm_name = "dont-widen-vmovs",
         .description = "Don't widen VMOVS to VMOVD",
@@ -415,11 +367,6 @@ pub const all_features = blk: {
         .description = "Supports DSP instructions in ARM and/or Thumb2",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.execute_only)] = .{
-        .llvm_name = "execute-only",
-        .description = "Enable the generation of execute only code.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.expand_fp_mlx)] = .{
         .llvm_name = "expand-fp-mlx",
         .description = "Expand VFP/NEON MLA/MLS instructions",
@@ -528,21 +475,6 @@ pub const all_features = blk: {
         .description = "CPU fuses literal generation operations",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.harden_sls_blr)] = .{
-        .llvm_name = "harden-sls-blr",
-        .description = "Harden against straight line speculation across indirect calls",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.harden_sls_nocomdat)] = .{
-        .llvm_name = "harden-sls-nocomdat",
-        .description = "Generate thunk code for SLS mitigation in the normal text section",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.harden_sls_retbr)] = .{
-        .llvm_name = "harden-sls-retbr",
-        .description = "Harden against straight line speculation across RETurn and BranchRegister instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.has_v4t)] = .{
         .llvm_name = "v4t",
         .description = "Support ARM v4T instructions",
@@ -799,26 +731,11 @@ pub const all_features = blk: {
         .description = "Enable Low Overhead Branch extensions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.long_calls)] = .{
-        .llvm_name = "long-calls",
-        .description = "Generate calls via indirect call instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.loop_align)] = .{
         .llvm_name = "loop-align",
         .description = "Prefer 32-bit alignment for branch targets",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.m55)] = .{
-        .llvm_name = "m55",
-        .description = "Cortex-M55 ARM processors",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.m85)] = .{
-        .llvm_name = "m85",
-        .description = "Cortex-M85 ARM processors",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.mclass)] = .{
         .llvm_name = "mclass",
         .description = "Is microcontroller profile ('M' series)",
@@ -889,19 +806,9 @@ pub const all_features = blk: {
         .description = "Has no branch predictor",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.no_bti_at_return_twice)] = .{
-        .llvm_name = "no-bti-at-return-twice",
-        .description = "Don't place a BTI instruction after a return-twice",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.no_movt)] = .{
-        .llvm_name = "no-movt",
-        .description = "Don't use movt/movw pairs for 32-bit imms",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.no_neg_immediates)] = .{
-        .llvm_name = "no-neg-immediates",
-        .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.",
+    result[@backingInt(Feature.no_unaligned_access)] = .{
+        .llvm_name = "strict-align",
+        .description = "Disallow all unaligned memory access",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@backingInt(Feature.noarm)] = .{
@@ -949,26 +856,6 @@ pub const all_features = blk: {
         .description = "Is realtime profile ('R' series)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.read_tp_tpidrprw)] = .{
-        .llvm_name = "read-tp-tpidrprw",
-        .description = "Reading thread pointer from TPIDRPRW register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.read_tp_tpidruro)] = .{
-        .llvm_name = "read-tp-tpidruro",
-        .description = "Reading thread pointer from TPIDRURO register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.read_tp_tpidrurw)] = .{
-        .llvm_name = "read-tp-tpidrurw",
-        .description = "Reading thread pointer from TPIDRURW register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r9)] = .{
-        .llvm_name = "reserve-r9",
-        .description = "Reserve R9, making it unavailable as GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.ret_addr_stack)] = .{
         .llvm_name = "ret-addr-stack",
         .description = "Has return address stack",
@@ -1021,11 +908,6 @@ pub const all_features = blk: {
         .description = "Disable VFP / NEON MAC instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.soft_float)] = .{
-        .llvm_name = "soft-float",
-        .description = "Use software floating point features.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.splat_vfp_neon)] = .{
         .llvm_name = "splat-vfp-neon",
         .description = "Splat register from VFP to NEON",
@@ -1033,69 +915,49 @@ pub const all_features = blk: {
             .dont_widen_vmovs,
         }),
     };
-    result[@backingInt(Feature.strict_align)] = .{
-        .llvm_name = "strict-align",
-        .description = "Disallow all unaligned memory access",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.thumb2)] = .{
         .llvm_name = "thumb2",
         .description = "Enable Thumb2 instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.thumb_mode)] = .{
-        .llvm_name = "thumb-mode",
-        .description = "Thumb mode",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.trustzone)] = .{
         .llvm_name = "trustzone",
         .description = "Enable support for TrustZone security extensions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.use_mipipeliner)] = .{
-        .llvm_name = "use-mipipeliner",
-        .description = "Use the MachinePipeliner",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.use_misched)] = .{
-        .llvm_name = "use-misched",
-        .description = "Use the MachineScheduler",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.v2)] = .{
         .llvm_name = null,
         .description = "ARMv2 architecture",
         .dependencies = featureSet(&[_]Feature{
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v2a)] = .{
         .llvm_name = null,
         .description = "ARMv2a architecture",
         .dependencies = featureSet(&[_]Feature{
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v3)] = .{
         .llvm_name = null,
         .description = "ARMv3 architecture",
         .dependencies = featureSet(&[_]Feature{
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v3m)] = .{
         .llvm_name = null,
         .description = "ARMv3m architecture",
         .dependencies = featureSet(&[_]Feature{
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v4)] = .{
         .llvm_name = "armv4",
         .description = "ARMv4 architecture",
         .dependencies = featureSet(&[_]Feature{
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v4t)] = .{
@@ -1103,7 +965,7 @@ pub const all_features = blk: {
         .description = "ARMv4t architecture",
         .dependencies = featureSet(&[_]Feature{
             .has_v4t,
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v5t)] = .{
@@ -1111,7 +973,7 @@ pub const all_features = blk: {
         .description = "ARMv5t architecture",
         .dependencies = featureSet(&[_]Feature{
             .has_v5t,
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v5te)] = .{
@@ -1119,7 +981,7 @@ pub const all_features = blk: {
         .description = "ARMv5te architecture",
         .dependencies = featureSet(&[_]Feature{
             .has_v5te,
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v5tej)] = .{
@@ -1127,7 +989,7 @@ pub const all_features = blk: {
         .description = "ARMv5tej architecture",
         .dependencies = featureSet(&[_]Feature{
             .has_v5te,
-            .strict_align,
+            .no_unaligned_access,
         }),
     };
     result[@backingInt(Feature.v6)] = .{
@@ -1167,9 +1029,8 @@ pub const all_features = blk: {
             .db,
             .has_v6m,
             .mclass,
+            .no_unaligned_access,
             .noarm,
-            .strict_align,
-            .thumb_mode,
         }),
     };
     result[@backingInt(Feature.v6sm)] = .{
@@ -1179,9 +1040,8 @@ pub const all_features = blk: {
             .db,
             .has_v6m,
             .mclass,
+            .no_unaligned_access,
             .noarm,
-            .strict_align,
-            .thumb_mode,
         }),
     };
     result[@backingInt(Feature.v6t2)] = .{
@@ -1213,7 +1073,6 @@ pub const all_features = blk: {
             .hwdiv,
             .mclass,
             .noarm,
-            .thumb_mode,
         }),
     };
     result[@backingInt(Feature.v7m)] = .{
@@ -1225,7 +1084,6 @@ pub const all_features = blk: {
             .hwdiv,
             .mclass,
             .noarm,
-            .thumb_mode,
         }),
     };
     result[@backingInt(Feature.v7r)] = .{
@@ -1282,7 +1140,6 @@ pub const all_features = blk: {
             .mclass,
             .noarm,
             .ras,
-            .thumb_mode,
         }),
     };
     result[@backingInt(Feature.v8_2a)] = .{
@@ -1441,9 +1298,8 @@ pub const all_features = blk: {
             .has_v8m,
             .hwdiv,
             .mclass,
+            .no_unaligned_access,
             .noarm,
-            .strict_align,
-            .thumb_mode,
         }),
     };
     result[@backingInt(Feature.v8m_main)] = .{
@@ -1456,7 +1312,6 @@ pub const all_features = blk: {
             .hwdiv,
             .mclass,
             .noarm,
-            .thumb_mode,
         }),
     };
     result[@backingInt(Feature.v8r)] = .{
@@ -2211,7 +2066,6 @@ pub const cpu = struct {
         .llvm_name = "cortex-m23",
         .features = featureSet(&[_]Feature{
             .no_branch_predictor,
-            .no_movt,
             .v8m,
         }),
     };
@@ -2221,7 +2075,6 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .loop_align,
             .no_branch_predictor,
-            .use_misched,
             .v7m,
         }),
     };
@@ -2235,7 +2088,6 @@ pub const cpu = struct {
             .no_branch_predictor,
             .slowfpvfmx,
             .slowfpvmlx,
-            .use_misched,
             .v8m_main,
         }),
     };
@@ -2248,7 +2100,6 @@ pub const cpu = struct {
             .no_branch_predictor,
             .slowfpvfmx,
             .slowfpvmlx,
-            .use_misched,
             .v8m_main,
         }),
     };
@@ -2260,7 +2111,6 @@ pub const cpu = struct {
             .no_branch_predictor,
             .slowfpvfmx,
             .slowfpvmlx,
-            .use_misched,
             .v7em,
         }),
     };
@@ -2273,7 +2123,6 @@ pub const cpu = struct {
             .mve1beat,
             .no_branch_predictor,
             .slowfpvmlx,
-            .use_misched,
             .v8_1m_main,
         }),
     };
@@ -2284,10 +2133,8 @@ pub const cpu = struct {
             .dsp,
             .fix_cmse_cve_2021_35465,
             .loop_align,
-            .m55,
             .no_branch_predictor,
             .slowfpvmlx,
-            .use_misched,
             .v8_1m_main,
         }),
     };
@@ -2296,8 +2143,6 @@ pub const cpu = struct {
         .llvm_name = "cortex-m7",
         .features = featureSet(&[_]Feature{
             .branch_align_64,
-            .use_mipipeliner,
-            .use_misched,
             .v7em,
         }),
     };
@@ -2308,8 +2153,6 @@ pub const cpu = struct {
             .@"8msecext",
             .branch_align_64,
             .dsp,
-            .m85,
-            .use_misched,
             .v8_1m_main,
         }),
     };
@@ -2353,7 +2196,6 @@ pub const cpu = struct {
         .llvm_name = "cortex-r52",
         .features = featureSet(&[_]Feature{
             .fpao,
-            .use_misched,
             .v8r,
         }),
     };
@@ -2362,7 +2204,6 @@ pub const cpu = struct {
         .llvm_name = "cortex-r52plus",
         .features = featureSet(&[_]Feature{
             .fpao,
-            .use_misched,
             .v8r,
         }),
     };
@@ -2419,12 +2260,10 @@ pub const cpu = struct {
             .avoid_movs_shop,
             .avoid_partial_cpsr,
             .crypto,
-            .disable_postra_scheduler,
             .neonfp,
             .ret_addr_stack,
             .slowfpvfmx,
             .slowfpvmlx,
-            .use_misched,
             .v8a,
             .zcz,
         }),
@@ -2438,7 +2277,7 @@ pub const cpu = struct {
     };
     pub const exynos_m1: CpuModel = .{
         .name = "exynos_m1",
-        .llvm_name = null,
+        .llvm_name = "generic",
         .features = featureSet(&[_]Feature{
             .crypto,
             .expand_fp_mlx,
@@ -2459,7 +2298,7 @@ pub const cpu = struct {
     };
     pub const exynos_m2: CpuModel = .{
         .name = "exynos_m2",
-        .llvm_name = null,
+        .llvm_name = "generic",
         .features = featureSet(&[_]Feature{
             .crypto,
             .expand_fp_mlx,
@@ -2658,7 +2497,6 @@ pub const cpu = struct {
         .llvm_name = "sc300",
         .features = featureSet(&[_]Feature{
             .no_branch_predictor,
-            .use_misched,
             .v7m,
         }),
     };
@@ -2672,7 +2510,6 @@ pub const cpu = struct {
             .no_branch_predictor,
             .slowfpvfmx,
             .slowfpvmlx,
-            .use_misched,
             .v8m_main,
         }),
     };
@@ -2685,7 +2522,6 @@ pub const cpu = struct {
             .mve1beat,
             .no_branch_predictor,
             .slowfpvmlx,
-            .use_misched,
             .v8_1m_main,
         }),
     };
@@ -2723,7 +2559,6 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .avoid_movs_shop,
             .avoid_partial_cpsr,
-            .disable_postra_scheduler,
             .hwdiv,
             .hwdiv_arm,
             .mp,
@@ -2738,7 +2573,6 @@ pub const cpu = struct {
             .slow_vgetlni32,
             .slowfpvfmx,
             .slowfpvmlx,
-            .use_misched,
             .v7a,
             .vfp4,
             .vmlx_hazards,

lib/std/Target/avr.zig

@@ -33,7 +33,6 @@ pub const Feature = enum {
     mul,
     rmw,
     smallstack,
-    special,
     spm,
     spmx,
     sram,
@@ -249,29 +248,6 @@ pub const all_features = blk: {
         .description = "The device has an 8-bit stack pointer",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.special)] = .{
-        .llvm_name = "special",
-        .description = "Enable use of the entire instruction set - used for debugging",
-        .dependencies = featureSet(&[_]Feature{
-            .addsubiw,
-            .@"break",
-            .des,
-            .eijmpcall,
-            .elpm,
-            .elpmx,
-            .ijmpcall,
-            .jmpcall,
-            .lpm,
-            .lpmx,
-            .memmappedregs,
-            .movw,
-            .mul,
-            .rmw,
-            .spm,
-            .spmx,
-            .sram,
-        }),
-    };
     result[@backingInt(Feature.spm)] = .{
         .llvm_name = "spm",
         .description = "The device supports the `SPM` instruction",

lib/std/Target/bpf.zig

@@ -5,8 +5,8 @@ const CpuFeature = std.Target.Cpu.Feature;
 const CpuModel = std.Target.Cpu.Model;
 
 pub const Feature = enum {
-    allows_misaligned_mem_access,
     alu32,
+    unaligned_access,
 };
 
 pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
@@ -18,16 +18,16 @@ pub const all_features = blk: {
     const len = @typeInfo(Feature).@"enum".field_names.len;
     std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
     var result: [len]CpuFeature = undefined;
-    result[@backingInt(Feature.allows_misaligned_mem_access)] = .{
-        .llvm_name = "allows-misaligned-mem-access",
-        .description = "Allows misaligned memory access",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.alu32)] = .{
         .llvm_name = "alu32",
         .description = "Enable ALU32 instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@backingInt(Feature.unaligned_access)] = .{
+        .llvm_name = "allows-misaligned-mem-access",
+        .description = "Allows misaligned memory access",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     const ti = @typeInfo(Feature);
     for (&result, 0..) |*elem, i| {
         elem.index = i;
@@ -37,16 +37,6 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{}),
-    };
-    pub const probe: CpuModel = .{
-        .name = "probe",
-        .llvm_name = "probe",
-        .features = featureSet(&[_]Feature{}),
-    };
     pub const v1: CpuModel = .{
         .name = "v1",
         .llvm_name = "v1",

lib/std/Target/csky.zig

@@ -35,17 +35,12 @@ pub const Feature = enum {
     fpuv3_hf,
     fpuv3_hi,
     fpuv3_sf,
-    hard_float,
-    hard_float_abi,
-    hard_tp,
     high_registers,
     hwdiv,
     istack,
     java,
     mp,
     mp1e2,
-    soft_tp,
-    stack_size,
     trust,
     vdsp2e3,
     vdsp2e60f,
@@ -229,21 +224,6 @@ pub const all_features = blk: {
         .description = "Enable FPUv3 single float instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.hard_float)] = .{
-        .llvm_name = "hard-float",
-        .description = "Use hard floating point features",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.hard_float_abi)] = .{
-        .llvm_name = "hard-float-abi",
-        .description = "Use hard floating point ABI to pass args",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.hard_tp)] = .{
-        .llvm_name = "hard-tp",
-        .description = "Enable TLS Pointer register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.high_registers)] = .{
         .llvm_name = "high-registers",
         .description = "Enable r16-r31 registers",
@@ -278,16 +258,6 @@ pub const all_features = blk: {
             .@"3e7",
         }),
     };
-    result[@backingInt(Feature.soft_tp)] = .{
-        .llvm_name = "soft-tp",
-        .description = "Disable TLS Pointer register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.stack_size)] = .{
-        .llvm_name = "stack-size",
-        .description = "Output stack size information",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.trust)] = .{
         .llvm_name = "trust",
         .description = "Enable trust instructions",
@@ -330,7 +300,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -353,7 +322,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -375,7 +343,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -397,7 +364,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -419,7 +385,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -442,7 +407,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -466,7 +430,6 @@ pub const cpu = struct {
             .fpuv3_hf,
             .fpuv3_hi,
             .fpuv3_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -489,7 +452,6 @@ pub const cpu = struct {
             .fpuv3_hf,
             .fpuv3_hi,
             .fpuv3_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2014,7 +1976,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2030,7 +1991,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2053,7 +2013,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2076,7 +2035,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2093,7 +2051,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2110,7 +2067,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2132,7 +2088,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2154,7 +2109,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2176,7 +2130,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2199,7 +2152,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2217,7 +2169,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2234,7 +2185,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2252,7 +2202,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2275,7 +2224,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2297,7 +2245,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2319,7 +2266,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2342,7 +2288,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2360,7 +2305,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2377,7 +2321,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2395,7 +2338,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2414,7 +2356,6 @@ pub const cpu = struct {
             .btst16,
             .cache,
             .dspe60,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2437,7 +2378,6 @@ pub const cpu = struct {
             .fpuv3_hf,
             .fpuv3_hi,
             .fpuv3_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2460,7 +2400,6 @@ pub const cpu = struct {
             .fpuv3_hf,
             .fpuv3_hi,
             .fpuv3_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2480,7 +2419,6 @@ pub const cpu = struct {
             .btst16,
             .cache,
             .dspe60,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2490,6 +2428,13 @@ pub const cpu = struct {
             .vdspv2,
         }),
     };
+    pub const e2: CpuModel = .{
+        .name = "e2",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .e2,
+        }),
+    };
     pub const e801: CpuModel = .{
         .name = "e801",
         .llvm_name = "e801",
@@ -2633,13 +2578,6 @@ pub const cpu = struct {
             .trust,
         }),
     };
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{
-            .btst16,
-        }),
-    };
     pub const @"i805": CpuModel = .{
         .name = "i805",
         .llvm_name = "i805",
@@ -2681,7 +2619,6 @@ pub const cpu = struct {
             .dsp1e2,
             .dspe60,
             .edsp,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,
@@ -2704,7 +2641,6 @@ pub const cpu = struct {
             .floate1,
             .fpuv2_df,
             .fpuv2_sf,
-            .hard_tp,
             .high_registers,
             .hwdiv,
             .mp,

lib/std/Target/hexagon.zig

@@ -7,8 +7,6 @@ const CpuModel = std.Target.Cpu.Model;
 pub const Feature = enum {
     audio,
     cabac,
-    compound,
-    duplex,
     hvx,
     hvx_ieee_fp,
     hvx_length128b,
@@ -26,50 +24,8 @@ pub const Feature = enum {
     hvxv75,
     hvxv79,
     hvxv81,
-    long_calls,
     mem_noshuf,
-    memops,
-    noreturn_stack_elim,
-    nvj,
-    nvs,
-    packets,
     prev65,
-    reserved_r10,
-    reserved_r11,
-    reserved_r12,
-    reserved_r13,
-    reserved_r14,
-    reserved_r15,
-    reserved_r16,
-    reserved_r17,
-    reserved_r18,
-    reserved_r19,
-    reserved_r20,
-    reserved_r21,
-    reserved_r22,
-    reserved_r23,
-    reserved_r24,
-    reserved_r25,
-    reserved_r26,
-    reserved_r27,
-    reserved_r28,
-    reserved_r6,
-    reserved_r7,
-    reserved_r8,
-    reserved_r9,
-    scs_reg_r16,
-    scs_reg_r17,
-    scs_reg_r18,
-    scs_reg_r19,
-    scs_reg_r20,
-    scs_reg_r21,
-    scs_reg_r22,
-    scs_reg_r23,
-    scs_reg_r24,
-    scs_reg_r25,
-    scs_reg_r26,
-    scs_reg_r27,
-    small_data,
     tinycore,
     v5,
     v55,
@@ -107,16 +63,6 @@ pub const all_features = blk: {
         .description = "Emit the CABAC instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.compound)] = .{
-        .llvm_name = "compound",
-        .description = "Use compound instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.duplex)] = .{
-        .llvm_name = "duplex",
-        .description = "Enable generation of duplex instruction",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.hvx)] = .{
         .llvm_name = "hvx",
         .description = "Hexagon HVX instructions",
@@ -125,7 +71,9 @@ pub const all_features = blk: {
     result[@backingInt(Feature.hvx_ieee_fp)] = .{
         .llvm_name = "hvx-ieee-fp",
         .description = "Hexagon HVX IEEE floating point instructions",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .hvxv68,
+        }),
     };
     result[@backingInt(Feature.hvx_length128b)] = .{
         .llvm_name = "hvx-length128b",
@@ -144,7 +92,9 @@ pub const all_features = blk: {
     result[@backingInt(Feature.hvx_qfloat)] = .{
         .llvm_name = "hvx-qfloat",
         .description = "Hexagon HVX QFloating point instructions",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .hvxv68,
+        }),
     };
     result[@backingInt(Feature.hvxv60)] = .{
         .llvm_name = "hvxv60",
@@ -231,230 +181,16 @@ pub const all_features = blk: {
             .hvxv79,
         }),
     };
-    result[@backingInt(Feature.long_calls)] = .{
-        .llvm_name = "long-calls",
-        .description = "Use constant-extended calls",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.mem_noshuf)] = .{
         .llvm_name = "mem_noshuf",
         .description = "Supports mem_noshuf feature",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.memops)] = .{
-        .llvm_name = "memops",
-        .description = "Use memop instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.noreturn_stack_elim)] = .{
-        .llvm_name = "noreturn-stack-elim",
-        .description = "Eliminate stack allocation in a noreturn function when possible",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.nvj)] = .{
-        .llvm_name = "nvj",
-        .description = "Support for new-value jumps",
-        .dependencies = featureSet(&[_]Feature{
-            .packets,
-        }),
-    };
-    result[@backingInt(Feature.nvs)] = .{
-        .llvm_name = "nvs",
-        .description = "Support for new-value stores",
-        .dependencies = featureSet(&[_]Feature{
-            .packets,
-        }),
-    };
-    result[@backingInt(Feature.packets)] = .{
-        .llvm_name = "packets",
-        .description = "Support for instruction packets",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.prev65)] = .{
         .llvm_name = "prev65",
         .description = "Support features deprecated in v65",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.reserved_r10)] = .{
-        .llvm_name = "reserved-r10",
-        .description = "Reserve register R10",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r11)] = .{
-        .llvm_name = "reserved-r11",
-        .description = "Reserve register R11",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r12)] = .{
-        .llvm_name = "reserved-r12",
-        .description = "Reserve register R12",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r13)] = .{
-        .llvm_name = "reserved-r13",
-        .description = "Reserve register R13",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r14)] = .{
-        .llvm_name = "reserved-r14",
-        .description = "Reserve register R14",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r15)] = .{
-        .llvm_name = "reserved-r15",
-        .description = "Reserve register R15",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r16)] = .{
-        .llvm_name = "reserved-r16",
-        .description = "Reserve register R16",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r17)] = .{
-        .llvm_name = "reserved-r17",
-        .description = "Reserve register R17",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r18)] = .{
-        .llvm_name = "reserved-r18",
-        .description = "Reserve register R18",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r19)] = .{
-        .llvm_name = "reserved-r19",
-        .description = "Reserve register R19",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r20)] = .{
-        .llvm_name = "reserved-r20",
-        .description = "Reserve register R20",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r21)] = .{
-        .llvm_name = "reserved-r21",
-        .description = "Reserve register R21",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r22)] = .{
-        .llvm_name = "reserved-r22",
-        .description = "Reserve register R22",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r23)] = .{
-        .llvm_name = "reserved-r23",
-        .description = "Reserve register R23",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r24)] = .{
-        .llvm_name = "reserved-r24",
-        .description = "Reserve register R24",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r25)] = .{
-        .llvm_name = "reserved-r25",
-        .description = "Reserve register R25",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r26)] = .{
-        .llvm_name = "reserved-r26",
-        .description = "Reserve register R26",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r27)] = .{
-        .llvm_name = "reserved-r27",
-        .description = "Reserve register R27",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r28)] = .{
-        .llvm_name = "reserved-r28",
-        .description = "Reserve register R28",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r6)] = .{
-        .llvm_name = "reserved-r6",
-        .description = "Reserve register R6",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r7)] = .{
-        .llvm_name = "reserved-r7",
-        .description = "Reserve register R7",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r8)] = .{
-        .llvm_name = "reserved-r8",
-        .description = "Reserve register R8",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserved_r9)] = .{
-        .llvm_name = "reserved-r9",
-        .description = "Reserve register R9",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r16)] = .{
-        .llvm_name = "scs-reg-r16",
-        .description = "Use register R16 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r17)] = .{
-        .llvm_name = "scs-reg-r17",
-        .description = "Use register R17 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r18)] = .{
-        .llvm_name = "scs-reg-r18",
-        .description = "Use register R18 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r19)] = .{
-        .llvm_name = "scs-reg-r19",
-        .description = "Use register R19 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r20)] = .{
-        .llvm_name = "scs-reg-r20",
-        .description = "Use register R20 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r21)] = .{
-        .llvm_name = "scs-reg-r21",
-        .description = "Use register R21 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r22)] = .{
-        .llvm_name = "scs-reg-r22",
-        .description = "Use register R22 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r23)] = .{
-        .llvm_name = "scs-reg-r23",
-        .description = "Use register R23 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r24)] = .{
-        .llvm_name = "scs-reg-r24",
-        .description = "Use register R24 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r25)] = .{
-        .llvm_name = "scs-reg-r25",
-        .description = "Use register R25 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r26)] = .{
-        .llvm_name = "scs-reg-r26",
-        .description = "Use register R26 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.scs_reg_r27)] = .{
-        .llvm_name = "scs-reg-r27",
-        .description = "Use register R27 as the shadow call stack pointer",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.small_data)] = .{
-        .llvm_name = "small-data",
-        .description = "Allow GP-relative addressing of global variables",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.tinycore)] = .{
         .llvm_name = "tinycore",
         .description = "Hexagon Tiny Core",
@@ -468,67 +204,93 @@ pub const all_features = blk: {
     result[@backingInt(Feature.v55)] = .{
         .llvm_name = "v55",
         .description = "Enable Hexagon V55 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v5,
+        }),
     };
     result[@backingInt(Feature.v60)] = .{
         .llvm_name = "v60",
         .description = "Enable Hexagon V60 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v55,
+        }),
     };
     result[@backingInt(Feature.v62)] = .{
         .llvm_name = "v62",
         .description = "Enable Hexagon V62 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v60,
+        }),
     };
     result[@backingInt(Feature.v65)] = .{
         .llvm_name = "v65",
         .description = "Enable Hexagon V65 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v62,
+        }),
     };
     result[@backingInt(Feature.v66)] = .{
         .llvm_name = "v66",
         .description = "Enable Hexagon V66 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v65,
+        }),
     };
     result[@backingInt(Feature.v67)] = .{
         .llvm_name = "v67",
         .description = "Enable Hexagon V67 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v66,
+        }),
     };
     result[@backingInt(Feature.v68)] = .{
         .llvm_name = "v68",
         .description = "Enable Hexagon V68 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v67,
+        }),
     };
     result[@backingInt(Feature.v69)] = .{
         .llvm_name = "v69",
         .description = "Enable Hexagon V69 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v68,
+        }),
     };
     result[@backingInt(Feature.v71)] = .{
         .llvm_name = "v71",
         .description = "Enable Hexagon V71 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v69,
+        }),
     };
     result[@backingInt(Feature.v73)] = .{
         .llvm_name = "v73",
         .description = "Enable Hexagon V73 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v71,
+        }),
     };
     result[@backingInt(Feature.v75)] = .{
         .llvm_name = "v75",
         .description = "Enable Hexagon V75 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v73,
+        }),
     };
     result[@backingInt(Feature.v79)] = .{
         .llvm_name = "v79",
         .description = "Enable Hexagon V79 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v75,
+        }),
     };
     result[@backingInt(Feature.v81)] = .{
         .llvm_name = "v81",
         .description = "Enable Hexagon V81 architecture",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .v79,
+        }),
     };
     result[@backingInt(Feature.zreg)] = .{
         .llvm_name = "zreg",
@@ -544,35 +306,12 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{
-            .cabac,
-            .compound,
-            .duplex,
-            .memops,
-            .nvj,
-            .nvs,
-            .prev65,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-        }),
-    };
     pub const hexagonv5: CpuModel = .{
         .name = "hexagonv5",
         .llvm_name = "hexagonv5",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
-            .memops,
-            .nvj,
-            .nvs,
             .prev65,
-            .small_data,
             .v5,
         }),
     };
@@ -581,14 +320,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv55",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
-            .memops,
-            .nvj,
-            .nvs,
             .prev65,
-            .small_data,
-            .v5,
             .v55,
         }),
     };
@@ -597,15 +329,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv60",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
-            .memops,
-            .nvj,
-            .nvs,
             .prev65,
-            .small_data,
-            .v5,
-            .v55,
             .v60,
         }),
     };
@@ -614,16 +338,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv62",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
-            .memops,
-            .nvj,
-            .nvs,
             .prev65,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
             .v62,
         }),
     };
@@ -632,17 +347,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv65",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
             .v65,
         }),
     };
@@ -651,18 +356,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv66",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
             .v66,
         }),
     };
@@ -671,19 +365,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv67",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
             .v67,
         }),
     };
@@ -692,18 +374,8 @@ pub const cpu = struct {
         .llvm_name = "hexagonv67t",
         .features = featureSet(&[_]Feature{
             .audio,
-            .compound,
             .mem_noshuf,
-            .memops,
-            .nvs,
-            .small_data,
             .tinycore,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
             .v67,
         }),
     };
@@ -712,20 +384,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv68",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
-            .v67,
             .v68,
         }),
     };
@@ -734,21 +393,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv69",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
-            .v67,
-            .v68,
             .v69,
         }),
     };
@@ -757,22 +402,7 @@ pub const cpu = struct {
         .llvm_name = "hexagonv71",
         .features = featureSet(&[_]Feature{
             .cabac,
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
-            .v67,
-            .v68,
-            .v69,
             .v71,
         }),
     };
@@ -781,21 +411,8 @@ pub const cpu = struct {
         .llvm_name = "hexagonv71t",
         .features = featureSet(&[_]Feature{
             .audio,
-            .compound,
             .mem_noshuf,
-            .memops,
-            .nvs,
-            .small_data,
             .tinycore,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
-            .v67,
-            .v68,
-            .v69,
             .v71,
         }),
     };
@@ -803,23 +420,7 @@ pub const cpu = struct {
         .name = "hexagonv73",
         .llvm_name = "hexagonv73",
         .features = featureSet(&[_]Feature{
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
-            .v67,
-            .v68,
-            .v69,
-            .v71,
             .v73,
         }),
     };
@@ -827,24 +428,7 @@ pub const cpu = struct {
         .name = "hexagonv75",
         .llvm_name = "hexagonv75",
         .features = featureSet(&[_]Feature{
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
-            .v67,
-            .v68,
-            .v69,
-            .v71,
-            .v73,
             .v75,
         }),
     };
@@ -852,25 +436,7 @@ pub const cpu = struct {
         .name = "hexagonv79",
         .llvm_name = "hexagonv79",
         .features = featureSet(&[_]Feature{
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
-            .v67,
-            .v68,
-            .v69,
-            .v71,
-            .v73,
-            .v75,
             .v79,
         }),
     };
@@ -878,26 +444,7 @@ pub const cpu = struct {
         .name = "hexagonv81",
         .llvm_name = "hexagonv81",
         .features = featureSet(&[_]Feature{
-            .compound,
-            .duplex,
             .mem_noshuf,
-            .memops,
-            .nvj,
-            .nvs,
-            .small_data,
-            .v5,
-            .v55,
-            .v60,
-            .v62,
-            .v65,
-            .v66,
-            .v67,
-            .v68,
-            .v69,
-            .v71,
-            .v73,
-            .v75,
-            .v79,
             .v81,
         }),
     };

lib/std/Target/lanai.zig

@@ -24,11 +24,6 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{}),
-    };
     pub const v11: CpuModel = .{
         .name = "v11",
         .llvm_name = "v11",

lib/std/Target/loongarch.zig

@@ -12,9 +12,6 @@ pub const Feature = enum {
     div32,
     f,
     frecipe,
-    la_global_with_abs,
-    la_global_with_pcrel,
-    la_local_with_abs,
     lam_bh,
     lamcas,
     lasx,
@@ -22,10 +19,8 @@ pub const Feature = enum {
     ld_seq_sa,
     lsx,
     lvz,
-    prefer_w_inst,
-    relax,
     scq,
-    ual,
+    unaligned_access,
 };
 
 pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
@@ -76,21 +71,6 @@ pub const all_features = blk: {
         .description = "Support frecipe.{s/d} and frsqrte.{s/d} instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.la_global_with_abs)] = .{
-        .llvm_name = "la-global-with-abs",
-        .description = "Expand la.global as la.abs",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.la_global_with_pcrel)] = .{
-        .llvm_name = "la-global-with-pcrel",
-        .description = "Expand la.global as la.pcrel",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.la_local_with_abs)] = .{
-        .llvm_name = "la-local-with-abs",
-        .description = "Expand la.local as la.abs",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.lam_bh)] = .{
         .llvm_name = "lam-bh",
         .description = "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions",
@@ -130,22 +110,12 @@ pub const all_features = blk: {
         .description = "'LVZ' (Loongson Virtualization Extension)",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.prefer_w_inst)] = .{
-        .llvm_name = "prefer-w-inst",
-        .description = "Prefer instructions with W suffix",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.relax)] = .{
-        .llvm_name = "relax",
-        .description = "Enable Linker relaxation",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.scq)] = .{
         .llvm_name = "scq",
         .description = "Support sc.q instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.ual)] = .{
+    result[@backingInt(Feature.unaligned_access)] = .{
         .llvm_name = "ual",
         .description = "Allow memory accesses to be unaligned",
         .dependencies = featureSet(&[_]Feature{}),
@@ -161,7 +131,7 @@ pub const all_features = blk: {
 pub const cpu = struct {
     pub const generic_la32: CpuModel = .{
         .name = "generic_la32",
-        .llvm_name = "generic-la32",
+        .llvm_name = null,
         .features = featureSet(&[_]Feature{
             .@"32bit",
         }),
@@ -173,12 +143,20 @@ pub const cpu = struct {
             .@"64bit",
         }),
     };
+    pub const la132: CpuModel = .{
+        .name = "la132",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .@"32bit",
+            .@"32s",
+        }),
+    };
     pub const la32rv1_0: CpuModel = .{
         .name = "la32rv1_0",
         .llvm_name = null,
         .features = featureSet(&[_]Feature{
             .@"32bit",
-            .ual,
+            .unaligned_access,
         }),
     };
     pub const la32v1_0: CpuModel = .{
@@ -188,7 +166,7 @@ pub const cpu = struct {
             .@"32bit",
             .@"32s",
             .d,
-            .ual,
+            .unaligned_access,
         }),
     };
     pub const la464: CpuModel = .{
@@ -199,7 +177,7 @@ pub const cpu = struct {
             .lasx,
             .lbt,
             .lvz,
-            .ual,
+            .unaligned_access,
         }),
     };
     pub const la64v1_0: CpuModel = .{
@@ -208,7 +186,7 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .@"64bit",
             .lsx,
-            .ual,
+            .unaligned_access,
         }),
     };
     pub const la64v1_1: CpuModel = .{
@@ -223,7 +201,7 @@ pub const cpu = struct {
             .ld_seq_sa,
             .lsx,
             .scq,
-            .ual,
+            .unaligned_access,
         }),
     };
     pub const la664: CpuModel = .{
@@ -240,7 +218,7 @@ pub const cpu = struct {
             .ld_seq_sa,
             .lvz,
             .scq,
-            .ual,
+            .unaligned_access,
         }),
     };
 };

lib/std/Target/m68k.zig

@@ -13,21 +13,6 @@ pub const Feature = enum {
     isa_68060,
     isa_68881,
     isa_68882,
-    reserve_a0,
-    reserve_a1,
-    reserve_a2,
-    reserve_a3,
-    reserve_a4,
-    reserve_a5,
-    reserve_a6,
-    reserve_d0,
-    reserve_d1,
-    reserve_d2,
-    reserve_d3,
-    reserve_d4,
-    reserve_d5,
-    reserve_d6,
-    reserve_d7,
 };
 
 pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
@@ -92,81 +77,6 @@ pub const all_features = blk: {
             .isa_68881,
         }),
     };
-    result[@backingInt(Feature.reserve_a0)] = .{
-        .llvm_name = "reserve-a0",
-        .description = "Reserve A0 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_a1)] = .{
-        .llvm_name = "reserve-a1",
-        .description = "Reserve A1 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_a2)] = .{
-        .llvm_name = "reserve-a2",
-        .description = "Reserve A2 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_a3)] = .{
-        .llvm_name = "reserve-a3",
-        .description = "Reserve A3 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_a4)] = .{
-        .llvm_name = "reserve-a4",
-        .description = "Reserve A4 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_a5)] = .{
-        .llvm_name = "reserve-a5",
-        .description = "Reserve A5 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_a6)] = .{
-        .llvm_name = "reserve-a6",
-        .description = "Reserve A6 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_d0)] = .{
-        .llvm_name = "reserve-d0",
-        .description = "Reserve D0 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_d1)] = .{
-        .llvm_name = "reserve-d1",
-        .description = "Reserve D1 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_d2)] = .{
-        .llvm_name = "reserve-d2",
-        .description = "Reserve D2 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_d3)] = .{
-        .llvm_name = "reserve-d3",
-        .description = "Reserve D3 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_d4)] = .{
-        .llvm_name = "reserve-d4",
-        .description = "Reserve D4 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_d5)] = .{
-        .llvm_name = "reserve-d5",
-        .description = "Reserve D5 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_d6)] = .{
-        .llvm_name = "reserve-d6",
-        .description = "Reserve D6 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_d7)] = .{
-        .llvm_name = "reserve-d7",
-        .description = "Reserve D7 register",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     const ti = @typeInfo(Feature);
     for (&result, 0..) |*elem, i| {
         elem.index = i;
@@ -176,50 +86,45 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{
-            .isa_68000,
-        }),
-    };
-    pub const M68000: CpuModel = .{
-        .name = "M68000",
+    pub const m68000: CpuModel = .{
+        .name = "m68000",
         .llvm_name = "M68000",
         .features = featureSet(&[_]Feature{
             .isa_68000,
         }),
     };
-    pub const M68010: CpuModel = .{
-        .name = "M68010",
+    pub const m68010: CpuModel = .{
+        .name = "m68010",
         .llvm_name = "M68010",
         .features = featureSet(&[_]Feature{
             .isa_68010,
         }),
     };
-    pub const M68020: CpuModel = .{
-        .name = "M68020",
+    pub const m68020: CpuModel = .{
+        .name = "m68020",
         .llvm_name = "M68020",
         .features = featureSet(&[_]Feature{
             .isa_68020,
+            .isa_68881,
         }),
     };
-    pub const M68030: CpuModel = .{
-        .name = "M68030",
+    pub const m68030: CpuModel = .{
+        .name = "m68030",
         .llvm_name = "M68030",
         .features = featureSet(&[_]Feature{
             .isa_68030,
+            .isa_68881,
         }),
     };
-    pub const M68040: CpuModel = .{
-        .name = "M68040",
+    pub const m68040: CpuModel = .{
+        .name = "m68040",
         .llvm_name = "M68040",
         .features = featureSet(&[_]Feature{
             .isa_68040,
         }),
     };
-    pub const M68060: CpuModel = .{
-        .name = "M68060",
+    pub const m68060: CpuModel = .{
+        .name = "m68060",
         .llvm_name = "M68060",
         .features = featureSet(&[_]Feature{
             .isa_68060,

lib/std/Target/m88k.zig

@@ -0,0 +1,83 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    isa_88110,
+    sfu1,
+    sfu2,
+    xmem_imm,
+    xrf,
+};
+
+pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).@"enum".field_names.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@backingInt(Feature.isa_88110)] = .{
+        .llvm_name = null,
+        .description = "Enable MC88110 additions to the base instruction set",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sfu1)] = .{
+        .llvm_name = null,
+        .description = "Enable floating-point unit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sfu2)] = .{
+        .llvm_name = null,
+        .description = "Enable graphics unit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.xmem_imm)] = .{
+        .llvm_name = null,
+        .description = "Enable xmem with 16-bit immediate offset",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.xrf)] = .{
+        .llvm_name = null,
+        .description = "Enable extended register file",
+        .dependencies = featureSet(&[_]Feature{
+            .sfu1,
+        }),
+    };
+    const ti = @typeInfo(Feature);
+    for (&result, 0..) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.@"enum".field_names[i];
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const m88000: CpuModel = .{
+        .name = "m88000",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sfu1,
+        }),
+    };
+    pub const m88100: CpuModel = .{
+        .name = "m88100",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sfu1,
+            .xmem_imm,
+        }),
+    };
+    pub const m88110: CpuModel = .{
+        .name = "m88110",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sfu2,
+            .xrf,
+        }),
+    };
+};

lib/std/Target/microblaze.zig

@@ -0,0 +1,301 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    barrel,
+    div,
+    fpu,
+    fpu2,
+    msr,
+    mul,
+    mul64,
+    pcmp,
+    pipe3,
+    pipe8,
+    reorder,
+    v10_0,
+    v7_20,
+    v8_10,
+    v8_30,
+};
+
+pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).@"enum".field_names.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@backingInt(Feature.barrel)] = .{
+        .llvm_name = null,
+        .description = "Enable barrel shift instructions (C_USE_BARREL)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.div)] = .{
+        .llvm_name = null,
+        .description = "Enable hardware divide instructions (C_USE_DIV)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.fpu)] = .{
+        .llvm_name = null,
+        .description = "Enable single-precision floating point instructions (C_USE_FPU >= 1)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.fpu2)] = .{
+        .llvm_name = null,
+        .description = "Enable floating point conversion and square root instructions (C_USE_FPU = 2)",
+        .dependencies = featureSet(&[_]Feature{
+            .fpu,
+        }),
+    };
+    result[@backingInt(Feature.msr)] = .{
+        .llvm_name = null,
+        .description = "Enable msrset and msrclr instructions (C_USE_MSR_INSTR)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.mul)] = .{
+        .llvm_name = null,
+        .description = "Enable 32-bit multiply instructions (C_USE_HW_MUL >= 1)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.mul64)] = .{
+        .llvm_name = null,
+        .description = "Enable multiply high instructions (C_USE_HW_MUL = 2)",
+        .dependencies = featureSet(&[_]Feature{
+            .mul,
+        }),
+    };
+    result[@backingInt(Feature.pcmp)] = .{
+        .llvm_name = null,
+        .description = "Enable pattern compare instructions, and clz with v8.10 (C_USE_PCMP_INSTR)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.pipe3)] = .{
+        .llvm_name = null,
+        .description = "Tune for the 3-stage pipeline (C_AREA_OPTIMIZED = 1)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.pipe8)] = .{
+        .llvm_name = null,
+        .description = "Tune for the 8-stage pipeline (C_AREA_OPTIMIZED = 2)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.reorder)] = .{
+        .llvm_name = null,
+        .description = "Enable byte-reversed load/store instructions, and swapb and swaph with v8.30 (C_USE_REORDER_INSTR)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.v10_0)] = .{
+        .llvm_name = null,
+        .description = "Enable MicroBlaze v10.0 instructions (bsefi and bsifi with barrel)",
+        .dependencies = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    result[@backingInt(Feature.v7_20)] = .{
+        .llvm_name = null,
+        .description = "Enable MicroBlaze v7.20 instructions (lwx, swx)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.v8_10)] = .{
+        .llvm_name = null,
+        .description = "Enable MicroBlaze v8.10 instructions (mbar)",
+        .dependencies = featureSet(&[_]Feature{
+            .v7_20,
+        }),
+    };
+    result[@backingInt(Feature.v8_30)] = .{
+        .llvm_name = null,
+        .description = "Enable MicroBlaze v8.30 instructions (swapb and swaph with reorder)",
+        .dependencies = featureSet(&[_]Feature{
+            .v8_10,
+        }),
+    };
+    const ti = @typeInfo(Feature);
+    for (&result, 0..) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.@"enum".field_names[i];
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const v10_0: CpuModel = .{
+        .name = "v10_0",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v10_0,
+        }),
+    };
+    pub const v11_0: CpuModel = .{
+        .name = "v11_0",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v10_0,
+        }),
+    };
+    pub const v2_00: CpuModel = .{
+        .name = "v2_00",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .pipe3,
+        }),
+    };
+    pub const v2_10: CpuModel = .{
+        .name = "v2_10",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .pipe3,
+        }),
+    };
+    pub const v3_00: CpuModel = .{
+        .name = "v3_00",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .pipe3,
+        }),
+    };
+    pub const v4_00: CpuModel = .{
+        .name = "v4_00",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .pipe3,
+        }),
+    };
+    pub const v5_00: CpuModel = .{
+        .name = "v5_00",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .msr,
+            .pcmp,
+        }),
+    };
+    pub const v6_00: CpuModel = .{
+        .name = "v6_00",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{}),
+    };
+    pub const v7_00: CpuModel = .{
+        .name = "v7_00",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{}),
+    };
+    pub const v7_10: CpuModel = .{
+        .name = "v7_10",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{}),
+    };
+    pub const v7_20: CpuModel = .{
+        .name = "v7_20",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v7_20,
+        }),
+    };
+    pub const v7_30: CpuModel = .{
+        .name = "v7_30",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v7_20,
+        }),
+    };
+    pub const v8_00: CpuModel = .{
+        .name = "v8_00",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .reorder,
+            .v7_20,
+        }),
+    };
+    pub const v8_10: CpuModel = .{
+        .name = "v8_10",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .reorder,
+            .v8_10,
+        }),
+    };
+    pub const v8_20: CpuModel = .{
+        .name = "v8_20",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .reorder,
+            .v8_10,
+        }),
+    };
+    pub const v8_30: CpuModel = .{
+        .name = "v8_30",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v8_40: CpuModel = .{
+        .name = "v8_40",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v8_50: CpuModel = .{
+        .name = "v8_50",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v9_0: CpuModel = .{
+        .name = "v9_0",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v9_1: CpuModel = .{
+        .name = "v9_1",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v9_2: CpuModel = .{
+        .name = "v9_2",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v9_3: CpuModel = .{
+        .name = "v9_3",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v9_4: CpuModel = .{
+        .name = "v9_4",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v9_5: CpuModel = .{
+        .name = "v9_5",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+    pub const v9_6: CpuModel = .{
+        .name = "v9_6",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .v8_30,
+        }),
+    };
+};

lib/std/Target/mips.zig

@@ -14,16 +14,8 @@ pub const Feature = enum {
     dspr3,
     eva,
     fix_r5900,
-    fp64,
-    fpxx,
     ginv,
-    gp64,
-    i6400,
-    i6500,
-    long_calls,
-    micromips,
     mips1,
-    mips16,
     mips2,
     mips3,
     mips32,
@@ -47,23 +39,12 @@ pub const Feature = enum {
     msa,
     mt,
     nan2008,
-    noabicalls,
+    no_unaligned_access,
     nomadd4,
-    nooddspreg,
-    notraps,
-    p5600,
-    ptr64,
     r5900,
     single_float,
-    soft_float,
-    strict_align,
-    sym32,
-    use_compact_branches,
-    use_indirect_jump_hazard,
-    use_tcc_in_div,
     vfpu,
     virt,
-    xgot,
 };
 
 pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
@@ -128,75 +109,27 @@ pub const all_features = blk: {
         .description = "Enable R5900 short loop erratum fix",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.fp64)] = .{
-        .llvm_name = "fp64",
-        .description = "Support 64-bit FP registers",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.fpxx)] = .{
-        .llvm_name = "fpxx",
-        .description = "Support for FPXX",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.ginv)] = .{
         .llvm_name = "ginv",
         .description = "Mips Global Invalidate ASE",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.gp64)] = .{
-        .llvm_name = "gp64",
-        .description = "General Purpose Registers are 64-bit wide",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.i6400)] = .{
-        .llvm_name = "i6400",
-        .description = "MIPS I6400 Processor",
-        .dependencies = featureSet(&[_]Feature{
-            .mips64r6,
-            .msa,
-        }),
-    };
-    result[@backingInt(Feature.i6500)] = .{
-        .llvm_name = "i6500",
-        .description = "MIPS I6500 Processor",
-        .dependencies = featureSet(&[_]Feature{
-            .mips64r6,
-            .msa,
-        }),
-    };
-    result[@backingInt(Feature.long_calls)] = .{
-        .llvm_name = "long-calls",
-        .description = "Disable use of the jal instruction",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.micromips)] = .{
-        .llvm_name = "micromips",
-        .description = "microMips mode",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.mips1)] = .{
         .llvm_name = "mips1",
-        .description = "Mips I ISA Support [highly experimental]",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.mips16)] = .{
-        .llvm_name = "mips16",
-        .description = "Mips16 mode",
+        .description = "Mips I ISA Support",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@backingInt(Feature.mips2)] = .{
         .llvm_name = "mips2",
-        .description = "Mips II ISA Support [highly experimental]",
+        .description = "Mips II ISA Support",
         .dependencies = featureSet(&[_]Feature{
             .mips1,
         }),
     };
     result[@backingInt(Feature.mips3)] = .{
         .llvm_name = "mips3",
-        .description = "MIPS III ISA Support [highly experimental]",
+        .description = "MIPS III ISA Support",
         .dependencies = featureSet(&[_]Feature{
-            .fp64,
-            .gp64,
             .mips2,
             .mips3_32,
             .mips3_32r2,
@@ -240,7 +173,6 @@ pub const all_features = blk: {
         .description = "Mips32r6 ISA Support [experimental]",
         .dependencies = featureSet(&[_]Feature{
             .abs2008,
-            .fp64,
             .mips32r5,
             .nan2008,
         }),
@@ -347,9 +279,9 @@ pub const all_features = blk: {
         .description = "IEEE 754-2008 NaN encoding",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.noabicalls)] = .{
-        .llvm_name = "noabicalls",
-        .description = "Disable SVR4-style position-independent code",
+    result[@backingInt(Feature.no_unaligned_access)] = .{
+        .llvm_name = "strict-align",
+        .description = "Disable unaligned load store for r6",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@backingInt(Feature.nomadd4)] = .{
@@ -357,28 +289,6 @@ pub const all_features = blk: {
         .description = "Disable 4-operand madd.fmt and related instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.nooddspreg)] = .{
-        .llvm_name = "nooddspreg",
-        .description = "Disable odd numbered single-precision registers",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.notraps)] = .{
-        .llvm_name = null,
-        .description = "Disable trap instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.p5600)] = .{
-        .llvm_name = "p5600",
-        .description = "The P5600 Processor",
-        .dependencies = featureSet(&[_]Feature{
-            .mips32r5,
-        }),
-    };
-    result[@backingInt(Feature.ptr64)] = .{
-        .llvm_name = "ptr64",
-        .description = "Pointers are 64-bit wide",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.r5900)] = .{
         .llvm_name = "r5900",
         .description = "R5900 (PS2 Emotion Engine) Support",
@@ -393,36 +303,6 @@ pub const all_features = blk: {
         .description = "Only supports single precision float",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.soft_float)] = .{
-        .llvm_name = "soft-float",
-        .description = "Does not support floating point instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.strict_align)] = .{
-        .llvm_name = "strict-align",
-        .description = "Disable unaligned load store for r6",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.sym32)] = .{
-        .llvm_name = "sym32",
-        .description = "Symbols are 32 bit on Mips64",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.use_compact_branches)] = .{
-        .llvm_name = "use-compact-branches",
-        .description = "Use compact branch instructions for MIPS32R6/MIPS64R6",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.use_indirect_jump_hazard)] = .{
-        .llvm_name = "use-indirect-jump-hazard",
-        .description = "Use indirect jump guards to prevent certain speculation based attacks",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.use_tcc_in_div)] = .{
-        .llvm_name = "use-tcc-in-div",
-        .description = "Force the assembler to use trapping",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.vfpu)] = .{
         .llvm_name = "vfpu",
         .description = "Enable vector FPU instructions",
@@ -433,11 +313,6 @@ pub const all_features = blk: {
         .description = "Mips Virtualization ASE",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.xgot)] = .{
-        .llvm_name = "xgot",
-        .description = "Assume 32-bit GOT",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     const ti = @typeInfo(Feature);
     for (&result, 0..) |*elem, i| {
         elem.index = i;
@@ -449,32 +324,27 @@ pub const all_features = blk: {
 pub const cpu = struct {
     pub const allegrex: CpuModel = .{
         .name = "allegrex",
-        .llvm_name = null,
+        .llvm_name = "mips2",
         .features = featureSet(&[_]Feature{
             .mips2,
-            .notraps,
             .single_float,
-        }),
-    };
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{
-            .mips32,
+            .vfpu,
         }),
     };
     pub const @"i6400": CpuModel = .{
         .name = "i6400",
         .llvm_name = "i6400",
         .features = featureSet(&[_]Feature{
-            .i6400,
+            .mips64r6,
+            .msa,
         }),
     };
     pub const @"i6500": CpuModel = .{
         .name = "i6500",
         .llvm_name = "i6500",
         .features = featureSet(&[_]Feature{
-            .i6500,
+            .mips64r6,
+            .msa,
         }),
     };
     pub const mips1: CpuModel = .{
@@ -540,13 +410,6 @@ pub const cpu = struct {
             .mips4,
         }),
     };
-    pub const mips5: CpuModel = .{
-        .name = "mips5",
-        .llvm_name = "mips5",
-        .features = featureSet(&[_]Feature{
-            .mips5,
-        }),
-    };
     pub const mips64: CpuModel = .{
         .name = "mips64",
         .llvm_name = "mips64",
@@ -600,16 +463,14 @@ pub const cpu = struct {
         .name = "p5600",
         .llvm_name = "p5600",
         .features = featureSet(&[_]Feature{
-            .p5600,
+            .mips32r5,
         }),
     };
     pub const r3000a: CpuModel = .{
         .name = "r3000a",
-        .llvm_name = null,
+        .llvm_name = "mips1",
         .features = featureSet(&[_]Feature{
             .mips1,
-            .notraps,
-            .soft_float,
         }),
     };
     pub const r5900: CpuModel = .{

lib/std/Target/msp430.zig

@@ -33,7 +33,9 @@ pub const all_features = blk: {
     result[@backingInt(Feature.hwmult32)] = .{
         .llvm_name = "hwmult32",
         .description = "Enable 32-bit hardware multiplier",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .hwmult16,
+        }),
     };
     result[@backingInt(Feature.hwmultf5)] = .{
         .llvm_name = "hwmultf5",
@@ -49,11 +51,6 @@ pub const all_features = blk: {
 };
 
 pub const cpu = struct {
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{}),
-    };
     pub const msp430: CpuModel = .{
         .name = "msp430",
         .llvm_name = "msp430",

lib/std/Target/or1k.zig

@@ -0,0 +1,253 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    adrp,
+    atomic,
+    cmov,
+    csync,
+    div,
+    ext,
+    ff1,
+    fl1,
+    mac,
+    madd_d,
+    madd_s,
+    msync,
+    mul,
+    muld,
+    no_addc,
+    no_sr_cy,
+    no_sr_ov,
+    no_sra,
+    orfpx32,
+    orfpx64a32,
+    psync,
+    ror,
+    sfimm,
+    sfun_s,
+    stod_dtos,
+};
+
+pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).@"enum".field_names.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@backingInt(Feature.adrp)] = .{
+        .llvm_name = null,
+        .description = "Enable PC-relative page address instruction (l.adrp)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.atomic)] = .{
+        .llvm_name = null,
+        .description = "Enable load-linked/store-conditional instructions (l.lwa, l.swa)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.cmov)] = .{
+        .llvm_name = null,
+        .description = "Enable conditional move instruction (l.cmov)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.csync)] = .{
+        .llvm_name = null,
+        .description = "Enable context synchronization instruction (l.csync)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.div)] = .{
+        .llvm_name = null,
+        .description = "Enable hardware divide instructions (l.div, l.divu)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.ext)] = .{
+        .llvm_name = null,
+        .description = "Enable sign/zero extension instructions (l.extbs, l.extbz, l.exths, l.exthz, l.extws, l.extwz)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.ff1)] = .{
+        .llvm_name = null,
+        .description = "Enable find first 1 instruction (l.ff1)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.fl1)] = .{
+        .llvm_name = null,
+        .description = "Enable find last 1 instruction (l.fl1)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.mac)] = .{
+        .llvm_name = null,
+        .description = "Enable multiply-accumulate instructions (l.mac, l.maci, l.macrc, l.macu, l.msb, l.msbu)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.madd_d)] = .{
+        .llvm_name = null,
+        .description = "Enable double-precision floating point multiply-add instruction (lf.madd.d)",
+        .dependencies = featureSet(&[_]Feature{
+            .orfpx64a32,
+        }),
+    };
+    result[@backingInt(Feature.madd_s)] = .{
+        .llvm_name = null,
+        .description = "Enable single-precision floating point multiply-add instruction (lf.madd.s)",
+        .dependencies = featureSet(&[_]Feature{
+            .orfpx32,
+        }),
+    };
+    result[@backingInt(Feature.msync)] = .{
+        .llvm_name = null,
+        .description = "Enable memory synchronization instruction (l.msync)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.mul)] = .{
+        .llvm_name = null,
+        .description = "Enable hardware multiply instructions (l.mul, l.muli, l.mulu)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.muld)] = .{
+        .llvm_name = null,
+        .description = "Enable widening multiply instructions (l.muld, l.muldu)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.no_addc)] = .{
+        .llvm_name = null,
+        .description = "Disable add with carry instructions (l.addc, l.addic)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.no_sr_cy)] = .{
+        .llvm_name = null,
+        .description = "Disable carry flag (SR[CY]) updates",
+        .dependencies = featureSet(&[_]Feature{
+            .no_addc,
+        }),
+    };
+    result[@backingInt(Feature.no_sr_ov)] = .{
+        .llvm_name = null,
+        .description = "Disable overflow flag (SR[OV]) updates",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.no_sra)] = .{
+        .llvm_name = null,
+        .description = "Disable arithmetic shift right instructions (l.sra, l.srai)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.orfpx32)] = .{
+        .llvm_name = null,
+        .description = "Enable single-precision floating point instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.orfpx64a32)] = .{
+        .llvm_name = null,
+        .description = "Enable double-precision floating point instructions on register pairs",
+        .dependencies = featureSet(&[_]Feature{
+            .sfun_s,
+        }),
+    };
+    result[@backingInt(Feature.psync)] = .{
+        .llvm_name = null,
+        .description = "Enable pipeline synchronization instruction (l.psync)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.ror)] = .{
+        .llvm_name = null,
+        .description = "Enable rotate right instructions (l.ror, l.rori)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sfimm)] = .{
+        .llvm_name = null,
+        .description = "Enable set flag with immediate instructions (l.sfeqi, l.sfnei, l.sfgtsi, l.sfgtui, l.sfgesi, l.sfgeui, l.sfltsi, l.sfltui, l.sflesi, l.sfleui)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sfun_s)] = .{
+        .llvm_name = null,
+        .description = "Enable unordered single-precision floating point comparison instructions (lf.sfueq.s, lf.sfune.s, lf.sfugt.s, lf.sfuge.s, lf.sfult.s, lf.sfule.s, lf.sfun.s)",
+        .dependencies = featureSet(&[_]Feature{
+            .orfpx32,
+        }),
+    };
+    result[@backingInt(Feature.stod_dtos)] = .{
+        .llvm_name = null,
+        .description = "Enable floating point precision conversion instructions (lf.stod.d, lf.dtos.d)",
+        .dependencies = featureSet(&[_]Feature{
+            .orfpx64a32,
+        }),
+    };
+    const ti = @typeInfo(Feature);
+    for (&result, 0..) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.@"enum".field_names[i];
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const ar100: CpuModel = .{
+        .name = "ar100",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .csync,
+            .ff1,
+            .msync,
+            .psync,
+            .sfimm,
+        }),
+    };
+    pub const marocchino: CpuModel = .{
+        .name = "marocchino",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .atomic,
+            .cmov,
+            .div,
+            .ext,
+            .ff1,
+            .fl1,
+            .msync,
+            .mul,
+            .orfpx64a32,
+            .ror,
+            .sfimm,
+        }),
+    };
+    pub const mor1kx: CpuModel = .{
+        .name = "mor1kx",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .atomic,
+            .cmov,
+            .div,
+            .ff1,
+            .fl1,
+            .msync,
+            .mul,
+            .sfimm,
+        }),
+    };
+    pub const or1200: CpuModel = .{
+        .name = "or1200",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .cmov,
+            .csync,
+            .div,
+            .ext,
+            .ff1,
+            .fl1,
+            .msync,
+            .mul,
+            .psync,
+            .sfimm,
+        }),
+    };
+    pub const orbis32: CpuModel = .{
+        .name = "orbis32",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{}),
+    };
+};

lib/std/Target/powerpc.zig

@@ -6,20 +6,15 @@ const CpuModel = std.Target.Cpu.Model;
 
 pub const Feature = enum {
     @"64bit",
-    @"64bit_support",
-    @"64bitregs",
-    allow_unaligned_fp_access,
     altivec,
     booke,
     bpermd,
     cmpb,
-    crbits,
     crypto,
     direct_move,
-    e500,
     efpu2,
     extdiv,
-    fast_MFLR,
+    fast_mflr,
     fcpsgn,
     float128,
     fpcvt,
@@ -43,12 +38,8 @@ pub const Feature = enum {
     fuse_wideimm,
     fuse_zeromove,
     fusion,
-    future_vector,
-    hard_float,
     htm,
     icbt,
-    invariant_function_descriptors,
-    isa_future_instructions,
     isa_v206_instructions,
     isa_v207_instructions,
     isa_v30_instructions,
@@ -56,7 +47,6 @@ pub const Feature = enum {
     isel,
     ldbrx,
     lfiwax,
-    longcall,
     mfocrf,
     mma,
     msync,
@@ -69,22 +59,15 @@ pub const Feature = enum {
     power8_vector,
     power9_altivec,
     power9_vector,
-    ppc4xx,
-    ppc6xx,
-    ppc_postra_sched,
-    ppc_prera_sched,
     predictable_select_expensive,
     prefix_instrs,
-    privileged,
     quadword_atomics,
     recipprec,
-    rop_protect,
-    secure_plt,
     slow_popcntd,
     spe,
     stfiwx,
     two_const_nr,
-    use_ptrgl_helper,
+    unaligned_fp_access,
     vectors_use_two_units,
     vsx,
 };
@@ -99,27 +82,10 @@ pub const all_features = blk: {
     std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
     var result: [len]CpuFeature = undefined;
     result[@backingInt(Feature.@"64bit")] = .{
-        .llvm_name = "64bit",
-        .description = "Enable 64-bit mode",
-        .dependencies = featureSet(&[_]Feature{
-            .@"64bit_support",
-        }),
-    };
-    result[@backingInt(Feature.@"64bit_support")] = .{
         .llvm_name = "64bit-support",
         .description = "Supports 64-bit instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.@"64bitregs")] = .{
-        .llvm_name = "64bitregs",
-        .description = "Enable 64-bit registers usage for ppc32 [beta]",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.allow_unaligned_fp_access)] = .{
-        .llvm_name = "allow-unaligned-fp-access",
-        .description = "CPU does not trap on unaligned FP access",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.altivec)] = .{
         .llvm_name = "altivec",
         .description = "Enable Altivec instructions",
@@ -144,11 +110,6 @@ pub const all_features = blk: {
         .description = "Enable the cmpb instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.crbits)] = .{
-        .llvm_name = "crbits",
-        .description = "Use condition-register bits individually",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.crypto)] = .{
         .llvm_name = "crypto",
         .description = "Enable POWER8 Crypto instructions",
@@ -163,11 +124,6 @@ pub const all_features = blk: {
             .vsx,
         }),
     };
-    result[@backingInt(Feature.e500)] = .{
-        .llvm_name = "e500",
-        .description = "Enable E500/E500mc instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.efpu2)] = .{
         .llvm_name = "efpu2",
         .description = "Enable Embedded Floating-Point APU 2 instructions",
@@ -180,7 +136,7 @@ pub const all_features = blk: {
         .description = "Enable extended divide instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.fast_MFLR)] = .{
+    result[@backingInt(Feature.fast_mflr)] = .{
         .llvm_name = "fast-MFLR",
         .description = "MFLR is a fast instruction",
         .dependencies = featureSet(&[_]Feature{}),
@@ -216,9 +172,7 @@ pub const all_features = blk: {
     result[@backingInt(Feature.fpu)] = .{
         .llvm_name = "fpu",
         .description = "Enable classic FPU instructions",
-        .dependencies = featureSet(&[_]Feature{
-            .hard_float,
-        }),
+        .dependencies = featureSet(&[_]Feature{}),
     };
     result[@backingInt(Feature.fre)] = .{
         .llvm_name = "fre",
@@ -344,19 +298,6 @@ pub const all_features = blk: {
         .description = "Target supports instruction fusion",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.future_vector)] = .{
-        .llvm_name = "future-vector",
-        .description = "Enable Future vector instructions",
-        .dependencies = featureSet(&[_]Feature{
-            .isa_future_instructions,
-            .power10_vector,
-        }),
-    };
-    result[@backingInt(Feature.hard_float)] = .{
-        .llvm_name = "hard-float",
-        .description = "Enable floating-point instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.htm)] = .{
         .llvm_name = "htm",
         .description = "Enable Hardware Transactional Memory instructions",
@@ -367,18 +308,6 @@ pub const all_features = blk: {
         .description = "Enable icbt instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.invariant_function_descriptors)] = .{
-        .llvm_name = "invariant-function-descriptors",
-        .description = "Assume function descriptors are invariant",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.isa_future_instructions)] = .{
-        .llvm_name = "isa-future-instructions",
-        .description = "Enable instructions for Future ISA.",
-        .dependencies = featureSet(&[_]Feature{
-            .isa_v31_instructions,
-        }),
-    };
     result[@backingInt(Feature.isa_v206_instructions)] = .{
         .llvm_name = "isa-v206-instructions",
         .description = "Enable instructions in ISA 2.06.",
@@ -420,11 +349,6 @@ pub const all_features = blk: {
             .fpu,
         }),
     };
-    result[@backingInt(Feature.longcall)] = .{
-        .llvm_name = "longcall",
-        .description = "Always use indirect calls",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.mfocrf)] = .{
         .llvm_name = "mfocrf",
         .description = "Enable the MFOCRF instruction",
@@ -510,26 +434,6 @@ pub const all_features = blk: {
             .power9_altivec,
         }),
     };
-    result[@backingInt(Feature.ppc4xx)] = .{
-        .llvm_name = "ppc4xx",
-        .description = "Enable PPC 4xx instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.ppc6xx)] = .{
-        .llvm_name = "ppc6xx",
-        .description = "Enable PPC 6xx instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.ppc_postra_sched)] = .{
-        .llvm_name = "ppc-postra-sched",
-        .description = "Use PowerPC post-RA scheduling strategy",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.ppc_prera_sched)] = .{
-        .llvm_name = "ppc-prera-sched",
-        .description = "Use PowerPC pre-RA scheduling strategy",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.predictable_select_expensive)] = .{
         .llvm_name = "predictable-select-expensive",
         .description = "Prefer likely predicted branches over selects",
@@ -542,11 +446,6 @@ pub const all_features = blk: {
             .isa_v31_instructions,
         }),
     };
-    result[@backingInt(Feature.privileged)] = .{
-        .llvm_name = "privileged",
-        .description = "Add privileged instructions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.quadword_atomics)] = .{
         .llvm_name = "quadword-atomics",
         .description = "Enable lqarx and stqcx.",
@@ -557,16 +456,6 @@ pub const all_features = blk: {
         .description = "Assume higher precision reciprocal estimates",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.rop_protect)] = .{
-        .llvm_name = "rop-protect",
-        .description = "Add ROP protect",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.secure_plt)] = .{
-        .llvm_name = "secure-plt",
-        .description = "Enable secure plt mode",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.slow_popcntd)] = .{
         .llvm_name = "slow-popcntd",
         .description = "Has slow popcnt[dw] instructions",
@@ -575,9 +464,7 @@ pub const all_features = blk: {
     result[@backingInt(Feature.spe)] = .{
         .llvm_name = "spe",
         .description = "Enable SPE instructions",
-        .dependencies = featureSet(&[_]Feature{
-            .hard_float,
-        }),
+        .dependencies = featureSet(&[_]Feature{}),
     };
     result[@backingInt(Feature.stfiwx)] = .{
         .llvm_name = "stfiwx",
@@ -591,9 +478,9 @@ pub const all_features = blk: {
         .description = "Requires two constant Newton-Raphson computation",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.use_ptrgl_helper)] = .{
-        .llvm_name = "use-ptrgl-helper",
-        .description = "Use ._ptrgl for indirect calls",
+    result[@backingInt(Feature.unaligned_fp_access)] = .{
+        .llvm_name = "allow-unaligned-fp-access",
+        .description = "CPU does not trap on unaligned FP access",
         .dependencies = featureSet(&[_]Feature{}),
     };
     result[@backingInt(Feature.vectors_use_two_units)] = .{
@@ -729,7 +616,7 @@ pub const cpu = struct {
         .name = "970",
         .llvm_name = "970",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .fres,
             .frsqrte,
@@ -742,7 +629,7 @@ pub const cpu = struct {
         .name = "a2",
         .llvm_name = "a2",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .booke,
             .cmpb,
             .fcpsgn,
@@ -765,9 +652,9 @@ pub const cpu = struct {
     };
     pub const cell: CpuModel = .{
         .name = "cell",
-        .llvm_name = null,
+        .llvm_name = "970",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .fres,
             .frsqrte,
@@ -794,20 +681,11 @@ pub const cpu = struct {
             .stfiwx,
         }),
     };
-    pub const e500v2: CpuModel = .{
-        .name = "e500v2",
-        .llvm_name = null,
-        .features = featureSet(&[_]Feature{
-            .efpu2,
-            .isel,
-            .msync,
-        }),
-    };
     pub const e5500: CpuModel = .{
         .name = "e5500",
         .llvm_name = "e5500",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .booke,
             .isel,
             .mfocrf,
@@ -816,61 +694,20 @@ pub const cpu = struct {
     };
     pub const e6500: CpuModel = .{
         .name = "e6500",
-        .llvm_name = null,
+        .llvm_name = "e5500",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .booke,
-            .isel,
-            .mfocrf,
-            .stfiwx,
-        }),
-    };
-    pub const future: CpuModel = .{
-        .name = "future",
-        .llvm_name = "future",
-        .features = featureSet(&[_]Feature{
-            .@"64bit_support",
-            .allow_unaligned_fp_access,
             .bpermd,
             .cmpb,
-            .crbits,
-            .crypto,
-            .direct_move,
-            .extdiv,
-            .fast_MFLR,
-            .fcpsgn,
-            .fpcvt,
-            .fprnd,
-            .fre,
             .fres,
             .frsqrte,
-            .frsqrtes,
-            .fsqrt,
-            .fuse_add_logical,
-            .fuse_arith_add,
-            .fuse_logical,
-            .fuse_logical_add,
-            .fuse_sha3,
-            .fuse_store,
-            .future_vector,
-            .icbt,
-            .isa_v206_instructions,
             .isel,
-            .ldbrx,
-            .lfiwax,
             .mfocrf,
-            .mma,
             .partword_atomics,
-            .pcrelative_memops,
             .popcntd,
-            .ppc_postra_sched,
-            .ppc_prera_sched,
-            .predictable_select_expensive,
-            .quadword_atomics,
-            .recipprec,
             .stfiwx,
-            .two_const_nr,
         }),
     };
     pub const g3: CpuModel = .{
@@ -903,7 +740,7 @@ pub const cpu = struct {
         .name = "g5",
         .llvm_name = "g5",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .fres,
             .frsqrte,
@@ -912,25 +749,16 @@ pub const cpu = struct {
             .stfiwx,
         }),
     };
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{
-            .hard_float,
-        }),
-    };
-    pub const ppc: CpuModel = .{
-        .name = "ppc",
-        .llvm_name = "ppc",
-        .features = featureSet(&[_]Feature{
-            .hard_float,
-        }),
+    pub const ppc32: CpuModel = .{
+        .name = "ppc32",
+        .llvm_name = "ppc32",
+        .features = featureSet(&[_]Feature{}),
     };
     pub const ppc64: CpuModel = .{
         .name = "ppc64",
         .llvm_name = "ppc64",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .fres,
             .frsqrte,
@@ -943,11 +771,9 @@ pub const cpu = struct {
         .name = "ppc64le",
         .llvm_name = "ppc64le",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
-            .allow_unaligned_fp_access,
+            .@"64bit",
             .bpermd,
             .cmpb,
-            .crbits,
             .crypto,
             .direct_move,
             .extdiv,
@@ -977,21 +803,20 @@ pub const cpu = struct {
             .recipprec,
             .stfiwx,
             .two_const_nr,
+            .unaligned_fp_access,
         }),
     };
     pub const pwr10: CpuModel = .{
         .name = "pwr10",
         .llvm_name = "pwr10",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
-            .allow_unaligned_fp_access,
+            .@"64bit",
             .bpermd,
             .cmpb,
-            .crbits,
             .crypto,
             .direct_move,
             .extdiv,
-            .fast_MFLR,
+            .fast_mflr,
             .fcpsgn,
             .fpcvt,
             .fprnd,
@@ -1017,28 +842,25 @@ pub const cpu = struct {
             .pcrelative_memops,
             .popcntd,
             .power10_vector,
-            .ppc_postra_sched,
-            .ppc_prera_sched,
             .predictable_select_expensive,
             .quadword_atomics,
             .recipprec,
             .stfiwx,
             .two_const_nr,
+            .unaligned_fp_access,
         }),
     };
     pub const pwr11: CpuModel = .{
         .name = "pwr11",
         .llvm_name = "pwr11",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
-            .allow_unaligned_fp_access,
+            .@"64bit",
             .bpermd,
             .cmpb,
-            .crbits,
             .crypto,
             .direct_move,
             .extdiv,
-            .fast_MFLR,
+            .fast_mflr,
             .fcpsgn,
             .fpcvt,
             .fprnd,
@@ -1064,20 +886,19 @@ pub const cpu = struct {
             .pcrelative_memops,
             .popcntd,
             .power10_vector,
-            .ppc_postra_sched,
-            .ppc_prera_sched,
             .predictable_select_expensive,
             .quadword_atomics,
             .recipprec,
             .stfiwx,
             .two_const_nr,
+            .unaligned_fp_access,
         }),
     };
     pub const pwr3: CpuModel = .{
         .name = "pwr3",
         .llvm_name = "pwr3",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .fres,
             .frsqrte,
@@ -1089,7 +910,7 @@ pub const cpu = struct {
         .name = "pwr4",
         .llvm_name = "pwr4",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .fres,
             .frsqrte,
@@ -1102,7 +923,7 @@ pub const cpu = struct {
         .name = "pwr5",
         .llvm_name = "pwr5",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .fre,
             .fres,
@@ -1117,7 +938,7 @@ pub const cpu = struct {
         .name = "pwr5x",
         .llvm_name = "pwr5x",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .fprnd,
             .fre,
@@ -1133,7 +954,7 @@ pub const cpu = struct {
         .name = "pwr6",
         .llvm_name = "pwr6",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .cmpb,
             .fcpsgn,
@@ -1153,7 +974,7 @@ pub const cpu = struct {
         .name = "pwr6x",
         .llvm_name = "pwr6x",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
+            .@"64bit",
             .altivec,
             .cmpb,
             .fcpsgn,
@@ -1173,8 +994,7 @@ pub const cpu = struct {
         .name = "pwr7",
         .llvm_name = "pwr7",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
-            .allow_unaligned_fp_access,
+            .@"64bit",
             .bpermd,
             .cmpb,
             .extdiv,
@@ -1195,6 +1015,7 @@ pub const cpu = struct {
             .recipprec,
             .stfiwx,
             .two_const_nr,
+            .unaligned_fp_access,
             .vsx,
         }),
     };
@@ -1202,11 +1023,9 @@ pub const cpu = struct {
         .name = "pwr8",
         .llvm_name = "pwr8",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
-            .allow_unaligned_fp_access,
+            .@"64bit",
             .bpermd,
             .cmpb,
-            .crbits,
             .crypto,
             .direct_move,
             .extdiv,
@@ -1236,17 +1055,16 @@ pub const cpu = struct {
             .recipprec,
             .stfiwx,
             .two_const_nr,
+            .unaligned_fp_access,
         }),
     };
     pub const pwr9: CpuModel = .{
         .name = "pwr9",
         .llvm_name = "pwr9",
         .features = featureSet(&[_]Feature{
-            .@"64bit_support",
-            .allow_unaligned_fp_access,
+            .@"64bit",
             .bpermd,
             .cmpb,
-            .crbits,
             .crypto,
             .direct_move,
             .extdiv,
@@ -1268,13 +1086,12 @@ pub const cpu = struct {
             .partword_atomics,
             .popcntd,
             .power9_vector,
-            .ppc_postra_sched,
-            .ppc_prera_sched,
             .predictable_select_expensive,
             .quadword_atomics,
             .recipprec,
             .stfiwx,
             .two_const_nr,
+            .unaligned_fp_access,
             .vectors_use_two_units,
         }),
     };

lib/std/Target/sh.zig

@@ -0,0 +1,236 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    cas,
+    dsp,
+    dynshift,
+    fpu,
+    fsca,
+    fsrra,
+    mmu,
+    sh2,
+    sh2a,
+    sh3,
+    sh4,
+    sh4a,
+};
+
+pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).@"enum".field_names.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@backingInt(Feature.cas)] = .{
+        .llvm_name = null,
+        .description = "Enable cas.l instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.dsp)] = .{
+        .llvm_name = null,
+        .description = "Enable DSP extension",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.dynshift)] = .{
+        .llvm_name = null,
+        .description = "Enable dynamic shift instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.fpu)] = .{
+        .llvm_name = null,
+        .description = "Enable floating point unit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.fsca)] = .{
+        .llvm_name = null,
+        .description = "Enable fsca instruction",
+        .dependencies = featureSet(&[_]Feature{
+            .fpu,
+        }),
+    };
+    result[@backingInt(Feature.fsrra)] = .{
+        .llvm_name = null,
+        .description = "Enable fsrra instruction",
+        .dependencies = featureSet(&[_]Feature{
+            .fpu,
+        }),
+    };
+    result[@backingInt(Feature.mmu)] = .{
+        .llvm_name = null,
+        .description = "Enable memory management unit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sh2)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-2 instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sh2a)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-2A instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .dynshift,
+            .sh2,
+        }),
+    };
+    result[@backingInt(Feature.sh3)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-3 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .dynshift,
+            .sh2,
+        }),
+    };
+    result[@backingInt(Feature.sh4)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-4 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .sh3,
+        }),
+    };
+    result[@backingInt(Feature.sh4a)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-4A instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .sh4,
+        }),
+    };
+    const ti = @typeInfo(Feature);
+    for (&result, 0..) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.@"enum".field_names[i];
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const j2: CpuModel = .{
+        .name = "j2",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .cas,
+            .dynshift,
+            .sh2,
+        }),
+    };
+    pub const sh1: CpuModel = .{
+        .name = "sh1",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{}),
+    };
+    pub const sh2: CpuModel = .{
+        .name = "sh2",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sh2,
+        }),
+    };
+    pub const sh2_dsp: CpuModel = .{
+        .name = "sh2_dsp",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .dsp,
+            .sh2,
+        }),
+    };
+    pub const sh2a: CpuModel = .{
+        .name = "sh2a",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .sh2a,
+        }),
+    };
+    pub const sh2a_nofpu: CpuModel = .{
+        .name = "sh2a_nofpu",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sh2a,
+        }),
+    };
+    pub const sh2e: CpuModel = .{
+        .name = "sh2e",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .sh2,
+        }),
+    };
+    pub const sh3: CpuModel = .{
+        .name = "sh3",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .mmu,
+            .sh3,
+        }),
+    };
+    pub const sh3_dsp: CpuModel = .{
+        .name = "sh3_dsp",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .dsp,
+            .mmu,
+            .sh3,
+        }),
+    };
+    pub const sh3e: CpuModel = .{
+        .name = "sh3e",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .mmu,
+            .sh3,
+        }),
+    };
+    pub const sh4: CpuModel = .{
+        .name = "sh4",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .mmu,
+            .sh4,
+        }),
+    };
+    pub const sh4_nofpu: CpuModel = .{
+        .name = "sh4_nofpu",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .mmu,
+            .sh4,
+        }),
+    };
+    pub const sh4a: CpuModel = .{
+        .name = "sh4a",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fsca,
+            .fsrra,
+            .mmu,
+            .sh4a,
+        }),
+    };
+    pub const sh4a_nofpu: CpuModel = .{
+        .name = "sh4a_nofpu",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .mmu,
+            .sh4a,
+        }),
+    };
+    pub const sh4al_dsp: CpuModel = .{
+        .name = "sh4al_dsp",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .dsp,
+            .mmu,
+            .sh4a,
+        }),
+    };
+};

lib/std/Target/sparc.zig

@@ -5,10 +5,8 @@ const CpuFeature = std.Target.Cpu.Feature;
 const CpuModel = std.Target.Cpu.Model;
 
 pub const Feature = enum {
-    @"64bit",
     crypto,
     deprecated_v8,
-    detectroundchange,
     fix_tn0009,
     fix_tn0010,
     fix_tn0011,
@@ -19,7 +17,6 @@ pub const Feature = enum {
     hasleoncasa,
     hasumacsmac,
     insertnopload,
-    leon,
     leoncyclecounter,
     leonpwrpsr,
     no_fmuls,
@@ -27,39 +24,10 @@ pub const Feature = enum {
     no_predictor,
     osa2011,
     popc,
-    reserve_g1,
-    reserve_g2,
-    reserve_g3,
-    reserve_g4,
-    reserve_g5,
-    reserve_g6,
-    reserve_g7,
-    reserve_i0,
-    reserve_i1,
-    reserve_i2,
-    reserve_i3,
-    reserve_i4,
-    reserve_i5,
-    reserve_l0,
-    reserve_l1,
-    reserve_l2,
-    reserve_l3,
-    reserve_l4,
-    reserve_l5,
-    reserve_l6,
-    reserve_l7,
-    reserve_o0,
-    reserve_o1,
-    reserve_o2,
-    reserve_o3,
-    reserve_o4,
-    reserve_o5,
     slow_rdpc,
-    soft_float,
     soft_mul_div,
     ua2005,
     ua2007,
-    v8plus,
     v9,
     vis,
     vis2,
@@ -75,13 +43,6 @@ pub const all_features = blk: {
     const len = @typeInfo(Feature).@"enum".field_names.len;
     std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
     var result: [len]CpuFeature = undefined;
-    result[@backingInt(Feature.@"64bit")] = .{
-        .llvm_name = "64bit",
-        .description = "Enable 64-bit mode",
-        .dependencies = featureSet(&[_]Feature{
-            .v9,
-        }),
-    };
     result[@backingInt(Feature.crypto)] = .{
         .llvm_name = "crypto",
         .description = "Enable cryptographic extensions",
@@ -94,11 +55,6 @@ pub const all_features = blk: {
         .description = "Enable deprecated V8 instructions in V9 mode",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.detectroundchange)] = .{
-        .llvm_name = "detectroundchange",
-        .description = "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.fix_tn0009)] = .{
         .llvm_name = "fix-tn0009",
         .description = "Enable workaround for errata described in GRLIB-TN-0009",
@@ -149,11 +105,6 @@ pub const all_features = blk: {
         .description = "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.leon)] = .{
-        .llvm_name = "leon",
-        .description = "Enable LEON extensions",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.leoncyclecounter)] = .{
         .llvm_name = "leoncyclecounter",
         .description = "Use the Leon cycle counter register",
@@ -193,141 +144,6 @@ pub const all_features = blk: {
         .description = "Use the popc (population count) instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.reserve_g1)] = .{
-        .llvm_name = "reserve-g1",
-        .description = "Reserve G1, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_g2)] = .{
-        .llvm_name = "reserve-g2",
-        .description = "Reserve G2, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_g3)] = .{
-        .llvm_name = "reserve-g3",
-        .description = "Reserve G3, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_g4)] = .{
-        .llvm_name = "reserve-g4",
-        .description = "Reserve G4, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_g5)] = .{
-        .llvm_name = "reserve-g5",
-        .description = "Reserve G5, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_g6)] = .{
-        .llvm_name = "reserve-g6",
-        .description = "Reserve G6, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_g7)] = .{
-        .llvm_name = "reserve-g7",
-        .description = "Reserve G7, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_i0)] = .{
-        .llvm_name = "reserve-i0",
-        .description = "Reserve I0, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_i1)] = .{
-        .llvm_name = "reserve-i1",
-        .description = "Reserve I1, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_i2)] = .{
-        .llvm_name = "reserve-i2",
-        .description = "Reserve I2, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_i3)] = .{
-        .llvm_name = "reserve-i3",
-        .description = "Reserve I3, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_i4)] = .{
-        .llvm_name = "reserve-i4",
-        .description = "Reserve I4, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_i5)] = .{
-        .llvm_name = "reserve-i5",
-        .description = "Reserve I5, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_l0)] = .{
-        .llvm_name = "reserve-l0",
-        .description = "Reserve L0, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_l1)] = .{
-        .llvm_name = "reserve-l1",
-        .description = "Reserve L1, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_l2)] = .{
-        .llvm_name = "reserve-l2",
-        .description = "Reserve L2, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_l3)] = .{
-        .llvm_name = "reserve-l3",
-        .description = "Reserve L3, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_l4)] = .{
-        .llvm_name = "reserve-l4",
-        .description = "Reserve L4, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_l5)] = .{
-        .llvm_name = "reserve-l5",
-        .description = "Reserve L5, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_l6)] = .{
-        .llvm_name = "reserve-l6",
-        .description = "Reserve L6, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_l7)] = .{
-        .llvm_name = "reserve-l7",
-        .description = "Reserve L7, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_o0)] = .{
-        .llvm_name = "reserve-o0",
-        .description = "Reserve O0, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_o1)] = .{
-        .llvm_name = "reserve-o1",
-        .description = "Reserve O1, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_o2)] = .{
-        .llvm_name = "reserve-o2",
-        .description = "Reserve O2, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_o3)] = .{
-        .llvm_name = "reserve-o3",
-        .description = "Reserve O3, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_o4)] = .{
-        .llvm_name = "reserve-o4",
-        .description = "Reserve O4, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_o5)] = .{
-        .llvm_name = "reserve-o5",
-        .description = "Reserve O5, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.slow_rdpc)] = .{
         .llvm_name = "slow-rdpc",
         .description = "rd %pc, %XX is slow",
@@ -335,11 +151,6 @@ pub const all_features = blk: {
             .v9,
         }),
     };
-    result[@backingInt(Feature.soft_float)] = .{
-        .llvm_name = "soft-float",
-        .description = "Use software emulation for floating point",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.soft_mul_div)] = .{
         .llvm_name = "soft-mul-div",
         .description = "Use software emulation for integer multiply and divide",
@@ -361,11 +172,6 @@ pub const all_features = blk: {
             .vis2,
         }),
     };
-    result[@backingInt(Feature.v8plus)] = .{
-        .llvm_name = "v8plus",
-        .description = "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.v9)] = .{
         .llvm_name = "v9",
         .description = "Enable SPARC-V9 instructions",
@@ -406,7 +212,6 @@ pub const cpu = struct {
         .llvm_name = "at697e",
         .features = featureSet(&[_]Feature{
             .insertnopload,
-            .leon,
         }),
     };
     pub const at697f: CpuModel = .{
@@ -414,7 +219,6 @@ pub const cpu = struct {
         .llvm_name = "at697f",
         .features = featureSet(&[_]Feature{
             .insertnopload,
-            .leon,
         }),
     };
     pub const f934: CpuModel = .{
@@ -422,17 +226,11 @@ pub const cpu = struct {
         .llvm_name = "f934",
         .features = featureSet(&[_]Feature{}),
     };
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{}),
-    };
     pub const gr712rc: CpuModel = .{
         .name = "gr712rc",
         .llvm_name = "gr712rc",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const gr740: CpuModel = .{
@@ -441,7 +239,6 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
             .hasumacsmac,
-            .leon,
             .leoncyclecounter,
             .leonpwrpsr,
         }),
@@ -454,9 +251,7 @@ pub const cpu = struct {
     pub const leon2: CpuModel = .{
         .name = "leon2",
         .llvm_name = "leon2",
-        .features = featureSet(&[_]Feature{
-            .leon,
-        }),
+        .features = featureSet(&[_]Feature{}),
     };
     pub const leon3: CpuModel = .{
         .name = "leon3",
@@ -464,7 +259,6 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
             .hasumacsmac,
-            .leon,
         }),
     };
     pub const leon4: CpuModel = .{
@@ -473,7 +267,6 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
             .hasumacsmac,
-            .leon,
         }),
     };
     pub const ma2080: CpuModel = .{
@@ -481,7 +274,6 @@ pub const cpu = struct {
         .llvm_name = "ma2080",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2085: CpuModel = .{
@@ -489,7 +281,6 @@ pub const cpu = struct {
         .llvm_name = "ma2085",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2100: CpuModel = .{
@@ -497,7 +288,6 @@ pub const cpu = struct {
         .llvm_name = "ma2100",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2150: CpuModel = .{
@@ -505,7 +295,6 @@ pub const cpu = struct {
         .llvm_name = "ma2150",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2155: CpuModel = .{
@@ -513,7 +302,6 @@ pub const cpu = struct {
         .llvm_name = "ma2155",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2450: CpuModel = .{
@@ -521,7 +309,6 @@ pub const cpu = struct {
         .llvm_name = "ma2450",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2455: CpuModel = .{
@@ -529,7 +316,6 @@ pub const cpu = struct {
         .llvm_name = "ma2455",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2480: CpuModel = .{
@@ -537,7 +323,6 @@ pub const cpu = struct {
         .llvm_name = "ma2480",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2485: CpuModel = .{
@@ -545,7 +330,6 @@ pub const cpu = struct {
         .llvm_name = "ma2485",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2x5x: CpuModel = .{
@@ -553,7 +337,6 @@ pub const cpu = struct {
         .llvm_name = "ma2x5x",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const ma2x8x: CpuModel = .{
@@ -561,7 +344,6 @@ pub const cpu = struct {
         .llvm_name = "ma2x8x",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const myriad2: CpuModel = .{
@@ -569,7 +351,6 @@ pub const cpu = struct {
         .llvm_name = "myriad2",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const myriad2_1: CpuModel = .{
@@ -577,7 +358,6 @@ pub const cpu = struct {
         .llvm_name = "myriad2.1",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const myriad2_2: CpuModel = .{
@@ -585,7 +365,6 @@ pub const cpu = struct {
         .llvm_name = "myriad2.2",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const myriad2_3: CpuModel = .{
@@ -593,7 +372,6 @@ pub const cpu = struct {
         .llvm_name = "myriad2.3",
         .features = featureSet(&[_]Feature{
             .hasleoncasa,
-            .leon,
         }),
     };
     pub const niagara: CpuModel = .{
@@ -688,7 +466,6 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .fixallfdivsqrt,
             .insertnopload,
-            .leon,
             .no_fmuls,
             .no_fsmuld,
         }),

lib/std/Target/wasm.zig

@@ -74,7 +74,9 @@ pub const all_features = blk: {
     result[@backingInt(Feature.fp16)] = .{
         .llvm_name = "fp16",
         .description = "Enable FP16 instructions",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .simd128,
+        }),
     };
     result[@backingInt(Feature.gc)] = .{
         .llvm_name = "gc",
@@ -121,7 +123,9 @@ pub const all_features = blk: {
     result[@backingInt(Feature.relaxed_atomics)] = .{
         .llvm_name = "relaxed-atomics",
         .description = "Enable relaxed-atomics proposal",
-        .dependencies = featureSet(&[_]Feature{}),
+        .dependencies = featureSet(&[_]Feature{
+            .atomics,
+        }),
     };
     result[@backingInt(Feature.relaxed_simd)] = .{
         .llvm_name = "relaxed-simd",
@@ -200,10 +204,8 @@ pub const cpu = struct {
         .name = "wasm_v3_0",
         .llvm_name = null,
         .features = featureSet(&[_]Feature{
-            .atomics,
             .exception_handling,
             .extended_const,
-            .fp16,
             .gc,
             .multimemory,
             .mutable_globals,

lib/std/Target/x86.zig

@@ -102,19 +102,14 @@ pub const Feature = enum {
     fsrm,
     fxsr,
     gfni,
-    harden_sls_ijmp,
-    harden_sls_ret,
     hreset,
     idivl_to_divb,
     idivq_to_divl,
-    inline_asm_use_gpr32,
     invpcid,
     jmpabs,
     kl,
     lea_sp,
     lea_uses_ag,
-    lvi_cfi,
-    lvi_load_hardening,
     lwp,
     lzcnt,
     macrofusion,
@@ -155,40 +150,10 @@ pub const Feature = enum {
     rdpru,
     rdrnd,
     rdseed,
-    reserve_edi,
-    reserve_r10,
-    reserve_r11,
-    reserve_r12,
-    reserve_r13,
-    reserve_r14,
-    reserve_r15,
-    reserve_r16,
-    reserve_r17,
-    reserve_r18,
-    reserve_r19,
-    reserve_r20,
-    reserve_r21,
-    reserve_r22,
-    reserve_r23,
-    reserve_r24,
-    reserve_r25,
-    reserve_r26,
-    reserve_r27,
-    reserve_r28,
-    reserve_r29,
-    reserve_r30,
-    reserve_r31,
-    reserve_r8,
-    reserve_r9,
-    retpoline,
-    retpoline_external_thunk,
-    retpoline_indirect_branches,
-    retpoline_indirect_calls,
     rtm,
     sahf,
     sbb_dep_breaking,
     serialize,
-    seses,
     sgx,
     sha,
     sha512,
@@ -208,20 +173,18 @@ pub const Feature = enum {
     sm4,
     smap,
     smep,
-    soft_float,
     sse,
     sse2,
     sse3,
     sse4_1,
     sse4_2,
     sse4a,
-    sse_unaligned_mem,
     ssse3,
-    tagged_globals,
     tbm,
     tsxldtrk,
     tuning_fast_imm_vector_shift,
     uintr,
+    unaligned_sse_access,
     use_glm_div_sqrt_costs,
     use_slm_arith_costs,
     usermsr,
@@ -231,7 +194,6 @@ pub const Feature = enum {
     waitpkg,
     wbnoinvd,
     widekl,
-    x32,
     x87,
     xop,
     xsave,
@@ -830,16 +792,6 @@ pub const all_features = blk: {
             .sse2,
         }),
     };
-    result[@backingInt(Feature.harden_sls_ijmp)] = .{
-        .llvm_name = "harden-sls-ijmp",
-        .description = "Harden against straight line speculation across indirect JMP instructions.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.harden_sls_ret)] = .{
-        .llvm_name = "harden-sls-ret",
-        .description = "Harden against straight line speculation across RET instructions.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.hreset)] = .{
         .llvm_name = "hreset",
         .description = "Has hreset instruction",
@@ -855,11 +807,6 @@ pub const all_features = blk: {
         .description = "Use 32-bit divide for positive values less than 2^32",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.inline_asm_use_gpr32)] = .{
-        .llvm_name = "inline-asm-use-gpr32",
-        .description = "Enable use of GPR32 in inline assembly for APX",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.invpcid)] = .{
         .llvm_name = "invpcid",
         .description = "Invalidate Process-Context Identifier",
@@ -887,16 +834,6 @@ pub const all_features = blk: {
         .description = "LEA instruction needs inputs at AG stage",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.lvi_cfi)] = .{
-        .llvm_name = "lvi-cfi",
-        .description = "Prevent indirect calls/branches from using a memory operand, and precede all indirect calls/branches from a register with an LFENCE instruction to serialize control flow. Also decompose RET instructions into a POP+LFENCE+JMP sequence.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.lvi_load_hardening)] = .{
-        .llvm_name = "lvi-load-hardening",
-        .description = "Insert LFENCE instructions to prevent data speculatively injected into loads from being used maliciously.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.lwp)] = .{
         .llvm_name = "lwp",
         .description = "Enable LWP instructions",
@@ -1099,156 +1036,6 @@ pub const all_features = blk: {
         .description = "Support RDSEED instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.reserve_edi)] = .{
-        .llvm_name = "reserve-edi",
-        .description = "Reserve EDI, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r10)] = .{
-        .llvm_name = "reserve-r10",
-        .description = "Reserve R10, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r11)] = .{
-        .llvm_name = "reserve-r11",
-        .description = "Reserve R11, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r12)] = .{
-        .llvm_name = "reserve-r12",
-        .description = "Reserve R12, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r13)] = .{
-        .llvm_name = "reserve-r13",
-        .description = "Reserve R13, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r14)] = .{
-        .llvm_name = "reserve-r14",
-        .description = "Reserve R14, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r15)] = .{
-        .llvm_name = "reserve-r15",
-        .description = "Reserve R15, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r16)] = .{
-        .llvm_name = "reserve-r16",
-        .description = "Reserve R16, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r17)] = .{
-        .llvm_name = "reserve-r17",
-        .description = "Reserve R17, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r18)] = .{
-        .llvm_name = "reserve-r18",
-        .description = "Reserve R18, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r19)] = .{
-        .llvm_name = "reserve-r19",
-        .description = "Reserve R19, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r20)] = .{
-        .llvm_name = "reserve-r20",
-        .description = "Reserve R20, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r21)] = .{
-        .llvm_name = "reserve-r21",
-        .description = "Reserve R21, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r22)] = .{
-        .llvm_name = "reserve-r22",
-        .description = "Reserve R22, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r23)] = .{
-        .llvm_name = "reserve-r23",
-        .description = "Reserve R23, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r24)] = .{
-        .llvm_name = "reserve-r24",
-        .description = "Reserve R24, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r25)] = .{
-        .llvm_name = "reserve-r25",
-        .description = "Reserve R25, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r26)] = .{
-        .llvm_name = "reserve-r26",
-        .description = "Reserve R26, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r27)] = .{
-        .llvm_name = "reserve-r27",
-        .description = "Reserve R27, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r28)] = .{
-        .llvm_name = "reserve-r28",
-        .description = "Reserve R28, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r29)] = .{
-        .llvm_name = "reserve-r29",
-        .description = "Reserve R29, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r30)] = .{
-        .llvm_name = "reserve-r30",
-        .description = "Reserve R30, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r31)] = .{
-        .llvm_name = "reserve-r31",
-        .description = "Reserve R31, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r8)] = .{
-        .llvm_name = "reserve-r8",
-        .description = "Reserve R8, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.reserve_r9)] = .{
-        .llvm_name = "reserve-r9",
-        .description = "Reserve R9, making it unavailable as a GPR",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.retpoline)] = .{
-        .llvm_name = "retpoline",
-        .description = "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct",
-        .dependencies = featureSet(&[_]Feature{
-            .retpoline_indirect_branches,
-            .retpoline_indirect_calls,
-        }),
-    };
-    result[@backingInt(Feature.retpoline_external_thunk)] = .{
-        .llvm_name = "retpoline-external-thunk",
-        .description = "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature",
-        .dependencies = featureSet(&[_]Feature{
-            .retpoline_indirect_calls,
-        }),
-    };
-    result[@backingInt(Feature.retpoline_indirect_branches)] = .{
-        .llvm_name = "retpoline-indirect-branches",
-        .description = "Remove speculation of indirect branches from the generated code",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
-    result[@backingInt(Feature.retpoline_indirect_calls)] = .{
-        .llvm_name = "retpoline-indirect-calls",
-        .description = "Remove speculation of indirect calls from the generated code",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.rtm)] = .{
         .llvm_name = "rtm",
         .description = "Support RTM instructions",
@@ -1269,13 +1056,6 @@ pub const all_features = blk: {
         .description = "Has serialize instruction",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.seses)] = .{
-        .llvm_name = "seses",
-        .description = "Prevent speculative execution side channel timing attacks by inserting a speculation barrier before memory reads, memory writes, and conditional branches. Implies LVI Control Flow integrity.",
-        .dependencies = featureSet(&[_]Feature{
-            .lvi_cfi,
-        }),
-    };
     result[@backingInt(Feature.sgx)] = .{
         .llvm_name = "sgx",
         .description = "Enable Software Guard Extensions",
@@ -1379,11 +1159,6 @@ pub const all_features = blk: {
         .description = "Enable Supervisor Mode Execution Prevention",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.soft_float)] = .{
-        .llvm_name = "soft-float",
-        .description = "Use software floating point features",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.sse)] = .{
         .llvm_name = "sse",
         .description = "Enable SSE instructions",
@@ -1425,11 +1200,6 @@ pub const all_features = blk: {
             .sse3,
         }),
     };
-    result[@backingInt(Feature.sse_unaligned_mem)] = .{
-        .llvm_name = "sse-unaligned-mem",
-        .description = "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.ssse3)] = .{
         .llvm_name = "ssse3",
         .description = "Enable SSSE3 instructions",
@@ -1437,11 +1207,6 @@ pub const all_features = blk: {
             .sse3,
         }),
     };
-    result[@backingInt(Feature.tagged_globals)] = .{
-        .llvm_name = "tagged-globals",
-        .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits.",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.tbm)] = .{
         .llvm_name = "tbm",
         .description = "Enable TBM instructions",
@@ -1462,6 +1227,11 @@ pub const all_features = blk: {
         .description = "Has UINTR Instructions",
         .dependencies = featureSet(&[_]Feature{}),
     };
+    result[@backingInt(Feature.unaligned_sse_access)] = .{
+        .llvm_name = "sse-unaligned-mem",
+        .description = "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
     result[@backingInt(Feature.use_glm_div_sqrt_costs)] = .{
         .llvm_name = "use-glm-div-sqrt-costs",
         .description = "Use Goldmont specific floating point div/sqrt costs",
@@ -1515,11 +1285,6 @@ pub const all_features = blk: {
             .kl,
         }),
     };
-    result[@backingInt(Feature.x32)] = .{
-        .llvm_name = "x32",
-        .description = "64-bit with ILP32 programming model (e.g. x32 ABI)",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.x87)] = .{
         .llvm_name = "x87",
         .description = "Enable X87 float instructions",
@@ -3068,21 +2833,6 @@ pub const cpu = struct {
             .xsaves,
         }),
     };
-    pub const generic: CpuModel = .{
-        .name = "generic",
-        .llvm_name = "generic",
-        .features = featureSet(&[_]Feature{
-            .@"64bit",
-            .cx8,
-            .fast_15bytenop,
-            .fast_scalar_fsqrt,
-            .idivq_to_divl,
-            .macrofusion,
-            .slow_3ops_lea,
-            .vzeroupper,
-            .x87,
-        }),
-    };
     pub const geode: CpuModel = .{
         .name = "geode",
         .llvm_name = "geode",
@@ -3890,7 +3640,6 @@ pub const cpu = struct {
         .features = featureSet(&[_]Feature{
             .cx8,
             .slow_unaligned_mem_16,
-            .soft_float,
             .vzeroupper,
         }),
     };

lib/std/Target/xcore.zig

@@ -57,7 +57,7 @@ pub const all_features = blk: {
 pub const cpu = struct {
     pub const xs1b: CpuModel = .{
         .name = "xs1b",
-        .llvm_name = null,
+        .llvm_name = "xs1b-generic",
         .features = featureSet(&[_]Feature{}),
     };
     pub const xs2a: CpuModel = .{

lib/std/Target/xtensa.zig

@@ -16,7 +16,6 @@ pub const Feature = enum {
     esp32s2ops,
     exception,
     extendedl32r,
-    forced_atomics,
     fp,
     highpriinterrupts,
     highpriinterrupts_level3,
@@ -109,11 +108,6 @@ pub const all_features = blk: {
         .description = "Enable Xtensa Extended L32R option",
         .dependencies = featureSet(&[_]Feature{}),
     };
-    result[@backingInt(Feature.forced_atomics)] = .{
-        .llvm_name = "forced-atomics",
-        .description = "Assume that lock-free native-width atomics are available",
-        .dependencies = featureSet(&[_]Feature{}),
-    };
     result[@backingInt(Feature.fp)] = .{
         .llvm_name = "fp",
         .description = "Enable Xtensa Single FP instructions",
@@ -345,8 +339,8 @@ pub const cpu = struct {
             .timers1,
         }),
     };
-    pub const generic: CpuModel = .{
-        .name = "generic",
+    pub const xtensa: CpuModel = .{
+        .name = "xtensa",
         .llvm_name = "generic",
         .features = featureSet(&[_]Feature{}),
     };

lib/std/Target/z80.zig

@@ -0,0 +1,221 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    epu,
+    ez80,
+    infc,
+    no_inirx,
+    no_ld_i_hl,
+    r800,
+    reliable_ld_a_i,
+    sli,
+    xdcb,
+    xyhl,
+    z180,
+    z280,
+    z380,
+    z80n,
+};
+
+pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).@"enum".field_names.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@backingInt(Feature.epu)] = .{
+        .llvm_name = null,
+        .description = "Enable Extended Processing Unit instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .z280,
+        }),
+    };
+    result[@backingInt(Feature.ez80)] = .{
+        .llvm_name = null,
+        .description = "Enable eZ80 instructions including ADL mode",
+        .dependencies = featureSet(&[_]Feature{
+            .xyhl,
+            .z180,
+        }),
+    };
+    result[@backingInt(Feature.infc)] = .{
+        .llvm_name = null,
+        .description = "Enable flags-only port input instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.no_inirx)] = .{
+        .llvm_name = null,
+        .description = "Disable block I/O instructions that address the port with DE and count with BC",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.no_ld_i_hl)] = .{
+        .llvm_name = null,
+        .description = "Disable 16-bit I register transfers",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.r800)] = .{
+        .llvm_name = null,
+        .description = "Enable R800 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .infc,
+            .xyhl,
+        }),
+    };
+    result[@backingInt(Feature.reliable_ld_a_i)] = .{
+        .llvm_name = null,
+        .description = "LD A,I and LD A,R reliably report the interrupt enable state",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sli)] = .{
+        .llvm_name = null,
+        .description = "Enable shift left inserting 1 instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.xdcb)] = .{
+        .llvm_name = null,
+        .description = "Enable indexed rotate, shift, RES, and SET instructions that also store to a register",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.xyhl)] = .{
+        .llvm_name = null,
+        .description = "Enable index register halves (IXH, IXL, IYH, IYL)",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.z180)] = .{
+        .llvm_name = null,
+        .description = "Enable Z180 instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.z280)] = .{
+        .llvm_name = null,
+        .description = "Enable Z280 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .infc,
+            .xyhl,
+        }),
+    };
+    result[@backingInt(Feature.z380)] = .{
+        .llvm_name = null,
+        .description = "Enable Z380 instructions including long mode",
+        .dependencies = featureSet(&[_]Feature{
+            .xyhl,
+            .z180,
+        }),
+    };
+    result[@backingInt(Feature.z80n)] = .{
+        .llvm_name = null,
+        .description = "Enable Z80N instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    const ti = @typeInfo(Feature);
+    for (&result, 0..) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.@"enum".field_names[i];
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const ez80: CpuModel = .{
+        .name = "ez80",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .ez80,
+            .reliable_ld_a_i,
+        }),
+    };
+    pub const ez80190: CpuModel = .{
+        .name = "ez80190",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .ez80,
+            .no_inirx,
+            .no_ld_i_hl,
+            .reliable_ld_a_i,
+        }),
+    };
+    pub const ez80f92: CpuModel = .{
+        .name = "ez80f92",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .ez80,
+            .no_ld_i_hl,
+            .reliable_ld_a_i,
+        }),
+    };
+    pub const r800: CpuModel = .{
+        .name = "r800",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .r800,
+        }),
+    };
+    pub const z180: CpuModel = .{
+        .name = "z180",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .z180,
+        }),
+    };
+    pub const z280: CpuModel = .{
+        .name = "z280",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .reliable_ld_a_i,
+            .z280,
+        }),
+    };
+    pub const z380: CpuModel = .{
+        .name = "z380",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .reliable_ld_a_i,
+            .z380,
+        }),
+    };
+    pub const z80: CpuModel = .{
+        .name = "z80",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{}),
+    };
+    pub const z80n: CpuModel = .{
+        .name = "z80n",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .infc,
+            .reliable_ld_a_i,
+            .sli,
+            .xdcb,
+            .xyhl,
+            .z80n,
+        }),
+    };
+    pub const z8400: CpuModel = .{
+        .name = "z8400",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .infc,
+            .sli,
+            .xdcb,
+            .xyhl,
+        }),
+    };
+    pub const z84c00: CpuModel = .{
+        .name = "z84c00",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .infc,
+            .reliable_ld_a_i,
+            .sli,
+            .xdcb,
+            .xyhl,
+        }),
+    };
+};

lib/std/atomic.zig

@@ -415,7 +415,7 @@ pub inline fn spinLoopHint() void {
 
         .sparc,
         .sparc64,
-        => if (comptime builtin.cpu.hasAny(.sparc, &.{ .v8plus, .v9 })) {
+        => if (comptime builtin.cpu.has(.sparc, .v9)) {
             asm volatile ("rd %%ccr, %%g0");
         },
 

lib/std/hash/crc.zig

@@ -786,7 +786,7 @@ pub const @"CRC-32/CKSUM" = Generic(u32, .{
     .xor_output = 0xffffffff,
 });
 
-pub const @"CRC-32/ISCSI" = if (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 }))
+pub const @"CRC-32/ISCSI" = if (builtin.target.cpu.arch == .x86_64 and builtin.target.cpu.has(.x86, .crc32))
     @import("crc/Crc32c.zig")
 else
     Generic(u32, .{

lib/std/lang.zig

@@ -393,6 +393,10 @@ pub const CallingConvention = union(enum(u8)) {
     spirv_task: SpirvKernelOptions,
     spirv_mesh: SpirvMeshOptions,
 
+    // Calling conventions for the `z80` architecture.
+    z80_cet,
+    z80_tiflags,
+
     // Calling conventions for the `ez80` architecture.
     ez80_cet,
     ez80_tiflags,

lib/std/lang/assembly.zig

@@ -2094,52 +2094,6 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) {
         v62: bool = false,
         v63: bool = false,
     },
-    .kalimba => packed struct {
-        /// Whether the inline assembly code may perform stores to memory
-        /// addresses other than those derived from input pointer provenance.
-        memory: bool = false,
-
-        i0: bool = false,
-        i1: bool = false,
-        i2: bool = false,
-        i3: bool = false,
-        i4: bool = false,
-        i5: bool = false,
-        i6: bool = false,
-        i7: bool = false,
-
-        m0: bool = false,
-        m1: bool = false,
-        m2: bool = false,
-        m3: bool = false,
-        l0: bool = false,
-        l1: bool = false,
-        l2: bool = false,
-        l3: bool = false,
-        l4: bool = false,
-        l5: bool = false,
-        doloopstart: bool = false,
-        doloopend: bool = false,
-        divresult: bool = false,
-        divremainder: bool = false,
-        rmac: bool = false,
-        rmac0: bool = false,
-        rmac1: bool = false,
-        rmac2: bool = false,
-        rlink: bool = false,
-        rflags: bool = false,
-        r0: bool = false,
-        r1: bool = false,
-        r2: bool = false,
-        r3: bool = false,
-        r4: bool = false,
-        r5: bool = false,
-        r6: bool = false,
-        r7: bool = false,
-        r8: bool = false,
-        r9: bool = false,
-        r10: bool = false,
-    },
     .or1k => packed struct {
         /// Whether the inline assembly code may perform stores to memory
         /// addresses other than those derived from input pointer provenance.

lib/std/simd.zig

@@ -35,6 +35,8 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
         } else if (cpu.arch.isLoongArch()) {
             if (cpu.has(.loongarch, .lasx)) break :blk 256;
             if (cpu.has(.loongarch, .lsx)) break :blk 128;
+        } else if (cpu.arch == .m88k) {
+            if (cpu.has(.m88k, .sfu2)) break :blk 64;
         } else if (cpu.arch.isMIPS()) {
             if (cpu.has(.mips, .msa)) break :blk 128;
             if (cpu.has(.mips, .mips3d)) break :blk 64;
@@ -65,7 +67,7 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
                 break :blk 256;
             }
         } else if (cpu.arch == .s390x) {
-            if (cpu.has(.s390x, .vector)) break :blk 128;
+            if (cpu.has(.s390x, .vx)) break :blk 128;
         } else if (cpu.arch.isSPARC()) {
             if (cpu.hasAny(.sparc, &.{ .vis, .vis2, .vis3 })) break :blk 64;
         } else if (cpu.arch == .kvx) {

lib/std/zig/llvm/Builder.zig

@@ -153,7 +153,6 @@ pub fn tripleForTarget(allocator: Allocator, target: *const std.Target) ![]const
         .ez80,
         .hppa,
         .hppa64,
-        .kalimba,
         .kvx,
         .m88k,
         .microblaze,
@@ -165,6 +164,7 @@ pub fn tripleForTarget(allocator: Allocator, target: *const std.Target) ![]const
         .spork8,
         .x86_16,
         .xtensaeb,
+        .z80,
         => unreachable, // Gated by hasLlvmSupport().
     };
 
@@ -253,13 +253,10 @@ pub fn tripleForTarget(allocator: Allocator, target: *const std.Target) ![]const
         .ps5,
         => "scei",
         .amdhsa,
-        .amdpal,
         => "amd",
         .cuda,
         .nvcl,
         => "nvidia",
-        .mesa3d,
-        => "mesa",
         else => "unknown",
     });
     try llvm_triple.append(allocator, '-');
@@ -281,8 +278,6 @@ pub fn tripleForTarget(allocator: Allocator, target: *const std.Target) ![]const
         .ps3 => "lv2",
         .ps4 => "ps4",
         .ps5 => "ps5",
-        .mesa3d => "mesa3d",
-        .amdpal => "amdpal",
         .hurd => "hurd",
         .wasi => "wasi",
         .emscripten => "emscripten",
@@ -582,7 +577,6 @@ pub const DataLayout = struct {
             .ez80,
             .hppa,
             .hppa64,
-            .kalimba,
             .kvx,
             .m88k,
             .microblaze,
@@ -591,9 +585,10 @@ pub const DataLayout = struct {
             .propeller,
             .sh,
             .sheb,
+            .spork8,
             .x86_16,
             .xtensaeb,
-            .spork8,
+            .z80,
             => unreachable,
         };
     }

lib/std/zig/system.zig

@@ -388,13 +388,6 @@ pub fn resolveTargetQuery(io: Io, query: Target.Query) DetectError!Target {
                 cpu.features.addFeature(@backingInt(Target.x86.Feature.@"32bit_mode"));
             }
         },
-        .arm, .armeb => {
-            // XXX What do we do if the target has the noarm feature?
-            //     What do we do if the user specifies +thumb_mode?
-        },
-        .thumb, .thumbeb => {
-            cpu.features.addFeature(@backingInt(Target.arm.Feature.thumb_mode));
-        },
         else => {},
     }
     updateCpuFeatures(
@@ -434,25 +427,10 @@ pub fn resolveTargetQuery(io: Io, query: Target.Query) DetectError!Target {
 
     // These CPU feature hacks have to come after ABI detection.
     {
-        if (result.cpu.arch == .hexagon) {
-            // Both LLVM and LLD have broken support for the small data area. Yet LLVM has the
-            // feature on by default for all Hexagon CPUs. Clang sort of solves this by defaulting
-            // the `-gpsize` command line parameter for the Hexagon backend to 0, so that no
-            // constants get placed in the SDA. (This of course breaks down if the user passes
-            // `-G <n>` to Clang...) We can't do the `-gpsize` hack because we can have multiple
-            // concurrent LLVM emit jobs, and command line options in LLVM are shared globally. So
-            // just force this feature off. Lovely stuff.
-            result.cpu.features.removeFeature(@backingInt(Target.hexagon.Feature.small_data));
-        }
-
         // https://github.com/llvm/llvm-project/issues/105978
         if (result.cpu.arch.isArm() and result.abi.float() == .soft) {
             result.cpu.features.removeFeature(@backingInt(Target.arm.Feature.vfp2));
         }
-
-        if (result.cpu.arch.isXtensa() and result.abi == .call0) {
-            result.cpu.features.removeFeature(@backingInt(Target.xtensa.Feature.windowed));
-        }
     }
 
     // It's possible that we detect the native ABI, but fail to detect the OS version or were told

lib/std/zig/system/freebsd.zig

@@ -79,8 +79,7 @@ const arm = struct {
 
 const powerpc = struct {
     const models = .{
-        .{ "Freescale e500v1 core", &std.Target.powerpc.cpu.e500 },
-        .{ "Freescale e500v2 core", &std.Target.powerpc.cpu.e500v2 },
+        .{ "Freescale e500v2 core", &std.Target.powerpc.cpu.e500 },
         .{ "Freescale e500mc core", &std.Target.powerpc.cpu.e500mc },
         .{ "Freescale e5500 core", &std.Target.powerpc.cpu.e5500 },
         .{ "Freescale e6500 core", &std.Target.powerpc.cpu.e6500 },

lib/std/zig/system/linux.zig

@@ -319,7 +319,6 @@ const mips = struct {
                 .{ "mips32r5", &Target.mips.cpu.mips32r5 },
                 .{ "mips32r2", &Target.mips.cpu.mips32r2 },
                 .{ "mips32r1", &Target.mips.cpu.mips32 },
-                .{ "mips5", &Target.mips.cpu.mips5 },
                 .{ "mips4", &Target.mips.cpu.mips4 },
                 .{ "mips3", &Target.mips.cpu.mips3 },
                 .{ "mips2", &Target.mips.cpu.mips2 },
@@ -448,8 +447,7 @@ const powerpc = struct {
                 .{ "e300c3", &Target.powerpc.cpu.@"603e" },
                 .{ "e300c4", &Target.powerpc.cpu.@"603e" },
                 .{ "e500mc", &Target.powerpc.cpu.e500mc },
-                .{ "e500v2", &Target.powerpc.cpu.e500v2 },
-                .{ "e500", &Target.powerpc.cpu.e500 },
+                .{ "e500v2", &Target.powerpc.cpu.e500 },
                 .{ "e5500", &Target.powerpc.cpu.e5500 },
                 .{ "e6500", &Target.powerpc.cpu.e6500 },
                 .{ "G2_LE", &Target.powerpc.cpu.@"603e" },
@@ -722,13 +720,13 @@ const riscv = struct {
                     setFeature(&cpu, .zicbop, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZICBOP));
                     setFeature(&cpu, .zilsd, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZILSD));
                     setFeature(&cpu, .zclsd, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZCLSD));
-                    setFeature(&cpu, .experimental_zicfilp, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZICFILP));
+                    // setFeature(&cpu, .experimental_zicfilp, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZICFILP));
                 },
                 RISCV_HWPROBE.KEY.MISALIGNED_SCALAR_PERF => {
-                    setFeature(&cpu, .unaligned_scalar_mem, value == RISCV_HWPROBE.MISALIGNED_SCALAR.FAST);
+                    setFeature(&cpu, .unaligned_access, value == RISCV_HWPROBE.MISALIGNED_SCALAR.FAST);
                 },
                 RISCV_HWPROBE.KEY.MISALIGNED_VECTOR_PERF => {
-                    setFeature(&cpu, .unaligned_vector_mem, value == RISCV_HWPROBE.MISALIGNED_VECTOR.FAST);
+                    setFeature(&cpu, .unaligned_vector_access, value == RISCV_HWPROBE.MISALIGNED_VECTOR.FAST);
                 },
                 RISCV_HWPROBE.KEY.VENDOR_EXT_MIPS_0 => {
                     setFeature(&cpu, .xmipsexectl, ima_support and set(value, RISCV_HWPROBE.MIPS_VENDOR_EXT_XMIPSEXECTL));
@@ -740,7 +738,7 @@ const riscv = struct {
                     setFeature(&cpu, .xsfvfwmaccqqq, ima_support and set(value, RISCV_HWPROBE.SIFIVE_VENDOR_EXT.XSFVFWMACCQQQ));
                 },
                 RISCV_HWPROBE.KEY.IMA_EXT_1 => {
-                    setFeature(&cpu, .experimental_zicfiss, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_1_EXT_ZICFISS));
+                    // setFeature(&cpu, .experimental_zicfiss, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_1_EXT_ZICFISS));
                 },
                 else => unreachable,
             }

lib/std/zig/system/loongarch.zig

@@ -1,6 +1,23 @@
 const builtin = @import("builtin");
 const std = @import("std");
 
+const Prid = packed struct(u32) {
+    product: u12,
+    series: enum(u4) {
+        la132 = 0x8,
+        la264 = 0xa,
+        la364 = 0xb,
+        la464 = 0xc,
+        la664 = 0xd,
+        _,
+    },
+    company: enum(u8) {
+        loongson = 0x14,
+        _,
+    },
+    reserved: u8,
+};
+
 const Variant = enum(u2) {
     la32r = 0b00,
     la32 = 0b01,
@@ -19,25 +36,44 @@ fn setFeature(cpu: *std.Target.Cpu, feature: std.Target.loongarch.Feature, enabl
 }
 
 pub fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
-    const variant: Variant = @fromBackingInt(@intCast(cpucfg(1) & 0b11));
+    const prid: Prid = @bitCast(cpucfg(0));
 
     var cpu: std.Target.Cpu = .{
         .arch = arch,
-        .model = switch (cpucfg(0) & 0b1111000000000000) {
-            else => switch (variant) {
-                .la32r, .la32 => &std.Target.loongarch.cpu.generic_la32,
-                .la64 => &std.Target.loongarch.cpu.generic_la64,
-                .reserved => unreachable,
+        .model = switch (arch) {
+            .loongarch32 => m: {
+                switch (prid.company) {
+                    .loongson => switch (prid.series) {
+                        .la132 => break :m &std.Target.loongarch.cpu.la132,
+                        else => {},
+                    },
+                    else => {},
+                }
+
+                break :m &std.Target.loongarch.cpu.generic_la32;
             },
-            0xc000 => &std.Target.loongarch.cpu.la464,
-            0xd000 => &std.Target.loongarch.cpu.la664,
+            .loongarch64 => m: {
+                switch (prid.company) {
+                    .loongson => switch (prid.series) {
+                        .la464 => break :m &std.Target.loongarch.cpu.la464,
+                        .la664 => break :m &std.Target.loongarch.cpu.la664,
+                        else => {},
+                    },
+                    else => {},
+                }
+
+                break :m &std.Target.loongarch.cpu.generic_la64;
+            },
+            else => unreachable,
         },
         .features = .empty,
     };
 
     cpu.features.addFeatureSet(cpu.model.features);
 
-    setFeature(&cpu, .@"32s", variant != .la32r);
+    const variant: Variant = @fromBackingInt(@intCast(cpucfg(1) & 0b11));
+
+    setFeature(&cpu, .@"32s", variant == .la32 or variant == .la64);
 
     const cfg2 = cpucfg(2);
     const cfg3 = cpucfg(3);
@@ -49,7 +85,7 @@ pub fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
         else
             std.os.linux.getauxval(std.elf.AT.HWCAP);
 
-        setFeature(&cpu, .ual, (hwcap_bits & HWCAP.UAL) != 0);
+        setFeature(&cpu, .unaligned_access, (hwcap_bits & HWCAP.UAL) != 0);
 
         const has_fpu = (hwcap_bits & HWCAP.FPU) != 0;
         setFeature(&cpu, .f, has_fpu and bit(cfg2, 1));
@@ -62,7 +98,7 @@ pub fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu {
 
         setFeature(&cpu, .lam_bh, (hwcap_bits & HWCAP.LAM_BH) != 0);
     } else {
-        setFeature(&cpu, .ual, false);
+        setFeature(&cpu, .unaligned_access, false);
 
         setFeature(&cpu, .f, false);
         setFeature(&cpu, .d, false);

lib/std/zig/target.zig

@@ -520,12 +520,12 @@ pub fn intAlignment(target: *const std.Target, bits: u16) u16 {
 }
 
 pub fn compilerRtFloatAbi(target: *const std.Target, bits: u16) std.Target.Abi.Float {
-    if (target.cpu.has(.x86, .soft_float)) return .soft;
+    if (target.cpu.arch.isX86() and target.abi.float() == .soft) return .soft;
     // Marks targets where clang does not even provide a usable C type.
     const no_c_type_available = .soft;
     switch (bits) {
         else => unreachable,
-        16 => if (target.cpu.arch.isMIPS() or target.cpu.arch.isPowerPC()) return no_c_type_available,
+        16 => if (target.cpu.arch.isMips() or target.cpu.arch.isPowerpc()) return no_c_type_available,
         32, 64 => {},
         80 => if (target.cTypeBitSize(.longdouble) != 80) return no_c_type_available,
         128 => {
@@ -659,9 +659,7 @@ pub fn isNative(query: *const std.Target.Query, target: *const std.Target, host:
             .alu_lsl_fast,
             .avoid_ldapur,
             .disable_fast_inc_vl,
-            .exynos_cheap_as_move,
             .fast_ld1_single,
-            .fixed_load_latency_4,
             .fuse_address,
             .fuse_addsub_2reg_const1,
             .fuse_adrp_add,
@@ -677,10 +675,6 @@ pub fn isNative(query: *const std.Target.Query, target: *const std.Target, host:
             .slow_misaligned_128store,
             .slow_paired_128,
             .slow_strqro_store,
-            .use_experimental_zeroing_pseudos,
-            .use_fixed_over_scalable_if_equal_cost,
-            .use_postra_scheduler,
-            .use_reciprocal_square_root,
             .use_wzr_to_vec_move,
         }),
         else => .empty,

lib/zig.h

@@ -99,6 +99,8 @@
 #define zig_x86
 #elif defined(__xtensa__)
 #define zig_xtensa
+#elif defined (__z80)
+#define zig_z80
 #elif defined (__ez80)
 #define zig_ez80
 #define zig_z80

src/Compilation.zig

@@ -92,8 +92,6 @@ windows_libs_num_done: u32,
 version: ?std.SemanticVersion,
 libc_installation: ?*const LibCInstallation,
 skip_linker_dependencies: bool,
-function_sections: bool,
-data_sections: bool,
 link_eh_frame_hdr: bool,
 native_system_include_paths: []const []const u8,
 /// List of symbols forced as undefined in the symbol table
@@ -1486,8 +1484,6 @@ pub const CreateOptions = struct {
     /// executable this field is ignored.
     want_compiler_rt: ?bool = null,
     want_ubsan_rt: ?bool = null,
-    function_sections: bool = false,
-    data_sections: bool = false,
     time_report: bool = false,
     stack_report: bool = false,
     link_eh_frame_hdr: bool = false,
@@ -1945,8 +1941,8 @@ pub fn create(gpa: Allocator, arena: Allocator, io: Io, diag: *CreateDiagnostic,
         cache.hash.add(options.config.any_sanitize_thread);
         cache.hash.add(options.config.any_sanitize_c);
         cache.hash.add(options.config.any_fuzz);
-        cache.hash.add(options.function_sections);
-        cache.hash.add(options.data_sections);
+        cache.hash.add(options.config.function_sections);
+        cache.hash.add(options.config.data_sections);
         cache.hash.add(link_libc);
         cache.hash.add(options.config.link_libcpp);
         cache.hash.add(options.config.link_libunwind);
@@ -2164,8 +2160,6 @@ pub fn create(gpa: Allocator, arena: Allocator, io: Io, diag: *CreateDiagnostic,
             .llvm_opt_bisect_limit = options.llvm_opt_bisect_limit,
             .skip_linker_dependencies = options.skip_linker_dependencies,
             .queued_jobs = .{},
-            .function_sections = options.function_sections,
-            .data_sections = options.data_sections,
             .native_system_include_paths = options.native_system_include_paths,
             .force_undefined_symbols = options.force_undefined_symbols,
             .link_eh_frame_hdr = link_eh_frame_hdr,
@@ -6673,15 +6667,36 @@ pub fn addCCArgs(
         });
     }
 
+    if (target.cpu.arch == .hexagon) {
+        try argv.append("-G0"); // Unsupported by LLD.
+    }
+
     // We might want to support -mfloat-abi=softfp for Arm and CSKY here in the future.
     if (target_util.clangSupportsFloatAbiArg(target)) {
-        const fabi = @tagName(target.abi.float());
+        const fabi = target.abi.float();
 
         try argv.append(switch (target.cpu.arch) {
             // For whatever reason, Clang doesn't support `-mfloat-abi` for s390x.
-            .s390x => try std.fmt.allocPrint(arena, "-m{s}-float", .{fabi}),
-            else => try std.fmt.allocPrint(arena, "-mfloat-abi={s}", .{fabi}),
+            .s390x => try std.fmt.allocPrint(arena, "-m{s}-float", .{@tagName(fabi)}),
+            else => try std.fmt.allocPrint(arena, "-mfloat-abi={s}", .{@tagName(fabi)}),
         });
+
+        if (target.cpu.arch.isMips() and fabi == .hard) {
+            try argv.appendSlice(if (target.cpu.has(.mips, .single_float))
+                &.{ "-msingle-float", "-mno-odd-spreg" }
+            else if (target.cpu.arch.isMips64() or target.cpu.hasAny(.mips, &.{ .mips32r6, .msa }))
+                &.{ "-mfp64", "-modd-spreg" }
+            else if (target.cpu.has(.mips, .mips2))
+                &.{ "-mfpxx", "-mno-odd-spreg" }
+            else
+                &.{ "-mfp32", "-mno-odd-spreg" });
+        }
+    }
+
+    if (target.cpu.arch.isX86() and target.abi.float() == .soft) {
+        // This is necessary to get the effects of the `soft-float` backend
+        // subtarget feature in the frontend as well.
+        try argv.append("-mgeneral-regs-only");
     }
 
     if (mod.patchable_function_entry > 0) {
@@ -6689,12 +6704,25 @@ pub fn addCCArgs(
         try argv.append(try std.fmt.allocPrint(arena, "-fpatchable-function-entry={}", .{pf}));
     }
 
+    if (target.cpu.arch.isMips()) {
+        try argv.append(if (mod.pic) "-mabicalls" else "-mno-abicalls");
+    }
+
     try comp.addCommonCCArgs(arena, argv, ext, out_dep_path, mod, comp.config.c_frontend);
 
     // Non-preprocessed assembly files don't support these flags.
     if (ext != .assembly) {
-        if (target_util.clangSupportsNoImplicitFloatArg(target) and target.abi.float() == .soft) {
-            try argv.append("-mno-implicit-float");
+        if (target.abi.float() == .soft) {
+            if (target_util.clangSupportsNoImplicitFloatArg(target)) {
+                try argv.append("-mno-implicit-float");
+            }
+
+            // Ensure that Clang emits the `use-soft-float` function attribute.
+            try argv.appendSlice(&.{ "-Xclang", "-msoft-float" });
+        }
+
+        if (target.cpu.arch.isMips() and !mod.pic) {
+            try argv.append("-mno-gpopt");
         }
 
         if (target_util.hasRedZone(target)) {
@@ -6719,8 +6747,8 @@ pub fn addCCArgs(
 
         try argv.append(if (mod.no_builtin) "-fno-builtin" else "-fbuiltin");
 
-        try argv.append(if (comp.function_sections) "-ffunction-sections" else "-fno-function-sections");
-        try argv.append(if (comp.data_sections) "-fdata-sections" else "-fno-data-sections");
+        try argv.append(if (comp.config.function_sections) "-ffunction-sections" else "-fno-function-sections");
+        try argv.append(if (comp.config.data_sections) "-fdata-sections" else "-fno-data-sections");
 
         switch (mod.unwind_tables) {
             .none => {
@@ -6776,17 +6804,9 @@ pub fn addCCArgs(
 
                 if (feature.llvm_name) |llvm_name| {
                     // We communicate these to Clang through the dedicated options.
-                    if (std.mem.startsWith(u8, llvm_name, "soft-float") or
-                        std.mem.startsWith(u8, llvm_name, "hard-float") or
-                        (target.cpu.arch.isPowerPC() and std.mem.startsWith(u8, llvm_name, "64bit")) or
-                        (target.cpu.arch.isX86() and std.mem.startsWith(u8, llvm_name, "x32")) or
-                        (target.cpu.arch == .s390x and std.mem.eql(u8, llvm_name, "backchain")))
+                    if (std.mem.startsWith(u8, llvm_name, "soft-float") or std.mem.startsWith(u8, llvm_name, "hard-float"))
                         continue;
 
-                    // Ignore these until we figure out how to handle the concept of omitting features.
-                    // See https://github.com/ziglang/zig/issues/23539
-                    if (target_util.isDynamicAMDGCNFeature(target, feature)) continue;
-
                     const plus_or_minus = "-+"[@intFromBool(is_enabled)];
                     const arg = try std.fmt.allocPrint(arena, "{c}{s}", .{ plus_or_minus, llvm_name });
                     for (xclang_flags) |xclang| {
@@ -6794,6 +6814,28 @@ pub fn addCCArgs(
                     }
                 }
             }
+
+            if (target.cpu.arch.isPowerpc32()) {
+                // https://github.com/llvm/llvm-project/issues/235393
+                for (xclang_flags) |xclang| try argv.appendSlice(&.{
+                    xclang,
+                    "-target-feature",
+                    xclang,
+                    "-crbits",
+                });
+            }
+
+            if (target.cpu.arch.isXtensa()) {
+                // LLVM does not currently support specifying windowed vs call0 ABI any other way than
+                // disabling all windowed instructions altogether. That's kind of silly because a
+                // windowed core can do call0 just fine.
+                if (target.abi == .call0) for (xclang_flags) |xclang| try argv.appendSlice(&.{
+                    xclang,
+                    "-target-feature",
+                    xclang,
+                    "-windowed",
+                });
+            }
         },
         else => {},
     }
@@ -7346,6 +7388,8 @@ fn buildOutputFromZig(
         .any_error_tracing = false,
         .root_error_tracing = false,
         .lto = if (options.allow_lto) comp.config.lto else .none,
+        .function_sections = true,
+        .data_sections = true,
     }) catch |err| {
         comp.lockAndSetMiscFailure(misc_task_tag, "sub-compilation of {t} failed: failed to resolve compilation config: {t}", .{ misc_task_tag, err });
         return error.AlreadyReported;
@@ -7407,8 +7451,6 @@ fn buildOutputFromZig(
         .root_name = root_name,
         .libc_installation = comp.libc_installation,
         .emit_bin = .yes_cache,
-        .function_sections = true,
-        .data_sections = true,
         .verbose_cc = comp.verbose_cc,
         .verbose_link = comp.verbose_link,
         .clang_passthrough_mode = comp.clang_passthrough_mode,
@@ -7486,6 +7528,8 @@ pub fn build_crt_file(
             .Lib => if (options.allow_lto) comp.config.lto else .none,
             .Obj, .Exe => .none,
         },
+        .function_sections = options.function_sections,
+        .data_sections = options.data_sections,
     }) catch |err| {
         comp.lockAndSetMiscFailure(misc_task_tag, "sub-compilation of {t} failed: failed to resolve compilation config: {t}", .{ misc_task_tag, err });
         return error.AlreadyReported;
@@ -7537,8 +7581,6 @@ pub fn build_crt_file(
         .root_name = root_name,
         .libc_installation = comp.libc_installation,
         .emit_bin = .yes_cache,
-        .function_sections = options.function_sections,
-        .data_sections = options.data_sections,
         .c_source_files = c_source_files,
         .verbose_cc = comp.verbose_cc,
         .verbose_link = comp.verbose_link,

src/Compilation/Config.zig

@@ -65,6 +65,8 @@ root_error_tracing: bool,
 dll_export_fns: bool,
 rdynamic: bool,
 san_cov_trace_pc_guard: bool,
+function_sections: bool,
+data_sections: bool,
 
 pub const CFrontend = enum { clang, aro };
 
@@ -119,6 +121,8 @@ pub const Options = struct {
     dll_export_fns: ?bool = null,
     rdynamic: ?bool = null,
     san_cov_trace_pc_guard: bool = false,
+    function_sections: ?bool = null,
+    data_sections: ?bool = null,
 };
 
 pub const ResolveError = error{
@@ -556,6 +560,55 @@ pub fn resolve(options: Options) ResolveError!Config {
         };
     };
 
+    const function_sections = b: {
+        if (options.function_sections) |x| break :b x;
+
+        // Xtensa *really* wants per-function literal pools or branches will start to break once the
+        // program grows past 256 KiB. This can only be accomplished with function sections.
+        if (target.cpu.arch.isXtensa()) break :b true;
+
+        break :b switch (backend) {
+            // LLVM uses short branches on these targets and is not capable of intelligently using
+            // long branches when the output object grows big enough. So on these targets, it makes
+            // for a better user experience to enable function sections by default.
+            //
+            // Rule of thumb: If a target needs thunks to reach +/- 2 GiB, it belongs on this list.
+            .stage2_llvm => switch (target.cpu.arch) {
+                // +/- 128 MiB
+                .aarch64,
+                .aarch64_be,
+                // +/- 32 MiB
+                .arm,
+                .armeb,
+                // +/- 8 MiB
+                .hexagon,
+                // +/- 32 KiB
+                .m68k,
+                // 256 MiB region
+                .mips,
+                .mipsel,
+                .mips64,
+                .mips64el,
+                // +/- 32 MiB
+                .powerpc,
+                .powerpcle,
+                .powerpc64,
+                .powerpc64le,
+                // +/- 4 MiB (Thumb-1), 16 MiB (Thumb-2)
+                .thumb,
+                .thumbeb,
+                => true,
+                else => false,
+            },
+            else => false,
+        };
+    };
+
+    const data_sections = b: {
+        if (options.data_sections) |x| break :b x;
+        break :b false;
+    };
+
     return .{
         .output_mode = options.output_mode,
         .have_zcu = options.have_zcu,
@@ -590,6 +643,8 @@ pub fn resolve(options: Options) ResolveError!Config {
         .root_strip = root_strip,
         .dll_export_fns = dll_export_fns,
         .rdynamic = rdynamic,
+        .function_sections = function_sections,
+        .data_sections = data_sections,
     };
 }
 

src/Module.zig

@@ -184,9 +184,8 @@ pub fn create(arena: Allocator, options: CreateOptions) !*Module {
                 return error.PieRequiresPic;
             break :b true;
         }
-        if (options.global.output_mode == .Lib and
-            options.global.link_mode == .dynamic and
-            target_util.requiresPicForDynamicLink(target))
+        if (options.global.link_mode == .dynamic and
+            target_util.requiresPicForDynamicLink(target, options.global.output_mode))
         {
             if (options.inherited.pic == false)
                 return error.DynamicLinkingRequiresPic;
@@ -371,19 +370,7 @@ pub fn create(arena: Allocator, options: CreateOptions) !*Module {
         var disabled_features = std.array_list.Managed(u8).init(arena);
         for (target.cpu.arch.allFeaturesList()) |feature| {
             if (feature.llvm_name) |llvm_name| {
-                // Ignore these until we figure out how to handle the concept of omitting features.
-                // See https://github.com/ziglang/zig/issues/23539
-                if (target_util.isDynamicAMDGCNFeature(target, feature)) continue;
-
-                if (target.cpu.arch.isPowerPC() and @as(std.Target.powerpc.Feature, @fromBackingInt(@intCast(feature.index))) == .@"64bit") continue;
-                if (target.cpu.arch.isX86() and @as(std.Target.x86.Feature, @fromBackingInt(@intCast(feature.index))) == .x32) continue;
-
-                var is_enabled = target.cpu.features.isEnabled(feature.index);
-                if (target.cpu.arch == .s390x and @as(std.Target.s390x.Feature, @fromBackingInt(@intCast(feature.index))) == .backchain) {
-                    is_enabled = !omit_frame_pointer;
-                }
-
-                if (is_enabled) {
+                if (target.cpu.features.isEnabled(feature.index)) {
                     try buf.ensureUnusedCapacity(2 + llvm_name.len);
                     buf.appendAssumeCapacity('+');
                     buf.appendSliceAssumeCapacity(llvm_name);
@@ -396,8 +383,47 @@ pub fn create(arena: Allocator, options: CreateOptions) !*Module {
                 }
             }
         }
-
         try buf.appendSlice(disabled_features.items);
+
+        if (target.cpu.arch.isArm()) {
+            try buf.append(if (target.cpu.arch.isThumb()) '+' else '-');
+            try buf.appendSlice("thumb-mode,");
+        }
+
+        if (target.cpu.arch == .hexagon) {
+            try buf.appendSlice("-small-data,"); // Unsupported by LLD.
+        }
+
+        if (target.cpu.arch.isMips()) {
+            try buf.append(if (pic) '-' else '+');
+            try buf.appendSlice("noabicalls,");
+            try buf.appendSlice(if (target.cpu.has(.mips, .single_float))
+                "-fpxx,+nooddspreg,"
+            else if (target.cpu.arch.isMips64() or target.cpu.hasAny(.mips, &.{ .mips32r6, .msa }))
+                "-fpxx,-nooddspreg,+fp64,"
+            else if (target.cpu.has(.mips, .mips2))
+                "+fpxx,+nooddspreg,"
+            else
+                "-fpxx,+nooddspreg,");
+        }
+
+        if (target.cpu.arch.isPowerpc32()) {
+            // https://github.com/llvm/llvm-project/issues/235393
+            try buf.appendSlice("-crbits,");
+        }
+
+        if (target.cpu.arch == .s390x) {
+            try buf.append(if (omit_frame_pointer) '-' else '+');
+            try buf.appendSlice("backchain,");
+        }
+
+        if (target.cpu.arch.isXtensa()) {
+            // LLVM does not currently support specifying windowed vs call0 ABI any other way than
+            // disabling all windowed instructions altogether. That's kind of silly because a
+            // windowed core can do call0 just fine.
+            if (target.abi == .call0) try buf.appendSlice("-windowed,");
+        }
+
         if (buf.items.len == 0) break :b "";
         assert(buf.items[buf.items.len - 1] == ',');
         buf.items[buf.items.len - 1] = 0;

src/Sema.zig

@@ -8522,7 +8522,7 @@ pub fn handleExternLibName(
                 .{lib_name},
             );
         }
-        if (!block.ownerModule().pic and target_util.requiresPicForDynamicLink(target)) {
+        if (!block.ownerModule().pic and target_util.requiresPicForDynamicLink(target, comp.config.output_mode)) {
             return sema.fail(
                 block,
                 src_loc,

src/Zcu.zig

@@ -4223,6 +4223,7 @@ pub fn atomicPtrAlignment(
     const max_atomic_bits: u16 = switch (target.cpu.arch) {
         .ez80,
         .spork8,
+        .z80,
         => 8,
 
         .aarch64,
@@ -4807,6 +4808,7 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.lang.CallingConvention) union(enum)
                 .avr_interrupt,
                 .avr_signal,
                 .ez80_tiflags,
+                .z80_tiflags,
                 .loongarch32_preserve_none,
                 .loongarch64_preserve_none,
                 .riscv32_preserve_most,

src/codegen/c/type.zig

@@ -223,7 +223,9 @@ pub const CType = union(enum) {
                 .x86_64_interrupt,
                 => .interrupt,
 
-                .ez80_tiflags => .tiflags,
+                .z80_tiflags,
+                .ez80_tiflags,
+                => .tiflags,
 
                 else => unreachable, // `Zcu.callconvSupported`
             };

src/codegen/llvm.zig

@@ -623,8 +623,8 @@ pub const Object = struct {
             opt_level,
             reloc_mode,
             code_model,
-            comp.function_sections,
-            comp.data_sections,
+            comp.config.function_sections,
+            comp.config.data_sections,
             switch (target.abi.float()) {
                 .hard => .Hard,
                 .soft => .Soft,
@@ -4500,6 +4500,8 @@ pub fn toLlvmCallConvTag(cc_tag: std.lang.CallingConvention.Tag, target: *const
         .avr_gnu,
         .bpf_std,
         .csky_sysv,
+        .z80_cet,
+        .z80_tiflags,
         .ez80_cet,
         .ez80_tiflags,
         .hexagon_sysv,
@@ -4802,7 +4804,6 @@ pub fn initializeLLVMTarget(io: Io, arch: std.Target.Cpu.Arch) void {
         .ez80,
         .hppa,
         .hppa64,
-        .kalimba,
         .kvx,
         .m88k,
         .microblaze,
@@ -4814,6 +4815,7 @@ pub fn initializeLLVMTarget(io: Io, arch: std.Target.Cpu.Arch) void {
         .spork8,
         .x86_16,
         .xtensaeb,
+        .z80,
         => unreachable,
     }
 }

src/codegen/llvm/FuncGen.zig

@@ -5299,25 +5299,7 @@ fn airLoad(fg: *FuncGen, inst: Air.Inst.Index) Allocator.Error!Builder.Value {
 
 fn airTrap(self: *FuncGen, inst: Air.Inst.Index) Allocator.Error!void {
     _ = inst;
-    const target = self.object.zcu.getTarget();
-    if ((target.cpu.arch == .mips or target.cpu.arch == .mipsel) and
-        target.cpu.has(.mips, .notraps))
-    {
-        // Emit a MIPS `break` instruction followed by an infinite loop (to fulfil the noreturn)
-        // since this CPU does not support trap instructions.
-        const o = self.object;
-        _ = try self.wip.callAsm(
-            .none,
-            try o.builder.fnType(.void, &.{}, .normal),
-            .{ .sideeffect = true },
-            try o.builder.string("break\n0:\nj 0b\nnop"),
-            try o.builder.string("~{memory}"),
-            &.{},
-            "",
-        );
-    } else {
-        _ = try self.wip.callIntrinsic(.normal, .none, .trap, &.{}, &.{}, "");
-    }
+    _ = try self.wip.callIntrinsic(.normal, .none, .trap, &.{}, &.{}, "");
     _ = try self.wip.@"unreachable"();
 }
 

src/codegen/loongarch/Select.zig

@@ -3998,7 +3998,7 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) codegen.Error!void
                     defer dst_vi.value.deref(isel);
 
                     // TODO unaligned loads
-                    assert(isel.target.cpu.has(.loongarch, .ual));
+                    assert(isel.target.cpu.has(.loongarch, .unaligned_access));
                     const ptr_vi = try isel.use(ty_op.operand);
                     const ptr_mat = try ptr_vi.matIntRegZeroExt(isel);
                     _ = try dst_vi.value.defLoad(isel, ptr_mat.reg(), 0, .{

src/codegen/loongarch/abi.zig

@@ -49,12 +49,11 @@ const Classifier = struct {
                 .loongarch32 => 32,
                 .loongarch64 => 64,
             },
-            .frlen = if (target.cpu.has(.loongarch, .d))
-                64
-            else if (target.cpu.has(.loongarch, .f))
-                32
-            else
-                0,
+            .frlen = switch (target.abi) {
+                .gnusf, .muslsf => 0,
+                .gnuf32, .muslf32 => 32,
+                else => 64,
+            },
         };
     }
 

src/codegen/x86_64/abi.zig

@@ -123,14 +123,14 @@ pub fn classifyWindows(init_ty: Type, zcu: *Zcu, target: *const std.Target, ctx:
             else => switch (ty.zigTypeTag(zcu)) {
                 .int => .win_i128,
                 .@"struct", .@"union" => if (ty.containerLayout(zcu) != .@"packed" or
-                    target.cpu.has(.x86, .soft_float)) .memory else .win_i128,
+                    target.abi.float() == .soft) .memory else .win_i128,
                 else => .memory,
             },
         },
         .noreturn => unreachable,
         .float => switch (ty.floatBits(target)) {
             else => unreachable,
-            16, 32, 64 => if (target.cpu.has(.x86, .soft_float)) .integer else .sse,
+            16, 32, 64 => if (target.abi.float() == .soft) .integer else .sse,
             80, 128 => .memory,
         },
         .vector => {
@@ -193,7 +193,7 @@ pub fn classifySystemV(ty: Type, zcu: *Zcu, target: *const std.Target, ctx: Cont
             if (bits <= 64 * 4) return Class.four_integers;
             return Class.stack;
         },
-        .float => if (target.cpu.has(.x86, .soft_float)) switch (ty.floatBits(target)) {
+        .float => if (target.abi.float() == .soft) switch (ty.floatBits(target)) {
             else => unreachable,
             16, 32, 64 => return Class.one_integer,
             80, 128 => return Class.two_integers,

src/libs/freebsd.zig

@@ -84,10 +84,6 @@ pub fn buildCrtFile(comp: *Compilation, crt_file: CrtFile, prog_node: std.Progre
                 "-w", // Disable all warnings.
             });
 
-            if (target.cpu.arch.isPowerPC64()) {
-                try cflags.append("-mlongcall");
-            }
-
             var acflags = std.array_list.Managed([]const u8).init(arena);
             try acflags.appendSlice(&.{
                 "-DLOCORE",

src/libs/libcxx.zig

@@ -147,6 +147,8 @@ pub fn buildLibCxx(comp: *Compilation, prog_node: std.Progress.Node) BuildError!
         .link_libc = true,
         .lto = comp.config.lto,
         .any_sanitize_thread = comp.config.any_sanitize_thread,
+        .function_sections = true,
+        .data_sections = true,
     }) catch |err| {
         comp.lockAndSetMiscFailure(
             .libcxx,
@@ -255,8 +257,6 @@ pub fn buildLibCxx(comp: *Compilation, prog_node: std.Progress.Node) BuildError!
         .root_name = root_name,
         .libc_installation = comp.libc_installation,
         .emit_bin = .yes_cache,
-        .function_sections = true,
-        .data_sections = true,
         .c_source_files = c_source_files.items,
         .verbose_cc = comp.verbose_cc,
         .verbose_link = comp.verbose_link,
@@ -328,6 +328,8 @@ pub fn buildLibCxxAbi(comp: *Compilation, prog_node: std.Progress.Node) BuildErr
         .any_unwind_tables = unwind_tables != .none,
         .lto = comp.config.lto,
         .any_sanitize_thread = comp.config.any_sanitize_thread,
+        .function_sections = true,
+        .data_sections = true,
     }) catch |err| {
         comp.lockAndSetMiscFailure(
             .libcxxabi,
@@ -436,8 +438,6 @@ pub fn buildLibCxxAbi(comp: *Compilation, prog_node: std.Progress.Node) BuildErr
         .root_name = root_name,
         .libc_installation = comp.libc_installation,
         .emit_bin = .yes_cache,
-        .function_sections = true,
-        .data_sections = true,
         .c_source_files = c_source_files.items,
         .verbose_cc = comp.verbose_cc,
         .verbose_link = comp.verbose_link,

src/libs/libtsan.zig

@@ -69,6 +69,8 @@ pub fn buildTsan(comp: *Compilation, prog_node: std.Progress.Node) BuildError!vo
         .any_unwind_tables = unwind_tables != .none,
         // LLVM disables LTO for its libtsan.
         .lto = .none,
+        .function_sections = true,
+        .data_sections = true,
     }) catch |err| {
         comp.lockAndSetMiscFailure(
             .libtsan,
@@ -290,8 +292,6 @@ pub fn buildTsan(comp: *Compilation, prog_node: std.Progress.Node) BuildError!vo
         .root_name = root_name,
         .libc_installation = comp.libc_installation,
         .emit_bin = .yes_cache,
-        .function_sections = true,
-        .data_sections = true,
         .c_source_files = c_source_files.items,
         .verbose_cc = comp.verbose_cc,
         .verbose_link = comp.verbose_link,

src/libs/libunwind.zig

@@ -42,6 +42,8 @@ pub fn buildStaticLib(comp: *Compilation, prog_node: std.Progress.Node) BuildErr
         .link_libc = true,
         .any_unwind_tables = unwind_tables != .none,
         .lto = comp.config.lto,
+        .function_sections = true,
+        .data_sections = true,
     }) catch |err| {
         comp.lockAndSetMiscFailure(
             .libunwind,
@@ -152,8 +154,6 @@ pub fn buildStaticLib(comp: *Compilation, prog_node: std.Progress.Node) BuildErr
         .main_mod = null,
         .libc_installation = comp.libc_installation,
         .emit_bin = .yes_cache,
-        .function_sections = true,
-        .data_sections = true,
         .c_source_files = &c_source_files,
         .verbose_cc = comp.verbose_cc,
         .verbose_link = comp.verbose_link,

src/link/Elf.zig

@@ -1538,8 +1538,6 @@ pub fn writeElfHeader(self: *Elf) !void {
     hdr_buf[index] = @backingInt(@as(elf.OSABI, switch (target.cpu.arch) {
         .amdgcn => switch (target.os.tag) {
             .amdhsa => .AMDGPU_HSA,
-            .amdpal => .AMDGPU_PAL,
-            .mesa3d => .AMDGPU_MESA3D,
             else => .NONE,
         },
         .msp430 => .STANDALONE,

src/link/Elf2.zig

@@ -5076,8 +5076,6 @@ fn create(
         .openbsd => .OPENBSD,
         .cuda => .CUDA,
         .amdhsa => .AMDGPU_HSA,
-        .amdpal => .AMDGPU_PAL,
-        .mesa3d => .AMDGPU_MESA3D,
     };
     const @"type": EhdrType = switch (comp.config.output_mode) {
         .Exe => if (comp.config.pie or target.os.tag == .haiku) .DYN else .EXEC,
@@ -5704,11 +5702,10 @@ fn initHeaders(
             ehdr.shoff = 0;
             ehdr.flags = switch (machine) {
                 .LOONGARCH => .{ .loongarch = .{
-                    .base_abi_modifier = mod: {
-                        const cpu = comp.getTarget().cpu;
-                        if (cpu.has(.loongarch, .d)) break :mod .d;
-                        if (cpu.has(.loongarch, .f)) break :mod .f;
-                        break :mod .s;
+                    .base_abi_modifier = switch (comp.getTarget().abi) {
+                        .gnusf, .muslsf => .s,
+                        .gnuf32, .muslf32 => .f,
+                        else => .d,
                     },
                     .abi_extension = .base,
                     .abi_version = 1,

src/main.zig

@@ -921,8 +921,6 @@ fn buildOutputType(
     var version: std.SemanticVersion = .{ .major = 0, .minor = 0, .patch = 0 };
     var have_version = false;
     var compatibility_version: ?std.SemanticVersion = null;
-    var function_sections = false;
-    var data_sections = false;
     var listen: Listen = .none;
     var debug_compile_errors = false;
     var debug_incremental = false;
@@ -1684,13 +1682,13 @@ fn buildOutputType(
                     } else if (mem.eql(u8, arg, "-fno-single-threaded")) {
                         mod_opts.single_threaded = false;
                     } else if (mem.eql(u8, arg, "-ffunction-sections")) {
-                        function_sections = true;
+                        create_module.opts.function_sections = true;
                     } else if (mem.eql(u8, arg, "-fno-function-sections")) {
-                        function_sections = false;
+                        create_module.opts.function_sections = false;
                     } else if (mem.eql(u8, arg, "-fdata-sections")) {
-                        data_sections = true;
+                        create_module.opts.data_sections = true;
                     } else if (mem.eql(u8, arg, "-fno-data-sections")) {
-                        data_sections = false;
+                        create_module.opts.data_sections = false;
                     } else if (mem.eql(u8, arg, "-fbuiltin")) {
                         mod_opts.no_builtin = false;
                     } else if (mem.eql(u8, arg, "-fno-builtin")) {
@@ -2137,10 +2135,10 @@ fn buildOutputType(
                     .no_red_zone => mod_opts.red_zone = false,
                     .omit_frame_pointer => mod_opts.omit_frame_pointer = true,
                     .no_omit_frame_pointer => mod_opts.omit_frame_pointer = false,
-                    .function_sections => function_sections = true,
-                    .no_function_sections => function_sections = false,
-                    .data_sections => data_sections = true,
-                    .no_data_sections => data_sections = false,
+                    .function_sections => create_module.opts.function_sections = true,
+                    .no_function_sections => create_module.opts.function_sections = false,
+                    .data_sections => create_module.opts.data_sections = true,
+                    .no_data_sections => create_module.opts.data_sections = false,
                     .builtin => mod_opts.no_builtin = false,
                     .no_builtin => mod_opts.no_builtin = true,
                     .color_diagnostics => color = .on,
@@ -3722,8 +3720,6 @@ fn buildOutputType(
         .force_undefined_symbols = force_undefined_symbols,
         .stack_size = stack_size,
         .image_base = image_base,
-        .function_sections = function_sections,
-        .data_sections = data_sections,
         .clang_passthrough_mode = clang_passthrough_mode,
         .clang_preprocessor_mode = clang_preprocessor_mode,
         .version = optional_version,

src/target.zig

@@ -76,12 +76,16 @@ pub fn requiresPic(target: *const std.Target) bool {
     return (target.os.tag == .windows or target.os.tag == .uefi) and (target.cpu.arch == .aarch64 or target.cpu.arch == .x86_64);
 }
 
-pub fn requiresPicForDynamicLink(target: *const std.Target) bool {
+pub fn requiresPicForDynamicLink(target: *const std.Target, output_mode: std.lang.OutputMode) bool {
     assert(canDynamicLink(target));
 
-    return switch (target.os.tag) {
-        .windows => target.cpu.arch == .aarch64 or target.cpu.arch == .x86_64,
-        else => !target.cpu.arch.isWasm(),
+    return switch (output_mode) {
+        .Lib => switch (target.os.tag) {
+            .windows => target.cpu.arch == .aarch64 or target.cpu.arch == .x86_64,
+            else => !target.cpu.arch.isWasm(),
+        },
+        .Exe => target.cpu.arch.isMips(),
+        .Obj => false,
     };
 }
 
@@ -254,6 +258,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
 
         // Third-party LLVM backend exists.
         .ez80,
+        .z80,
         => false,
 
         // No LLVM backend exists.
@@ -261,7 +266,6 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat)
         .arceb,
         .hppa,
         .hppa64,
-        .kalimba,
         .kvx,
         .m88k,
         .microblaze,
@@ -534,6 +538,8 @@ pub fn clangSupportsTargetCpuArg(target: *const std.Target) bool {
     return switch (target.cpu.arch) {
         .arc,
         .msp430,
+        .spirv32,
+        .spirv64,
         .ve,
         .xcore,
         .xtensa,
@@ -651,8 +657,7 @@ pub fn addrSpaceIsLogical(target: *const std.Target, as: AddressSpace) bool {
             .push_constant,
             => true,
             .shared => !features.isEnabled(@backingInt(std.Target.spirv.Feature.variable_pointers)),
-            .storage_buffer => !features.isEnabled(@backingInt(std.Target.spirv.Feature.variable_pointers)) and
-                !features.isEnabled(@backingInt(std.Target.spirv.Feature.variable_pointers_storage_buffer)),
+            .storage_buffer => !features.isEnabled(@backingInt(std.Target.spirv.Feature.variable_pointers_storage_buffer)),
             .physical_storage_buffer => false,
             else => unreachable,
         },
@@ -660,56 +665,14 @@ pub fn addrSpaceIsLogical(target: *const std.Target, as: AddressSpace) bool {
     };
 }
 
-pub fn isDynamicAMDGCNFeature(target: *const std.Target, feature: std.Target.Cpu.Feature) bool {
-    if (target.cpu.arch != .amdgcn) return false;
-
-    const sramecc_only = &[_]*const std.Target.Cpu.Model{
-        &std.Target.amdgcn.cpu.gfx1010,
-        &std.Target.amdgcn.cpu.gfx1011,
-        &std.Target.amdgcn.cpu.gfx1012,
-        &std.Target.amdgcn.cpu.gfx1013,
-    };
-    const xnack_or_sramecc = &[_]*const std.Target.Cpu.Model{
-        &std.Target.amdgcn.cpu.gfx1030,
-        &std.Target.amdgcn.cpu.gfx1031,
-        &std.Target.amdgcn.cpu.gfx1032,
-        &std.Target.amdgcn.cpu.gfx1033,
-        &std.Target.amdgcn.cpu.gfx1034,
-        &std.Target.amdgcn.cpu.gfx1035,
-        &std.Target.amdgcn.cpu.gfx1036,
-        &std.Target.amdgcn.cpu.gfx1100,
-        &std.Target.amdgcn.cpu.gfx1101,
-        &std.Target.amdgcn.cpu.gfx1102,
-        &std.Target.amdgcn.cpu.gfx1103,
-        &std.Target.amdgcn.cpu.gfx1150,
-        &std.Target.amdgcn.cpu.gfx1151,
-        &std.Target.amdgcn.cpu.gfx1152,
-        &std.Target.amdgcn.cpu.gfx1153,
-        &std.Target.amdgcn.cpu.gfx1200,
-        &std.Target.amdgcn.cpu.gfx1201,
-    };
-    const feature_tag: std.Target.amdgcn.Feature = @fromBackingInt(@intCast(feature.index));
-
-    if (feature_tag == .sramecc) {
-        if (std.mem.findScalar(
-            *const std.Target.Cpu.Model,
-            sramecc_only ++ xnack_or_sramecc,
-            target.cpu.model,
-        )) |_| return true;
-    }
-    if (feature_tag == .xnack) {
-        if (std.mem.findScalar(
-            *const std.Target.Cpu.Model,
-            xnack_or_sramecc,
-            target.cpu.model,
-        )) |_| return true;
-    }
-
-    return false;
-}
-
 pub fn llvmMachineAbi(target: *const std.Target) ?[:0]const u8 {
     return switch (target.cpu.arch) {
+        .aarch64, .aarch64_be => if (target.abi.float() == .soft)
+            "aapcs-soft"
+        else if (target.os.tag.isDarwin())
+            "darwinpcs"
+        else
+            "aapcs",
         .arm, .armeb, .thumb, .thumbeb => "aapcs",
         .loongarch64 => switch (target.abi) {
             .gnusf, .muslsf => "lp64s",

stage1/zig.h

@@ -99,6 +99,8 @@
 #define zig_x86
 #elif defined(__xtensa__)
 #define zig_xtensa
+#elif defined (__z80)
+#define zig_z80
 #elif defined (__ez80)
 #define zig_ez80
 #define zig_z80
@@ -261,6 +263,12 @@
 #define zig_no_builtin
 #endif
 
+#if zig_has_attribute(patchable_function_entry)
+#define zig_patchable_function_entry(count) __attribute__((patchable_function_entry(count)))
+#else
+#define zig_patchable_function_entry(count) zig_patchable_function_entry_unavailable
+#endif
+
 #if zig_has_attribute(aligned) || defined(zig_tinyc)
 #define zig_under_align(alignment) __attribute__((aligned(alignment)))
 #elif defined(zig_msvc)
@@ -6725,19 +6733,7 @@ static inline void* zig_e_zig_windows_peb(void) {
 
 #endif
 
-#if defined(zig_loongarch)
-
-static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) zig_mangled(zig_e_zig_loongarch_cpucfg, "zig_loongarch_cpucfg");
-
-static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) {
-#if defined(zig_gnuc_asm)
-    __asm__("cpucfg %[result], %[word]" : [result] "=r" (*result) : [word] "r" (word));
-#else
-    *result = 0;
-#endif
-}
-
-#elif defined(zig_x86) && !defined(zig_x86_16)
+#if defined(zig_x86) && !defined(zig_x86_16)
 
 static inline void zig_e_zig_x86_cpuid(uint32_t leaf_id, uint32_t subid, uint32_t* eax, uint32_t* ebx, uint32_t* ecx, uint32_t* edx) zig_mangled(zig_e_zig_x86_cpuid, "zig_x86_cpuid");
 static inline uint32_t zig_e_zig_x86_get_xcr0(void) zig_mangled(zig_e_zig_x86_get_xcr0, "zig_x86_get_xcr0");

test/cases/compile_errors/callconv_spirv_on_unsupported_platform.zig

@@ -22,7 +22,7 @@ export fn entry4() void {
 // error
 // backend=selfhosted
 // target=spirv64-opencl
-// cpu_features=opencl_v2+mesh_shading_ext
+// cpu_features=opencl_v2_1+mesh_shading_ext
 //
 // :1:28: error: calling convention 'spirv_fragment' not supported by compiler backend 'stage2_spirv'
 // :2:28: error: calling convention 'spirv_vertex' not supported by compiler backend 'stage2_spirv'

test/llvm/allowzero

@@ -1,6 +1,4 @@
 #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
 
 #skip bpfeb-freestanding-none-baseline-whole-llvm-lld-pic
 

test/llvm/array_to_vector

@@ -1,6 +1,4 @@
 #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
 
 #skip csky-freestanding-eabi-baseline-whole-llvm-lld-pic
 #skip csky-freestanding-eabihf-baseline-whole-llvm-lld-pic

test/llvm/dead_store

@@ -1,6 +1,4 @@
 #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
 
 #skip csky-freestanding-eabi-baseline-whole-llvm-lld-pic
 #skip csky-freestanding-eabihf-baseline-whole-llvm-lld-pic

test/llvm/empty_analyze

@@ -1,6 +1,3 @@
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
-
 #skip arm-uefi-eabi-baseline-whole-llvm-lld-pic
 #skip arm-uefi-eabihf-baseline-whole-llvm-lld-pic
 

test/llvm/empty_assembly

@@ -1,6 +1,3 @@
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
-
 #skip arm-uefi-eabi-baseline-whole-llvm-lld-pic
 #skip arm-uefi-eabihf-baseline-whole-llvm-lld-pic
 

test/llvm/empty_object

@@ -1,6 +1,3 @@
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
-
 #skip arc-freestanding-none-baseline-whole-llvm-lld-pic
 #skip arc-linux-gnu-baseline-whole-llvm-lld-pic
 #skip arc-linux-none-baseline-whole-llvm-lld-pic

test/llvm/load_store_bool

@@ -1,6 +1,4 @@
 #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
 
 #skip bpfeb-freestanding-none-baseline-whole-llvm-lld-pic
 

test/llvm/matrix.zon

@@ -38,8 +38,6 @@
     .{ .cpu = .{ .aarch64_be = .{} }, .os = .{ .netbsd = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
 
     .{ .cpu = .{ .amdgcn = .{} }, .os = .{ .amdhsa = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
-    .{ .cpu = .{ .amdgcn = .{} }, .os = .{ .amdpal = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
-    .{ .cpu = .{ .amdgcn = .{} }, .os = .{ .mesa3d = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
 
     .{ .cpu = .{ .arc = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .arc = .{} }, .os = .{ .linux = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
@@ -65,6 +63,7 @@
     .{ .cpu = .{ .arm = .{} }, .os = .{ .openbsd = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .arm = .{} }, .os = .{ .rtems = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .arm = .{} }, .os = .{ .rtems = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
+    .{ .cpu = .{ .arm = .{} }, .os = .{ .@"switch" = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .arm = .{} }, .os = .{ .uefi = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .arm = .{} }, .os = .{ .uefi = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .arm = .{} }, .os = .{ .vita = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
@@ -238,18 +237,21 @@
 
     .{ .cpu = .{ .riscv64be = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
 
-    .{ .cpu = .{ .s390x = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
+    .{ .cpu = .{ .s390x = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
+    .{ .cpu = .{ .s390x = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .s390x = .{} }, .os = .{ .linux = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .s390x = .{} }, .os = .{ .linux = .{} }, .abi = .{ .musl = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .s390x = .{} }, .os = .{ .linux = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
 
-    .{ .cpu = .{ .sparc = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
+    .{ .cpu = .{ .sparc = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
+    .{ .cpu = .{ .sparc = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .sparc = .{} }, .os = .{ .linux = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .sparc = .{} }, .os = .{ .linux = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .sparc = .{} }, .os = .{ .netbsd = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .sparc = .{} }, .os = .{ .rtems = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
 
-    .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
+    .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
+    .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
     .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .linux = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
     .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .linux = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
     .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .netbsd = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
@@ -299,7 +301,8 @@
     .{ .cpu = .{ .wasm64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .wasm64 = .{} }, .os = .{ .wasi = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
 
-    .{ .cpu = .{ .x86 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
+    .{ .cpu = .{ .x86 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
+    .{ .cpu = .{ .x86 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .x86 = .{} }, .os = .{ .haiku = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .x86 = .{} }, .os = .{ .hurd = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
     .{ .cpu = .{ .x86 = .{} }, .os = .{ .illumos = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
@@ -316,8 +319,8 @@
     .{ .cpu = .{ .x86 = .{} }, .os = .{ .windows = .{} }, .abi = .{ .msvc = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic },
 
     .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .freebsd = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
-    .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
-    .{ .cpu = .{ .x86_64 = .{ .features = .{ .add = .{.soft_float}, .remove = .{ .mmx, .sse, .sse2, .avx, .avx2 } } } }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
+    .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
+    .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
     .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .fuchsia = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
     .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .dragonfly = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic },
     .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .driverkit = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .old, .pic = .pic },

test/llvm/nonnull

@@ -1,6 +1,4 @@
 #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
 
 #skip csky-freestanding-eabi-baseline-whole-llvm-lld-pic
 #skip csky-freestanding-eabihf-baseline-whole-llvm-lld-pic

test/llvm/unused_load

@@ -1,6 +1,4 @@
 #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic
-#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic
 
 #skip csky-freestanding-eabi-baseline-whole-llvm-lld-pic
 #skip csky-freestanding-eabihf-baseline-whole-llvm-lld-pic

test/tests.zig

@@ -420,25 +420,27 @@ const module_test_targets = blk: {
             .link_libc = true,
         },
 
-        // Similar to Thumb, we need long calls on Hexagon due to relocation range issues.
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "hexagon-linux-none",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
+            .target = .{
+                .cpu_arch = .hexagon,
+                .os_tag = .linux,
+                .abi = .none,
+            },
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "hexagon-linux-musl",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
+            .target = .{
+                .cpu_arch = .hexagon,
+                .os_tag = .linux,
+                .abi = .musl,
+            },
             .link_libc = true,
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "hexagon-linux-musl",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
+            .target = .{
+                .cpu_arch = .hexagon,
+                .os_tag = .linux,
+                .abi = .musl,
+            },
             .linkage = .dynamic,
             .link_libc = true,
             .extra_target = true,
@@ -1074,69 +1076,66 @@ const module_test_targets = blk: {
             .link_libc = true,
         },
 
-        // Calls are normally lowered to branch instructions that only support +/- 16 MB range when
-        // targeting Thumb. This easily becomes insufficient for our test binaries, so use long
-        // calls to avoid out-of-range relocations.
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumb-linux-eabi",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
-            .pic = false, // Long calls don't work with PIC.
+            .target = .{
+                .cpu_arch = .thumb,
+                .os_tag = .linux,
+                .abi = .eabi,
+            },
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumb-linux-eabihf",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
-            .pic = false, // Long calls don't work with PIC.
+            .target = .{
+                .cpu_arch = .thumb,
+                .os_tag = .linux,
+                .abi = .eabihf,
+            },
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumb-linux-musleabi",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
+            .target = .{
+                .cpu_arch = .thumb,
+                .os_tag = .linux,
+                .abi = .musleabi,
+            },
             .link_libc = true,
-            .pic = false, // Long calls don't work with PIC.
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumb-linux-musleabihf",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
+            .target = .{
+                .cpu_arch = .thumb,
+                .os_tag = .linux,
+                .abi = .musleabihf,
+            },
             .link_libc = true,
-            .pic = false, // Long calls don't work with PIC.
         },
 
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumbeb-linux-eabi",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
-            .pic = false, // Long calls don't work with PIC.
+            .target = .{
+                .cpu_arch = .thumbeb,
+                .os_tag = .linux,
+                .abi = .eabi,
+            },
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumbeb-linux-eabihf",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
-            .pic = false, // Long calls don't work with PIC.
+            .target = .{
+                .cpu_arch = .thumbeb,
+                .os_tag = .linux,
+                .abi = .eabihf,
+            },
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumbeb-linux-musleabi",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
+            .target = .{
+                .cpu_arch = .thumbeb,
+                .os_tag = .linux,
+                .abi = .musleabi,
+            },
             .link_libc = true,
-            .pic = false, // Long calls don't work with PIC.
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumbeb-linux-musleabihf",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
+            .target = .{
+                .cpu_arch = .thumbeb,
+                .os_tag = .linux,
+                .abi = .musleabihf,
+            },
             .link_libc = true,
-            .pic = false, // Long calls don't work with PIC.
         },
 
         .{
@@ -1980,33 +1979,33 @@ const c_abi_targets = blk: {
         },
 
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumb-linux-musleabi",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
-            .pic = false, // Long calls don't work with PIC.
+            .target = .{
+                .cpu_arch = .thumb,
+                .os_tag = .linux,
+                .abi = .musleabi,
+            },
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumb-linux-musleabihf",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
-            .pic = false, // Long calls don't work with PIC.
+            .target = .{
+                .cpu_arch = .thumb,
+                .os_tag = .linux,
+                .abi = .musleabihf,
+            },
         },
 
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumbeb-linux-musleabi",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
-            .pic = false, // Long calls don't work with PIC.
+            .target = .{
+                .cpu_arch = .thumbeb,
+                .os_tag = .linux,
+                .abi = .musleabi,
+            },
         },
         .{
-            .target = std.Target.Query.parse(.{
-                .arch_os_abi = "thumbeb-linux-musleabihf",
-                .cpu_features = "baseline+long_calls",
-            }) catch unreachable,
-            .pic = false, // Long calls don't work with PIC.
+            .target = .{
+                .cpu_arch = .thumbeb,
+                .os_tag = .linux,
+                .abi = .musleabihf,
+            },
         },
 
         .{
@@ -2693,8 +2692,8 @@ fn addOneModuleTest(
     if (options.build_options) |build_options| {
         these_tests.root_module.addOptions("build_options", build_options);
     }
-    if (test_target.function_sections) |fs| these_tests.link_function_sections = fs;
-    if (test_target.data_sections) |ds| these_tests.link_data_sections = ds;
+    if (test_target.function_sections) |fs| these_tests.function_sections = fs;
+    if (test_target.data_sections) |ds| these_tests.data_sections = ds;
     const single_threaded_suffix = if (test_target.single_threaded == true) "-single" else "";
     const backend_suffix = if (test_target.use_llvm == true)
         "-llvm"

tools/gen_spirv_spec.zig

@@ -268,13 +268,10 @@ fn render(
     );
 
     try writer.print(
-        \\pub const version: Version = .{{ .major = {}, .minor = {}, .patch = {} }};
         \\pub const magic_number: Word = {s};
         \\
         \\
-    ,
-        .{ registry.major_version, registry.minor_version, registry.revision, registry.magic_number },
-    );
+    , .{registry.magic_number});
 
     var all_operand_kinds: OperandKindMap = .empty;
     for (registry.operand_kinds) |kind| {
@@ -311,7 +308,6 @@ fn renderExtension(
 ) !void {
     try writer.writeAll(
         \\pub const Extension = enum {
-        \\v1_0,
         \\v1_1,
         \\v1_2,
         \\v1_3,
@@ -808,17 +804,50 @@ fn renderValueEnum(
     if (std.mem.eql(u8, "Capability", enumeration.kind)) {
         try writer.writeAll(
             \\
-            \\pub fn dependencies(self: Capability) []const Extension {
+            \\pub fn dependencyExtensions(self: Capability) []const Extension {
             \\ return switch (self) {
         );
         for (enum_indices) |i| {
             const enumerant = enumerants[i];
             const enum_version = enumerant.version.?;
             const minor = if (enum_version[0] == 'N') '0' else enum_version[2];
-            try writer.print("\n.{f} => &.{{.v1_{c}", .{ formatId(enumerant.enumerant), minor });
+            try writer.print("\n.{f} => &.{{", .{formatId(enumerant.enumerant)});
+            var comma = if (minor != '0') b: {
+                try writer.print(".v1_{c}", .{minor});
+                break :b true;
+            } else false;
             for (enumerant.extensions) |extension| {
                 if (!isAllowedExtension(extension)) continue;
-                try writer.print(", .{s}", .{extension});
+                if (comma) try writer.writeAll(", ");
+                try writer.print(".{s}", .{extension});
+                comma = true;
+            }
+            try writer.writeAll("},");
+        }
+        try writer.writeAll(
+            \\};
+            \\}
+            \\
+            \\pub fn dependencyCapabilities(self: Capability) []const Capability {
+            \\ return switch (self) {
+        );
+        var by_name: std.StringHashMapUnmanaged(u31) = .empty;
+        for (enumerants) |enumerant| {
+            const value: u31 = switch (enumerant.value) {
+                .int => |value| value,
+                .bitflag => |value| try std.fmt.parseInt(u31, value, 10),
+            };
+            try by_name.putNoClobber(arena, enumerant.enumerant, value);
+            for (enumerant.aliases) |alias| try by_name.putNoClobber(arena, alias, value);
+        }
+        for (enum_indices) |i| {
+            const enumerant = enumerants[i];
+            try writer.print("\n.{f} => &.{{", .{formatId(enumerant.enumerant)});
+            var comma = false;
+            for (enumerant.capabilities) |name| {
+                if (comma) try writer.writeAll(", ");
+                try writer.print(".{f}", .{formatId(enumerants[enum_map.get(by_name.get(name).?).?].enumerant)});
+                comma = true;
             }
             try writer.writeAll("},");
         }
@@ -1057,6 +1086,7 @@ fn renderFieldName(writer: *std.Io.Writer, operands: []const Operand, field_inde
 }
 
 fn isAllowedCapability(name: []const u8) bool {
+    if (std.mem.find(u8, name, "Provisional") != null) return false;
     const last = name[name.len - 1];
     if (std.ascii.isLower(last) or std.ascii.isDigit(last)) return true;
     for (allowed_vendors) |vendor| {
@@ -1091,6 +1121,7 @@ fn isEnabled(version: ?[]const u8, capabilities: []const []const u8, extensions:
 fn keepEnabled(instructions: *[]Instruction, kinds: []OperandKind) void {
     var kept: usize = 0;
     for (instructions.*) |inst| {
+        if (inst.provisional) continue;
         if (!isEnabled(inst.version, inst.capabilities, inst.extensions)) continue;
         instructions.*[kept] = inst;
         kept += 1;
@@ -1100,8 +1131,9 @@ fn keepEnabled(instructions: *[]Instruction, kinds: []OperandKind) void {
         const enumerants = kind.enumerants orelse continue;
         var kept_enumerants: usize = 0;
         for (enumerants) |enumerant| {
+            if (enumerant.provisional) continue;
             const enabled = if (std.mem.eql(u8, kind.kind, "Capability"))
-                isAllowedCapability(enumerant.enumerant)
+                isEnabled(enumerant.version, &.{}, enumerant.extensions) and std.mem.find(u8, enumerant.enumerant, "Provisional") == null
             else
                 isEnabled(enumerant.version, enumerant.capabilities, enumerant.extensions);
             if (!enabled) continue;