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update_cpu_features: populate sh data
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@@ -768,7 +768,7 @@ pub const powerpc = @import("Target/powerpc.zig");
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pub const propeller = @import("Target/propeller.zig");
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pub const riscv = @import("Target/riscv.zig");
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pub const s390x = @import("Target/s390x.zig");
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pub const sh = @import("Target/generic.zig");
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pub const sh = @import("Target/sh.zig");
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pub const sparc = @import("Target/sparc.zig");
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pub const spirv = @import("Target/spirv.zig");
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pub const spork8 = @import("Target/generic.zig");
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@@ -2075,6 +2075,7 @@ pub const Cpu = struct {
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.riscv32, .riscv32be => &riscv.cpu.rv32i,
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.riscv64, .riscv64be => &riscv.cpu.rv64i,
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.s390x => &s390x.cpu.arch8,
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.sh, .sheb => &sh.cpu.sh1,
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.sparc => &sparc.cpu.v7,
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.sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
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.spirv32, .spirv64 => &spirv.cpu.v1_0,
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@@ -2158,6 +2159,10 @@ pub const Cpu = struct {
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.riscv32, .riscv32be => &riscv.cpu.rv32gc,
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.riscv64, .riscv64be => &riscv.cpu.rv64gc,
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.s390x => &s390x.cpu.arch11,
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.sh, .sheb => switch (os.tag) {
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.netbsd => &sh.cpu.sh3,
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else => &sh.cpu.sh4,
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},
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.sparc => switch (os.tag) {
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.linux => &sparc.cpu.v9, // glibc does not work with 'plain' v8.
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else => &sparc.cpu.v8,
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@@ -0,0 +1,236 @@
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//! This file is auto-generated by tools/update_cpu_features.zig.
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const std = @import("../std.zig");
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const CpuFeature = std.Target.Cpu.Feature;
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const CpuModel = std.Target.Cpu.Model;
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pub const Feature = enum {
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cas,
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dsp,
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dynshift,
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fpu,
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fsca,
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fsrra,
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mmu,
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sh2,
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sh2a,
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sh3,
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sh4,
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sh4a,
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};
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pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
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pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
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pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
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pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
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pub const all_features = blk: {
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const len = @typeInfo(Feature).@"enum".field_names.len;
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std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
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var result: [len]CpuFeature = undefined;
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result[@backingInt(Feature.cas)] = .{
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.llvm_name = null,
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.description = "Enable cas.l instruction",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@backingInt(Feature.dsp)] = .{
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.llvm_name = null,
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.description = "Enable DSP extension",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@backingInt(Feature.dynshift)] = .{
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.llvm_name = null,
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.description = "Enable dynamic shift instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@backingInt(Feature.fpu)] = .{
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.llvm_name = null,
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.description = "Enable floating point unit",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@backingInt(Feature.fsca)] = .{
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.llvm_name = null,
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.description = "Enable fsca instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@backingInt(Feature.fsrra)] = .{
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.llvm_name = null,
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.description = "Enable fsrra instruction",
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.dependencies = featureSet(&[_]Feature{
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.fpu,
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}),
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};
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result[@backingInt(Feature.mmu)] = .{
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.llvm_name = null,
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.description = "Enable memory management unit",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@backingInt(Feature.sh2)] = .{
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.llvm_name = null,
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.description = "Enable SH-2 instructions",
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.dependencies = featureSet(&[_]Feature{}),
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};
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result[@backingInt(Feature.sh2a)] = .{
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.llvm_name = null,
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.description = "Enable SH-2A instructions",
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.dependencies = featureSet(&[_]Feature{
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.dynshift,
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.sh2,
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}),
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};
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result[@backingInt(Feature.sh3)] = .{
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.llvm_name = null,
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.description = "Enable SH-3 instructions",
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.dependencies = featureSet(&[_]Feature{
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.dynshift,
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.sh2,
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}),
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};
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result[@backingInt(Feature.sh4)] = .{
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.llvm_name = null,
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.description = "Enable SH-4 instructions",
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.dependencies = featureSet(&[_]Feature{
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.sh3,
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}),
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};
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result[@backingInt(Feature.sh4a)] = .{
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.llvm_name = null,
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.description = "Enable SH-4A instructions",
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.dependencies = featureSet(&[_]Feature{
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.sh4,
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}),
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};
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const ti = @typeInfo(Feature);
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for (&result, 0..) |*elem, i| {
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elem.index = i;
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elem.name = ti.@"enum".field_names[i];
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}
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break :blk result;
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};
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pub const cpu = struct {
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pub const j2: CpuModel = .{
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.name = "j2",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.cas,
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.dynshift,
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.sh2,
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}),
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};
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pub const sh1: CpuModel = .{
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.name = "sh1",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{}),
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};
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pub const sh2: CpuModel = .{
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.name = "sh2",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.sh2,
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}),
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};
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pub const sh2_dsp: CpuModel = .{
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.name = "sh2_dsp",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.dsp,
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.sh2,
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}),
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};
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pub const sh2a: CpuModel = .{
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.name = "sh2a",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.fpu,
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.sh2a,
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}),
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};
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pub const sh2a_nofpu: CpuModel = .{
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.name = "sh2a_nofpu",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.sh2a,
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}),
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};
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pub const sh2e: CpuModel = .{
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.name = "sh2e",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.fpu,
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.sh2,
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}),
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};
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pub const sh3: CpuModel = .{
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.name = "sh3",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.mmu,
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.sh3,
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}),
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};
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pub const sh3_dsp: CpuModel = .{
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.name = "sh3_dsp",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.dsp,
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.mmu,
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.sh3,
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}),
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};
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pub const sh3e: CpuModel = .{
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.name = "sh3e",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.fpu,
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.mmu,
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.sh3,
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}),
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};
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pub const sh4: CpuModel = .{
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.name = "sh4",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.fpu,
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.mmu,
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.sh4,
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}),
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};
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pub const sh4_nofpu: CpuModel = .{
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.name = "sh4_nofpu",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.mmu,
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.sh4,
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}),
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};
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pub const sh4a: CpuModel = .{
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.name = "sh4a",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.fsca,
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.fsrra,
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.mmu,
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.sh4a,
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}),
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};
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pub const sh4a_nofpu: CpuModel = .{
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.name = "sh4a_nofpu",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.mmu,
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.sh4a,
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}),
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};
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pub const sh4al_dsp: CpuModel = .{
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.name = "sh4al_dsp",
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.llvm_name = null,
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.features = featureSet(&[_]Feature{
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.dsp,
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.mmu,
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.sh4a,
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}),
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};
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};
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@@ -4060,6 +4060,197 @@ const targets = [_]ArchTarget{
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},
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},
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},
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.{
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.zig_name = "sh",
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.llvm = null,
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.extra_features = &.{
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.{
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.zig_name = "cas",
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.desc = "Enable cas.l instruction",
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.deps = &.{},
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},
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.{
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.zig_name = "dsp",
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.desc = "Enable DSP extension",
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.deps = &.{},
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},
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.{
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.zig_name = "dynshift",
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.desc = "Enable dynamic shift instructions",
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.deps = &.{},
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},
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.{
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.zig_name = "fpu",
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.desc = "Enable floating point unit",
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.deps = &.{},
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},
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.{
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.zig_name = "fsca",
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.desc = "Enable fsca instruction",
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.deps = &.{"fpu"},
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},
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.{
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.zig_name = "fsrra",
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.desc = "Enable fsrra instruction",
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.deps = &.{"fpu"},
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},
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.{
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.zig_name = "mmu",
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.desc = "Enable memory management unit",
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.deps = &.{},
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},
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.{
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.zig_name = "sh2",
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.desc = "Enable SH-2 instructions",
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.deps = &.{},
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},
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.{
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.zig_name = "sh2a",
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.desc = "Enable SH-2A instructions",
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.deps = &.{ "dynshift", "sh2" },
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},
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.{
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.zig_name = "sh3",
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.desc = "Enable SH-3 instructions",
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.deps = &.{ "dynshift", "sh2" },
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},
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.{
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.zig_name = "sh4",
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.desc = "Enable SH-4 instructions",
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.deps = &.{"sh3"},
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},
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.{
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.zig_name = "sh4a",
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.desc = "Enable SH-4A instructions",
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.deps = &.{"sh4"},
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},
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},
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.extra_models = &.{
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.{
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.llvm_name = null,
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.zig_name = "j2",
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.features = &.{
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"cas",
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"dynshift",
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"sh2",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh1",
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.features = &.{},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh2",
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.features = &.{
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"sh2",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh2_dsp",
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.features = &.{
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"dsp",
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"sh2",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh2a",
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.features = &.{
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"fpu",
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"sh2a",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh2a_nofpu",
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.features = &.{
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"sh2a",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh2e",
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.features = &.{
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"fpu",
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"sh2",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh3",
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.features = &.{
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"mmu",
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"sh3",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh3_dsp",
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.features = &.{
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"dsp",
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"mmu",
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"sh3",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh3e",
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.features = &.{
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"fpu",
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"mmu",
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"sh3",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh4",
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.features = &.{
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"fpu",
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"mmu",
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"sh4",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh4_nofpu",
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.features = &.{
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"mmu",
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"sh4",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh4a",
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.features = &.{
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"fpu",
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"fsca",
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"fsrra",
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"mmu",
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"sh4a",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh4a_nofpu",
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.features = &.{
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"mmu",
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"sh4a",
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},
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},
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.{
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.llvm_name = null,
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.zig_name = "sh4al_dsp",
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.features = &.{
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"dsp",
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"mmu",
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"sh4a",
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},
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},
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},
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},
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.{
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.zig_name = "sparc",
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.llvm = .{
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