update_cpu_features: populate m88k data

lib/std/Target.zig

@@ -758,7 +758,7 @@ pub const kvx = @import("Target/kvx.zig");
 pub const lanai = @import("Target/lanai.zig");
 pub const loongarch = @import("Target/loongarch.zig");
 pub const m68k = @import("Target/m68k.zig");
-pub const m88k = @import("Target/generic.zig");
+pub const m88k = @import("Target/m88k.zig");
 pub const microblaze = @import("Target/generic.zig");
 pub const mips = @import("Target/mips.zig");
 pub const msp430 = @import("Target/msp430.zig");
@@ -2060,6 +2060,7 @@ pub const Cpu = struct {
                 .loongarch32 => &loongarch.cpu.generic_la32,
                 .loongarch64 => &loongarch.cpu.generic_la64,
                 .m68k => &m68k.cpu.m68000,
+                .m88k => &m88k.cpu.m88000,
                 .mips, .mipsel => &mips.cpu.mips32,
                 .mips64, .mips64el => &mips.cpu.mips64,
                 .msp430 => &msp430.cpu.msp430,

lib/std/Target/m88k.zig

@@ -0,0 +1,83 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    isa_88110,
+    sfu1,
+    sfu2,
+    xmem_imm,
+    xrf,
+};
+
+pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).@"enum".field_names.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@backingInt(Feature.isa_88110)] = .{
+        .llvm_name = null,
+        .description = "Enable MC88110 additions to the base instruction set",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sfu1)] = .{
+        .llvm_name = null,
+        .description = "Enable floating-point unit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sfu2)] = .{
+        .llvm_name = null,
+        .description = "Enable graphics unit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.xmem_imm)] = .{
+        .llvm_name = null,
+        .description = "Enable xmem with 16-bit immediate offset",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.xrf)] = .{
+        .llvm_name = null,
+        .description = "Enable extended register file",
+        .dependencies = featureSet(&[_]Feature{
+            .sfu1,
+        }),
+    };
+    const ti = @typeInfo(Feature);
+    for (&result, 0..) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.@"enum".field_names[i];
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const m88000: CpuModel = .{
+        .name = "m88000",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sfu1,
+        }),
+    };
+    pub const m88100: CpuModel = .{
+        .name = "m88100",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sfu1,
+            .xmem_imm,
+        }),
+    };
+    pub const m88110: CpuModel = .{
+        .name = "m88110",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sfu2,
+            .xrf,
+        }),
+    };
+};

lib/std/simd.zig

@@ -35,6 +35,8 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu)
         } else if (cpu.arch.isLoongArch()) {
             if (cpu.has(.loongarch, .lasx)) break :blk 256;
             if (cpu.has(.loongarch, .lsx)) break :blk 128;
+        } else if (cpu.arch == .m88k) {
+            if (cpu.has(.m88k, .sfu2)) break :blk 64;
         } else if (cpu.arch.isMIPS()) {
             if (cpu.has(.mips, .msa)) break :blk 128;
             if (cpu.has(.mips, .mips3d)) break :blk 64;

tools/update_cpu_features.zig

@@ -2824,6 +2824,63 @@ const targets = [_]ArchTarget{
             },
         },
     },
+    .{
+        .zig_name = "m88k",
+        .llvm = null,
+        .extra_features = &.{
+            .{
+                .zig_name = "isa_88110",
+                .desc = "Enable MC88110 additions to the base instruction set",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "sfu1",
+                .desc = "Enable floating-point unit",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "sfu2",
+                .desc = "Enable graphics unit",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "xmem_imm",
+                .desc = "Enable xmem with 16-bit immediate offset",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "xrf",
+                .desc = "Enable extended register file",
+                .deps = &.{"sfu1"},
+            },
+        },
+        .extra_models = &.{
+            .{
+                .llvm_name = null,
+                .zig_name = "m88000",
+                .features = &.{
+                    "sfu1",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "m88100",
+                .features = &.{
+                    "sfu1",
+                    "xmem_imm",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "m88110",
+                .features = &.{
+                    "sfu1",
+                    "sfu2",
+                    "xrf",
+                },
+            },
+        },
+    },
     .{
         .zig_name = "msp430",
         .llvm = .{