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update_cpu_feature: replace generic/baseline riscv models with common arch combos

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Alex Rønne Petersen committed 2026-10-26 11:02:43 +01:00
1 parent dd949d3153
commit 104652f6c6
3 files changed
+300 -50
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lib/std/Target.zig
+4 -4
View File
@@ -2065,8 +2065,8 @@ pub const Cpu = struct {
.powerpc, .powerpcle => &powerpc.cpu.ppc32,
.powerpc64, .powerpc64le => &powerpc.cpu.ppc64,
.propeller => &propeller.cpu.p1,
.riscv32, .riscv32be => &riscv.cpu.generic_rv32,
.riscv64, .riscv64be => &riscv.cpu.generic_rv64,
.riscv32, .riscv32be => &riscv.cpu.rv32i,
.riscv64, .riscv64be => &riscv.cpu.rv64i,
.s390x => &s390x.cpu.arch8,
.sparc => &sparc.cpu.v7,
.sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
@@ -2146,8 +2146,8 @@ pub const Cpu = struct {
else => generic(arch),
},
.powerpc64le => &powerpc.cpu.ppc64le,
.riscv32, .riscv32be => &riscv.cpu.baseline_rv32,
.riscv64, .riscv64be => &riscv.cpu.baseline_rv64,
.riscv32, .riscv32be => &riscv.cpu.rv32gc,
.riscv64, .riscv64be => &riscv.cpu.rv64gc,
.s390x => &s390x.cpu.arch11,
.sparc => switch (os.tag) {
.linux => &sparc.cpu.v9, // glibc does not work with 'plain' v8.
lib/std/Target/riscv.zig
+199 -42
View File
@@ -2482,30 +2482,6 @@ pub const cpu = struct {
.zifencei,
}),
};
pub const baseline_rv32: CpuModel = .{
.name = "baseline_rv32",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.a,
.c,
.d,
.i,
.m,
}),
};
pub const baseline_rv64: CpuModel = .{
.name = "baseline_rv64",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.c,
.d,
.i,
.m,
}),
};
pub const et_soc1: CpuModel = .{
.name = "et_soc1",
.llvm_name = "et-soc1",
@@ -2516,24 +2492,6 @@ pub const cpu = struct {
.xaifet,
}),
};
pub const generic_rv32: CpuModel = .{
.name = "generic_rv32",
.llvm_name = "generic-rv32",
.features = featureSet(&[_]Feature{
.@"32bit",
.i,
.optimized_nf2_segment_load_store,
}),
};
pub const generic_rv64: CpuModel = .{
.name = "generic_rv64",
.llvm_name = "generic-rv64",
.features = featureSet(&[_]Feature{
.@"64bit",
.i,
.optimized_nf2_segment_load_store,
}),
};
pub const mips_p8700: CpuModel = .{
.name = "mips_p8700",
.llvm_name = "mips-p8700",
@@ -2597,6 +2555,205 @@ pub const cpu = struct {
.zifencei,
}),
};
pub const rv32e: CpuModel = .{
.name = "rv32e",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.e,
}),
};
pub const rv32ec: CpuModel = .{
.name = "rv32ec",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.c,
.e,
}),
};
pub const rv32emc: CpuModel = .{
.name = "rv32emc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.c,
.e,
.m,
}),
};
pub const rv32gc: CpuModel = .{
.name = "rv32gc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.a,
.c,
.i,
.m,
.zcd,
.zcf,
.zifencei,
}),
};
pub const rv32i: CpuModel = .{
.name = "rv32i",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.i,
}),
};
pub const rv32im: CpuModel = .{
.name = "rv32im",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.i,
.m,
}),
};
pub const rv32ima: CpuModel = .{
.name = "rv32ima",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.a,
.i,
.m,
}),
};
pub const rv32imac: CpuModel = .{
.name = "rv32imac",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.a,
.c,
.i,
.m,
}),
};
pub const rv32imafc: CpuModel = .{
.name = "rv32imafc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.a,
.c,
.i,
.m,
.zcf,
}),
};
pub const rv32imafdc: CpuModel = .{
.name = "rv32imafdc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.a,
.c,
.i,
.m,
.zcd,
.zcf,
}),
};
pub const rv32imc: CpuModel = .{
.name = "rv32imc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"32bit",
.c,
.i,
.m,
}),
};
pub const rv64gc: CpuModel = .{
.name = "rv64gc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.c,
.i,
.m,
.zcd,
.zifencei,
}),
};
pub const rv64i: CpuModel = .{
.name = "rv64i",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.i,
}),
};
pub const rv64im: CpuModel = .{
.name = "rv64im",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.i,
.m,
}),
};
pub const rv64ima: CpuModel = .{
.name = "rv64ima",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.i,
.m,
}),
};
pub const rv64imac: CpuModel = .{
.name = "rv64imac",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.c,
.i,
.m,
}),
};
pub const rv64imafc: CpuModel = .{
.name = "rv64imafc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.c,
.f,
.i,
.m,
}),
};
pub const rv64imafdc: CpuModel = .{
.name = "rv64imafdc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.a,
.c,
.i,
.m,
.zcd,
}),
};
pub const rv64imc: CpuModel = .{
.name = "rv64imc",
.llvm_name = null,
.features = featureSet(&[_]Feature{
.@"64bit",
.c,
.i,
.m,
}),
};
pub const sifive_7_series: CpuModel = .{
.name = "sifive_7_series",
.llvm_name = "sifive-7-series",
tools/update_cpu_features.zig
+97 -4
View File
@@ -3599,17 +3599,110 @@ const targets = [_]ArchTarget{
.llvm_name = "generic-ooo",
.omit = true,
},
.{
.llvm_name = "generic-rv32",
.omit = true,
},
.{
.llvm_name = "generic-rv64",
.omit = true,
},
},
.extra_models = &.{
.{
.llvm_name = null,
.zig_name = "baseline_rv32",
.features = &.{ "32bit", "a", "c", "d", "f", "i", "m" },
.zig_name = "rv32e",
.features = &.{ "32bit", "e" },
},
.{
.llvm_name = null,
.zig_name = "baseline_rv64",
.features = &.{ "64bit", "a", "c", "d", "f", "i", "m" },
.zig_name = "rv32ec",
.features = &.{ "32bit", "c", "e" },
},
.{
.llvm_name = null,
.zig_name = "rv32emc",
.features = &.{ "32bit", "c", "e", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv32gc",
.features = &.{ "32bit", "a", "c", "d", "i", "m", "zcd", "zcf", "zicsr", "zifencei" },
},
.{
.llvm_name = null,
.zig_name = "rv32i",
.features = &.{ "32bit", "i" },
},
.{
.llvm_name = null,
.zig_name = "rv32im",
.features = &.{ "32bit", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv32ima",
.features = &.{ "32bit", "a", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv32imac",
.features = &.{ "32bit", "a", "c", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv32imafc",
.features = &.{ "32bit", "a", "c", "f", "i", "m", "zcf" },
},
.{
.llvm_name = null,
.zig_name = "rv32imafdc",
.features = &.{ "32bit", "a", "c", "d", "i", "m", "zcd", "zcf" },
},
.{
.llvm_name = null,
.zig_name = "rv32imc",
.features = &.{ "32bit", "c", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv64gc",
.features = &.{ "64bit", "a", "c", "d", "i", "m", "zcd", "zicsr", "zifencei" },
},
.{
.llvm_name = null,
.zig_name = "rv64i",
.features = &.{ "64bit", "i" },
},
.{
.llvm_name = null,
.zig_name = "rv64im",
.features = &.{ "64bit", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv64ima",
.features = &.{ "64bit", "a", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv64imac",
.features = &.{ "64bit", "a", "c", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv64imafc",
.features = &.{ "64bit", "a", "c", "f", "i", "m" },
},
.{
.llvm_name = null,
.zig_name = "rv64imafdc",
.features = &.{ "64bit", "a", "c", "d", "i", "m", "zcd" },
},
.{
.llvm_name = null,
.zig_name = "rv64imc",
.features = &.{ "64bit", "c", "i", "m" },
},
},
},