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Code Activity
41,005 Commits 64 Branches 26 Tags
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Commit Graph
192 Commits
Author SHA1 Message Date
Alex Rønne Petersen 3237f171fd update_cpu_features: populate z80 data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen f2140c7cfb gen_spirv_spec, update_cpu_features: fix some accidentally omitted capabilities 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 6ba6a19a8b gen_spirv_spec, update_cpu_features: fix capabilities missing implied capabilities 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 1ee1c9b1c0 gen_spirv_spec, update_cpu_features: omit provisional spirv features 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen da74d9df7f update_cpu_features: omit SPV_EXT_physical_storage_buffer 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen ea23fdce37 gen_spirv_spec, update_cpu_features: omit v1_0 spirv feature 
It's always implied so it's just a waste of bytes.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 93e6194050 codegen.spirv.spec, std.Target.spirv: regenerate from 1.6.7 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen c41d12dee7 update_cpu_features: remove some legacy leftover spirv features 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 820ee28df0 update_cpu_features: omit matrix spirv feature 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen c7716c1212 update_cpu_features: populate microblaze data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0bb7fc0cd0 update_cpu_features: populate sh data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 8df29bb518 update_cpu_features: populate or1k data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen beadbc63ec update_cpu_features: map cell powerpc model to LLVM's 970 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 1bd2abaf53 update_cpu_features: map e6500 powerpc model to LLVM's e5500 
This is the closest sensible thing for scheduling purposes.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0f100d1987 update_cpu_features: map r3000a and allegrex mips models to mips1/mips2 in LLVM 
Otherwise Clang misclassifies them as mips32r2.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0892046a15 update_cpu_features: map some arm and aarch64 models to LLVM's generic 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen f759705998 update_cpu_features: populate m88k data 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 06555e298d update_cpu_features: rename generic xtensa model to xtensa 
Since it's just the base Xtensa ISA.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 4449211074 update_cpu_features: rename generic arc model to arcv2 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen e80dcf3474 update_cpu_features: rename generic csky model to e2 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen f542e8050e update_cpu_features: rename 64bit_support powerpc feature to 64bit 
For consistency with x86.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 51fdb7063e update_cpu_features: add riscv profile models and flatten the profile features 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 104652f6c6 update_cpu_feature: replace generic/baseline riscv models with common arch combos 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen dd949d3153 update_cpu_features: don't map generic csky model to LLVM's generic 
Clang doesn't recognize it.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 020aa22288 update_cpu_features: flesh out spirv models a bit 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 2361de28fd update_cpu_features: don't map generic_la32 loongarch model to LLVM's generic-la32 
Clang doesn't recognize it.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 1e440e14ef update_cpu_feature: replace generic aarch64 model with architecture level models 
And use armv8a as the generic model.

The old generic model was incoherent; it didn't even have v8a.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen f4fd2f30d0 update_cpu_features: tweak generic csky model 
A truly generic model is not possible for csky, but with this weak, it covers
148 of 151 models. I think that's Good Enough.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 25017aa872 update_cpu_features: remove generic mips model 
We weren't using it for anything and it certainly wasn't "generic".
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 8e553c1691 update_cpu_features: remove generic x86 model 
This model just... didn't make a ton of sense? We also weren't using it for
anything since generic() returns the i86, i386, and x86_64 models.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen cc2431f382 update_cpu_features: remove generic s390x model 
This is just arch8/z10.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 78a614343c update_cpu_features: remove generic hexagon model 
This is just hexagonv60.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 1dd5f188ae update_cpu_features: remove generic sparc model 
This is just v7.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 6ed004cad7 update_cpu_features: remove generic lanai model 
This is just v11.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 2b5270107c update_cpu_features: remove mips float ABI features 
Floating point on this god-forsaken architecture is a disaster without equal.
I'm actually mad at everyone who contributed to this fucking mess.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen dd136e8604 update_cpu_features: clean up mips features a bit 
* Remove codegen options
* Flatten microarchitecture features
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 63f374719a update_cpu_features: remove soft_float sparc feature 
LLVM takes this from the target triple, which is what we want.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 18dacc3689 update_cpu_features: remove soft_float arm feature 
LLVM takes this from the target triple, which is what we want.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen d7e6ccac78 update_cpu_features: remove generic and generic-hsa amdgcn models 
These literally don't mean anything.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 46eb8d9dd1 update_cpu_features: refactor amdgcn family features 
The gfx* family features are redundant information. Remove them and replace them
with the gfx*-insts features intead, and add missing dependency relationships.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen b94d7ad236 update_cpu_features: remove some amdgcn codegen options 
The sramecc and xnack features will be removed with LLVM 24. For now, we just
omit them from std.Target.amdgcn when generating it.

closes https://github.com/ziglang/zig/issues/23539
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen de0818df89 update_cpu_features: remove some x86 codegen options 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 1940ae589b update_cpu_features: remove x86 soft_float feature 
Soft float on x86 now requires setting an appropriate target triple, such as
x86-freestanding-eabi. In the future, this will become less weird when we add a
float ABI component to the target syntax.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 24643dfec1 update_cpu_features: remove thumb_mode arm feature 
This is now derived from the target's arch tag in the compiler.
 2026-10-26 11:02:42 +01:00
Alex Rønne Petersen 2fcfe11af3 update_cpu_features: remove no_unaligned_access from thunderx3t110 aarch64 model 
LLVM includes it for performance reasons. That's all well and good, but the same
argument could be used for basically every single aarch64 model. And the feature
is supposed to indicate whether an unaligned access traps, not whether it's
slow.
 2026-10-26 11:02:42 +01:00
Alex Rønne Petersen 8a6179b923 update_cpu_features: remove some aarch64 codegen options 2026-10-26 11:02:42 +01:00
Alex Rønne Petersen 9a5d8fbad9 update_cpu_features: flatten some aarch64 model family features 2026-10-26 11:02:42 +01:00
Alex Rønne Petersen 79a849bd43 std.Target.mips: regenerate from LLVM 23.1.4 2026-10-26 11:02:42 +01:00
Alex Rønne Petersen 72a87418ac update_cpu_features: clean up arm features a bit 
* Remove codegen options
* Flatten microarchitecture features
 2026-10-26 11:02:42 +01:00
Alex Rønne Petersen e887cc7bc5 update_cpu_features: make strict/unaligned access feature names consistent 2026-10-26 11:02:42 +01:00