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Code Activity
41,005 Commits 64 Branches 26 Tags
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Commit Graph
16990 Commits
Author SHA1 Message Date
Masa Bence 1420479be7 std: update Arraylist in unicode.zig to unmanaged 2026-10-27 19:37:22 +01:00
Francisco Nevitt Gonçalves a8165f8e8d Add missing flush in FuzzTestRunner.saveCrash 
This was causing crash files to be truncated, preventing users from
reproducing fuzzing crashes.
 2026-10-27 17:37:42 +01:00
akbarhusain 167a8f987f std.Io: fix flush spin on failing io 2026-10-27 17:35:34 +01:00
Lwazi Dube 6b685a440e Fix invalid bx instuction error when building for strongarm 
The following command was used for building:
zig build -Dtarget=arm-freestanding -Dcpu=strongarm1110 --release=safe
 2026-10-27 17:34:13 +01:00
Matthew Lugg f6751410e9 build: run some tests with -flegalize-all 
It's useful to run both a little-endian and a big-endian target here,
because some legalizations are susceptible to endianness bugs, e.g. any
related to bitwise operations or to `packed` (aka `bitpack`) types.

When modifying legalizations or adding new ones, they can be tested by
running `zig build test-modules -Donly-legalize` to limit to the targets
which pass `-flegalize-all`.

This makes it much easier to facilitate external contributions towards
https://codeberg.org/ziglang/zig/issues/36719, and will prevent
legalization passes from bit-rotting in the future.
 2026-10-26 14:17:03 +00:00
Alex Rønne Petersen 2d6ff903a1 std.Target: add z80 arch tag and ABI info 
Also fix cCharSignedness() for ez80.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 3237f171fd update_cpu_features: populate z80 data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen f2140c7cfb gen_spirv_spec, update_cpu_features: fix some accidentally omitted capabilities 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 6ba6a19a8b gen_spirv_spec, update_cpu_features: fix capabilities missing implied capabilities 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 38186a3cfe std.Target: update some baseline() CPU models 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 1ee1c9b1c0 gen_spirv_spec, update_cpu_features: omit provisional spirv features 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen da74d9df7f update_cpu_features: omit SPV_EXT_physical_storage_buffer 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen ea23fdce37 gen_spirv_spec, update_cpu_features: omit v1_0 spirv feature 
It's always implied so it's just a waste of bytes.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 93e6194050 codegen.spirv.spec, std.Target.spirv: regenerate from 1.6.7 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen c41d12dee7 update_cpu_features: remove some legacy leftover spirv features 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 820ee28df0 update_cpu_features: omit matrix spirv feature 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 766840daf1 std.Target: remove the kalimba arch tag 
What little target info we had for this was incomplete/wrong, and it's
annoyingly difficult to get reliable information about it because Qualcomm
doesn't publish the documentation. So just delete it.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen c7716c1212 update_cpu_features: populate microblaze data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0bb7fc0cd0 update_cpu_features: populate sh data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 2d2de5f69e std.Target: fix Abi.default() for sh-openbsd and sh(eb)-netbsd 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 8df29bb518 update_cpu_features: populate or1k data 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen beadbc63ec update_cpu_features: map cell powerpc model to LLVM's 970 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 1bd2abaf53 update_cpu_features: map e6500 powerpc model to LLVM's e5500 
This is the closest sensible thing for scheduling purposes.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0f100d1987 update_cpu_features: map r3000a and allegrex mips models to mips1/mips2 in LLVM 
Otherwise Clang misclassifies them as mips32r2.
 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen 0892046a15 update_cpu_features: map some arm and aarch64 models to LLVM's generic 2026-10-26 11:02:44 +01:00
Alex Rønne Petersen f759705998 update_cpu_features: populate m88k data 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 06555e298d update_cpu_features: rename generic xtensa model to xtensa 
Since it's just the base Xtensa ISA.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 4449211074 update_cpu_features: rename generic arc model to arcv2 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen e80dcf3474 update_cpu_features: rename generic csky model to e2 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 4d94cf182f std.hash.crc: fix x86_64 + crc32 feature check 
The 64bit feature just indicates that the model has long mode support; it does
not necessarily mean that we are compiling for 64-bit.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen f542e8050e update_cpu_features: rename 64bit_support powerpc feature to 64bit 
For consistency with x86.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 51fdb7063e update_cpu_features: add riscv profile models and flatten the profile features 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 104652f6c6 update_cpu_feature: replace generic/baseline riscv models with common arch combos 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen dd949d3153 update_cpu_features: don't map generic csky model to LLVM's generic 
Clang doesn't recognize it.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen b012a84c34 std.Target: pick better baseline models for spirv 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen cdadcb2e1d std.Target: adjust OS min/max version ranges for GPU targets 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 020aa22288 update_cpu_features: flesh out spirv models a bit 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 2361de28fd update_cpu_features: don't map generic_la32 loongarch model to LLVM's generic-la32 
Clang doesn't recognize it.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 1e440e14ef update_cpu_feature: replace generic aarch64 model with architecture level models 
And use armv8a as the generic model.

The old generic model was incoherent; it didn't even have v8a.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen f4fd2f30d0 update_cpu_features: tweak generic csky model 
A truly generic model is not possible for csky, but with this weak, it covers
148 of 151 models. I think that's Good Enough.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 25017aa872 update_cpu_features: remove generic mips model 
We weren't using it for anything and it certainly wasn't "generic".
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 8e553c1691 update_cpu_features: remove generic x86 model 
This model just... didn't make a ton of sense? We also weren't using it for
anything since generic() returns the i86, i386, and x86_64 models.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen cc2431f382 update_cpu_features: remove generic s390x model 
This is just arch8/z10.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 78a614343c update_cpu_features: remove generic hexagon model 
This is just hexagonv60.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 1dd5f188ae update_cpu_features: remove generic sparc model 
This is just v7.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 6ed004cad7 update_cpu_features: remove generic lanai model 
This is just v11.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 2b5270107c update_cpu_features: remove mips float ABI features 
Floating point on this god-forsaken architecture is a disaster without equal.
I'm actually mad at everyone who contributed to this fucking mess.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen dd136e8604 update_cpu_features: clean up mips features a bit 
* Remove codegen options
* Flatten microarchitecture features
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 0d142b9e17 std.Target: remove amdpal and mesa3d OS tags 
* mesa3d is for internal use in Mesa's shader compilation pipeline. This never
  really made sense to have in Zig.
* amdpal is for LLPC, part of AMDVLK, which AMD discontinued development of in
  favor of RADV in 2025.

Follow-up work: Removing the amdgcn_cs calling convention.
 2026-10-26 11:02:43 +01:00
Alex Rønne Petersen 63f374719a update_cpu_features: remove soft_float sparc feature 
LLVM takes this from the target triple, which is what we want.
 2026-10-26 11:02:43 +01:00