diff --git a/CMakeLists.txt b/CMakeLists.txt index fd8a347004..71f2ae5f42 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -627,8 +627,8 @@ else() set(ZIG2_COMPILE_FLAGS "-std=c99 -Oz -fno-sanitize=undefined -fno-stack-protector -fno-strict-aliasing") # Must match the condition in build.zig. if(ZIG_HOST_TARGET_ARCH MATCHES "^(arm|thumb)(eb)?$" OR ZIG_HOST_TARGET_ARCH EQUAL "hexagon" OR ZIG_HOST_TARGET_ARCH MATCHES "^powerpc(64)?(le)?$") - set(ZIG1_COMPILE_FLAGS "${ZIG1_COMPILE_FLAGS} -ffunction-sections -fdata-sections") - set(ZIG2_COMPILE_FLAGS "${ZIG2_COMPILE_FLAGS} -ffunction-sections -fdata-sections") + set(ZIG1_COMPILE_FLAGS "${ZIG1_COMPILE_FLAGS} -ffunction-sections") + set(ZIG2_COMPILE_FLAGS "${ZIG2_COMPILE_FLAGS} -ffunction-sections") endif() if (CMAKE_C_COMPILER_ID STREQUAL "GNU") # Prevent GCC from miscompiling 'zig2.c'. See also 'GCC_BUG_119085_PRESENT' workaround details in 'bootstrap.c'. diff --git a/build.zig b/build.zig index ffc7b37d58..0a8bd4de69 100644 --- a/build.zig +++ b/build.zig @@ -930,24 +930,6 @@ fn addCompilerStep(b: *std.Build, options: AddCompilerModOptions) *std.Build.Ste }); exe.stack_size = stack_size; - // Must match the condition in CMakeLists.txt. - const function_data_sections = switch (options.target.result.cpu.arch) { - .arm, - .armeb, - .thumb, - .thumbeb, - .hexagon, - .powerpc, - .powerpcle, - .powerpc64, - .powerpc64le, - => true, - else => false, - }; - - exe.link_function_sections = function_data_sections; - exe.link_data_sections = function_data_sections; - return exe; } diff --git a/lib/compiler/Maker/Step/Compile.zig b/lib/compiler/Maker/Step/Compile.zig index 4fbe6e4679..8afb5ec881 100644 --- a/lib/compiler/Maker/Step/Compile.zig +++ b/lib/compiler/Maker/Step/Compile.zig @@ -630,8 +630,8 @@ fn lowerZigArgs( try addBool(gpa, zig_args, "--eh-frame-hdr", conf_comp.flags.link_eh_frame_hdr); try addBool(gpa, zig_args, "--emit-relocs", conf_comp.flags.link_emit_relocs); - try addBool(gpa, zig_args, "-ffunction-sections", conf_comp.flags.link_function_sections); - try addBool(gpa, zig_args, "-fdata-sections", conf_comp.flags.link_data_sections); + try addFlag(gpa, zig_args, "function-sections", conf_comp.flags4.function_sections.toBool()); + try addFlag(gpa, zig_args, "data-sections", conf_comp.flags4.data_sections.toBool()); if (conf_comp.flags2.link_gc_sections.toBool()) |x| try zig_args.append(gpa, if (x) "--gc-sections" else "--no-gc-sections"); diff --git a/lib/compiler/aro/aro/Compilation.zig b/lib/compiler/aro/aro/Compilation.zig index 8d893abfc3..f9d995cf2d 100644 --- a/lib/compiler/aro/aro/Compilation.zig +++ b/lib/compiler/aro/aro/Compilation.zig @@ -729,10 +729,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { try define(w, "__APX_F__"); } - if (target.cpu.hasAll(.x86, &.{ .egpr, .inline_asm_use_gpr32 })) { - try define(w, "__APX_INLINE_ASM_USE_GPR32__"); - } - if (target.cpu.has(.x86, .cx8)) { try define(w, "__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8"); } @@ -800,18 +796,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { try w.print("#define _MIPS_ARCH_{s} 1\n", .{upper}); } - if (!target.cpu.has(.mips, .noabicalls)) { - try define(w, "__mips_abicalls"); - if (target.os.tag.isBSD()) { - try define(w, "__ABICALLS__"); - } - } - - if (target.cpu.has(.mips, .soft_float)) { - try define(w, "__mips_soft_float"); - } else { - try define(w, "__mips_hard_float"); - } if (target.cpu.has(.mips, .single_float)) { try define(w, "__mips_single_float"); } @@ -825,12 +809,9 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { const fpset: u8 = if (target.defaultMipsFpMode() == .fp64 or target.cpu.has(.mips, .single_float)) 32 else 16; try w.print("#define _MIPS_FPSET {d}\n", .{fpset}); - const spfpset: u8 = if (target.cpu.has(.mips, .nooddspreg) or - target.defaultMipsFpMode() == .fpxx) 16 else 32; + const spfpset: u8 = if (target.defaultMipsFpMode() == .fpxx) 16 else 32; try w.print("#define _MIPS_SPFPSET {d}\n", .{spfpset}); } - if (target.cpu.has(.mips, .mips16)) try define(w, "__mips16"); - if (target.cpu.has(.mips, .micromips)) try define(w, "__mips_micromips"); if (target.cpu.has(.mips, .nan2008)) try define(w, "__mips_nan2008"); if (target.cpu.has(.mips, .abs2008)) try define(w, "__mips_abs2008"); if (target.cpu.has(.mips, .dspr3)) { @@ -918,7 +899,7 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { } } - if (target.cpu.has(.arm, .thumb2) or target.cpu.has(.arm, .thumb_mode)) { + if (target.cpu.has(.arm, .thumb2) or target.cpu.arch.isThumb()) { try define(w, "__thumb__"); } // ARM ISA means we are not M profile @@ -1017,7 +998,7 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { try w.print("#define __ARM_FEATURE_LDREX 0x{x}\n", .{@as(u4, @bitCast(ldrex))}); } - if (!target.cpu.has(.arm, .strict_align)) { + if (!target.cpu.has(.arm, .no_unaligned_access)) { try define(w, "__ARM_FEATURE_UNALIGNED"); } @@ -1136,9 +1117,6 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { try define(w, "__ARM_FEATURE_SME"); try define(w, "__ARM_FEATURE_LOCALLY_STREAMING"); } - if (target.cpu.has(.aarch64, .fmv)) { - try define(w, "__HAVE_FUNCTION_MULTI_VERSIONING"); - } if (target.cpu.has(.aarch64, .sha3)) { try define(w, "__ARM_FEATURE_SHA3"); try define(w, "__ARM_FEATURE_SHA512"); @@ -1147,7 +1125,7 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { try define(w, "__ARM_FEATURE_SM3"); try define(w, "__ARM_FEATURE_SM4"); } - if (!target.cpu.has(.aarch64, .strict_align)) { + if (!target.cpu.has(.aarch64, .no_unaligned_access)) { try define(w, "__ARM_FEATURE_UNALIGNED"); } if (target.cpu.hasAll(.aarch64, &.{ .neon, .fullfp16 })) { @@ -1228,10 +1206,10 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { try define(w, "__s390x__"); try define(w, "__zarch__"); - if (target.cpu.has(.s390x, .transactional_execution)) { + if (target.cpu.has(.s390x, .te)) { try define(w, "__HTM__"); } - if (target.cpu.has(.s390x, .vector)) { + if (target.cpu.has(.s390x, .vx)) { try define(w, "__VX__"); } }, diff --git a/lib/compiler/aro/aro/Target.zig b/lib/compiler/aro/aro/Target.zig index 609ffe1377..bb808bb98e 100644 --- a/lib/compiler/aro/aro/Target.zig +++ b/lib/compiler/aro/aro/Target.zig @@ -116,7 +116,6 @@ pub const SubArch = enum { } else if (arch.isSpirv()) { const spirv = std.Target.spirv.Feature; return @backingInt(switch (sub) { - .spirv_v10 => spirv.v1_0, .spirv_v11 => spirv.v1_1, .spirv_v12 => spirv.v1_2, .spirv_v13 => spirv.v1_3, @@ -1085,6 +1084,7 @@ pub fn get32BitArchVariant(target: *const Target) ?Target { .s390x, .spork8, .ve, + .z80, => return null, .arc, @@ -1094,7 +1094,6 @@ pub fn get32BitArchVariant(target: *const Target) ?Target { .csky, .hexagon, .hppa, - .kalimba, .lanai, .loongarch32, .m68k, @@ -1152,7 +1151,6 @@ pub fn get64BitArchVariant(target: *const Target) ?Target { .csky, .ez80, .hexagon, - .kalimba, .lanai, .m68k, .m88k, @@ -1167,6 +1165,7 @@ pub fn get64BitArchVariant(target: *const Target) ?Target { .xcore, .xtensa, .xtensaeb, + .z80, => return null, .aarch64_be, @@ -1274,7 +1273,6 @@ pub fn toLLVMTriple(target: *const Target, buf: []u8) []const u8 { .ez80 => "ez80", .hppa => "hppa", .hppa64 => "hppa64", - .kalimba => "kalimba", .kvx => "kvx", .microblaze => "microblaze", .microblazeel => "microblazeel", @@ -1286,13 +1284,13 @@ pub fn toLLVMTriple(target: *const Target, buf: []u8) []const u8 { .spork8 => "spork8", .x86_16 => "i86", .xtensaeb => "xtensaeb", + .z80 => "z80", }; writer.writeAll(llvm_arch) catch unreachable; writer.writeByte('-') catch unreachable; const llvm_os = switch (target.os.tag) { .amdhsa => "amdhsa", - .amdpal => "amdpal", .cuda => "cuda", .dragonfly => "dragonfly", .driverkit => "driverkit", @@ -1307,7 +1305,6 @@ pub fn toLLVMTriple(target: *const Target, buf: []u8) []const u8 { .linux => "linux", .macos => "macosx", .managarm => "managarm", - .mesa3d => "mesa3d", .netbsd => "netbsd", .nvcl => "nvcl", .openbsd => "openbsd", @@ -1410,8 +1407,6 @@ pub fn isPIEDefault(target: *const Target) DefaultPIStatus { .cuda, .amdhsa, - .amdpal, - .mesa3d, .ps4, .ps5, @@ -1484,8 +1479,6 @@ pub fn isPICdefault(target: *const Target) DefaultPIStatus { .driverkit, .amdhsa, - .amdpal, - .mesa3d, .ps4, .ps5, @@ -1551,7 +1544,7 @@ pub fn isPICdefault(target: *const Target) DefaultPIStatus { pub fn isPICDefaultForced(target: *const Target) DefaultPIStatus { return switch (target.os.tag) { - .amdhsa, .amdpal, .mesa3d => .yes, + .amdhsa => .yes, .haiku, .dragonfly, diff --git a/lib/compiler_rt/atomics.zig b/lib/compiler_rt/atomics.zig index f04eb95090..8ef09e7e18 100644 --- a/lib/compiler_rt/atomics.zig +++ b/lib/compiler_rt/atomics.zig @@ -30,7 +30,7 @@ const largest_atomic_size = switch (arch) { // On SPARC systems that lacks CAS and/or swap instructions, the only // available atomic operation is a test-and-set (`ldstub`), so we force // every atomic memory access to go through the lock. - .sparc => if (builtin.cpu.has(.sparc, .hasleoncasa)) @sizeOf(usize) else 0, + .sparc => if (builtin.cpu.hasAny(.sparc, &.{ .hasleoncasa, .v9 })) @sizeOf(usize) else 0, // XXX: On x86/x86_64 we could check the presence of cmpxchg8b/cmpxchg16b // and set this parameter accordingly. diff --git a/lib/compiler_rt/elf/tls.zig b/lib/compiler_rt/elf/tls.zig index c93dc3d258..4b67541c22 100644 --- a/lib/compiler_rt/elf/tls.zig +++ b/lib/compiler_rt/elf/tls.zig @@ -44,8 +44,9 @@ comptime { /// Represents an ELF TLS variant. /// -/// In all variants, the TP and the TLS blocks must be aligned to the `p_align` value in the -/// `PT.TLS` ELF program header. Everything else has natural alignment. +/// In all variants, TLS blocks must be aligned to the `p_align` value in the `PT.TLS` ELF program +/// header. The TP is usually similarly aligned, with one particular exception for the modified +/// Variant I noted below. Everything else has natural alignment. /// /// The location of the DTV does not actually matter. For simplicity, we put it in the TLS area, but /// there is no actual ABI requirement that it reside there. @@ -71,7 +72,8 @@ const Variant = enum { /// `-- The TP register points here (*inside* the TLS blocks). /// /// The offset from the start of the TLS blocks to the TP register is `current_tp_offset`. It - /// may be zero, in which case the TP register points to the start of the TLS blocks. + /// may be zero, in which case the TP register points to the end of the ABI TCB, which is + /// usually the start of the TLS blocks, but see `blocksGap`. /// /// The first (and only) word in the ABI TCB points to the DTV. I_modified, @@ -145,6 +147,20 @@ const current_tp_offset = switch (native_arch) { else => 0, }; +/// Only used by the modified Variant I. Calculates the number of padding bytes between the end of +/// the ABI TCB and the start of the TLS blocks. +/// +/// Inline because TLS is not set up yet. +inline fn blocksGap(alignment: usize) usize { + return switch (native_arch) { + // https://git.musl-libc.org/cgit/musl/commit/?id=de5536d827114ebc6b6db7800216610385663ad2 + // + // This is arguably a binutils bug, but I guess we all just have to live with it now. + .or1k => alignForward(16, alignment) - 16, + else => 0, + }; +} + /// Usually only used by the modified Variant I. const current_dtv_offset = switch (native_arch) { .m68k, @@ -548,16 +564,18 @@ fn computeAreaDesc(phdrs: []elf.ElfN.Phdr) void { var l: usize = 0; dtv_offset = l; l += @sizeOf(Dtv); - // In this variant, the TLS blocks must begin immediately after the end of the ABI TCB, - // with the TP pointing to the beginning of the TLS blocks. Add padding so that the TP - // (`abi_tcb_offset`) is aligned to `align_factor` and the `ZigTcb` structure can be - // found by subtracting `@sizeOf(AbiTcb) + @sizeOf(ZigTcb)` from the TP. - const delta = (l + @sizeOf(ZigTcb) + @sizeOf(AbiTcb)) & (align_factor - 1); + // In this variant, the TLS blocks begin `blocksGap()` bytes (usually zero) after the + // end of the ABI TCB. Add padding so that the TLS blocks are aligned to `align_factor` + // and the `ZigTcb` structure can be found by subtracting + // `@sizeOf(AbiTcb) + @sizeOf(ZigTcb)` from the end of the ABI TCB. + const gap = blocksGap(align_factor); + const delta = (l + @sizeOf(ZigTcb) + @sizeOf(AbiTcb) + gap) & (align_factor - 1); if (delta > 0) l += align_factor - delta; l += @sizeOf(ZigTcb); abi_tcb_offset = l; l += @sizeOf(AbiTcb); + l += gap; block_offset = l; l += block_size; break :blk l; @@ -648,7 +666,8 @@ fn __zig_elf_static_tls_fill(area: [*]u8) callconv(.c) usize { // the pointer arithmetic involving the TP is done with wrapping semantics. return @intFromPtr(area) +% switch (current_variant) { .I_original, .II => area_info.abi_tcb.offset, - .I_modified => area_info.block.offset +% current_tp_offset, + // This expression must account for the `blocksGap() != 0` possibility. + .I_modified => area_info.abi_tcb.offset +% @sizeOf(AbiTcb) +% current_tp_offset, }; } @@ -745,6 +764,9 @@ fn __tls_get_addr(ti: *const TlsIndex) callconv(.c) *anyopaque { const tp = getThreadPointer(); const block = switch (current_variant) { .I_original => tp -% area_info.abi_tcb.offset +% area_info.block.offset, + // For `blocksGap() != 0`, this intentionally computes the end of the ABI TCB rather than + // the beginning of the TLS blocks. The linker will include the `blocksGap()` in the offset + // written into `ti.offset`. .I_modified => tp -% current_tp_offset, // The `.I_original` approach would also work for `.II`, but there is an // alternative strategy which is one less operation: diff --git a/lib/std/Build/Configuration.zig b/lib/std/Build/Configuration.zig index bb71c44ad6..126f70730e 100644 --- a/lib/std/Build/Configuration.zig +++ b/lib/std/Build/Configuration.zig @@ -1000,8 +1000,6 @@ pub const Step = extern struct { shared_memory: bool, link_eh_frame_hdr: bool, link_emit_relocs: bool, - link_function_sections: bool, - link_data_sections: bool, linker_dynamicbase: bool, link_z_notext: bool, link_z_relro: bool, @@ -1012,6 +1010,7 @@ pub const Step = extern struct { force_load_objc: bool, discard_local_symbols: bool, mingw_unicode_entry_point: bool, + _: u2 = 0, }; pub const Flags2 = packed struct(u32) { @@ -1077,7 +1076,9 @@ pub const Step = extern struct { generated_llvm_ir: bool, generated_h: bool, incremental: DefaultingBool, - _: u7 = 0, + function_sections: DefaultingBool, + data_sections: DefaultingBool, + _: u3 = 0, }; pub fn isDynamicLibrary(compile: *const Compile) bool { @@ -2388,7 +2389,6 @@ pub const TargetQuery = struct { hexagon, hppa, hppa64, - kalimba, kvx, lanai, loongarch32, @@ -2433,6 +2433,7 @@ pub const TargetQuery = struct { xcore, xtensa, xtensaeb, + z80, default, @@ -2488,9 +2489,7 @@ pub const TargetQuery = struct { emscripten, wasi, amdhsa, - amdpal, cuda, - mesa3d, nvcl, opencl, opengl, diff --git a/lib/std/Build/Serialize.zig b/lib/std/Build/Serialize.zig index 3cf0ca9466..3a28c7caa5 100644 --- a/lib/std/Build/Serialize.zig +++ b/lib/std/Build/Serialize.zig @@ -132,8 +132,6 @@ pub fn write(b: *std.Build, wc: *Configuration.Wip, writer: *std.Io.Writer) !voi .shared_memory = c.shared_memory, .link_eh_frame_hdr = c.link_eh_frame_hdr, .link_emit_relocs = c.link_emit_relocs, - .link_function_sections = c.link_function_sections, - .link_data_sections = c.link_data_sections, .linker_dynamicbase = c.linker_dynamicbase, .link_z_notext = c.link_z_notext, .link_z_relro = c.link_z_relro, @@ -218,6 +216,8 @@ pub fn write(b: *std.Build, wc: *Configuration.Wip, writer: *std.Io.Writer) !voi .generated_llvm_ir = c.generated_llvm_ir != .none, .generated_h = c.generated_h != .none, .incremental = .init(c.incremental), + .function_sections = .init(c.function_sections), + .data_sections = .init(c.data_sections), }, .root_module = try s.addModule(c.root_module), .root_name = try wc.addString(c.name), diff --git a/lib/std/Build/Step/Compile.zig b/lib/std/Build/Step/Compile.zig index 6d1c1ec4c4..12702dc393 100644 --- a/lib/std/Build/Step/Compile.zig +++ b/lib/std/Build/Step/Compile.zig @@ -109,11 +109,11 @@ link_emit_relocs: bool = false, /// Place every function in its own section so that unused ones may be /// safely garbage-collected during the linking phase. -link_function_sections: bool = false, +function_sections: ?bool = null, -/// Place every data in its own section so that unused ones may be +/// Place every datum in its own section so that unused ones may be /// safely garbage-collected during the linking phase. -link_data_sections: bool = false, +data_sections: ?bool = null, /// Remove functions and data that are unreachable by the entry point or /// exported symbols. diff --git a/lib/std/Target.zig b/lib/std/Target.zig index 28afc9d2ca..46a4c7fded 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -62,9 +62,7 @@ pub const Os = struct { wasi, amdhsa, - amdpal, cuda, - mesa3d, nvcl, opencl, opengl, @@ -171,8 +169,6 @@ pub const Os = struct { .emscripten, - .mesa3d, - .ashetos, => .none, @@ -205,7 +201,6 @@ pub const Os = struct { .wasi, .amdhsa, - .amdpal, .cuda, .nvcl, .opencl, @@ -410,8 +405,6 @@ pub const Os = struct { .emscripten, - .mesa3d, - .ashetos, => .{ .none = {} }, @@ -668,12 +661,6 @@ pub const Os = struct { .max = .{ .major = 7, .minor = 2, .patch = 3 }, }, }, - .amdpal => .{ - .semver = .{ - .min = .{ .major = 1, .minor = 1, .patch = 0 }, - .max = .{ .major = 3, .minor = 5, .patch = 0 }, - }, - }, .cuda => .{ .semver = .{ .min = .{ .major = 12, .minor = 5, .patch = 0 }, @@ -684,26 +671,32 @@ pub const Os = struct { .opencl, => .{ .semver = .{ - .min = .{ .major = 2, .minor = 2, .patch = 0 }, - .max = .{ .major = 3, .minor = 0, .patch = 19 }, + .min = .{ .major = 2, .minor = 1, .patch = 0 }, + .max = .{ .major = 3, .minor = 1, .patch = 19 }, }, }, .opengl => .{ .semver = .{ - .min = .{ .major = 4, .minor = 5, .patch = 0 }, + .min = .{ .major = 4, .minor = 6, .patch = 0 }, .max = .{ .major = 4, .minor = 6, .patch = 0 }, }, }, .tios => .{ - .semver = .{ - .min = .{ .major = 5, .minor = 0, .patch = 0 }, - .max = .{ .major = 5, .minor = 8, .patch = 4 }, + .semver = switch (arch) { + .z80 => .{ + .min = .{ .major = 1, .minor = 3, .patch = 0 }, + .max = .{ .major = 4, .minor = 2, .patch = 0 }, + }, + else => .{ + .min = .{ .major = 5, .minor = 0, .patch = 0 }, + .max = .{ .major = 5, .minor = 8, .patch = 4 }, + }, }, }, .vulkan => .{ .semver = .{ - .min = .{ .major = 1, .minor = 2, .patch = 0 }, - .max = .{ .major = 1, .minor = 4, .patch = 352 }, + .min = .{ .major = 1, .minor = 0, .patch = 0 }, + .max = .{ .major = 1, .minor = 4, .patch = 366 }, }, }, }; @@ -766,22 +759,21 @@ pub const bpf = @import("Target/bpf.zig"); pub const csky = @import("Target/csky.zig"); pub const hexagon = @import("Target/hexagon.zig"); pub const hppa = @import("Target/hppa.zig"); -pub const kalimba = @import("Target/generic.zig"); pub const kvx = @import("Target/kvx.zig"); pub const lanai = @import("Target/lanai.zig"); pub const loongarch = @import("Target/loongarch.zig"); pub const m68k = @import("Target/m68k.zig"); -pub const m88k = @import("Target/generic.zig"); -pub const microblaze = @import("Target/generic.zig"); +pub const m88k = @import("Target/m88k.zig"); +pub const microblaze = @import("Target/microblaze.zig"); pub const mips = @import("Target/mips.zig"); pub const msp430 = @import("Target/msp430.zig"); pub const nvptx = @import("Target/nvptx.zig"); -pub const or1k = @import("Target/generic.zig"); +pub const or1k = @import("Target/or1k.zig"); pub const powerpc = @import("Target/powerpc.zig"); pub const propeller = @import("Target/propeller.zig"); pub const riscv = @import("Target/riscv.zig"); pub const s390x = @import("Target/s390x.zig"); -pub const sh = @import("Target/generic.zig"); +pub const sh = @import("Target/sh.zig"); pub const sparc = @import("Target/sparc.zig"); pub const spirv = @import("Target/spirv.zig"); pub const spork8 = @import("Target/generic.zig"); @@ -790,7 +782,7 @@ pub const wasm = @import("Target/wasm.zig"); pub const x86 = @import("Target/x86.zig"); pub const xcore = @import("Target/xcore.zig"); pub const xtensa = @import("Target/xtensa.zig"); -pub const z80 = @import("Target/generic.zig"); +pub const z80 = @import("Target/z80.zig"); pub const Abi = enum { none, @@ -918,6 +910,8 @@ pub const Abi = enum { // Soft float tends to be more common for MIPS. .mips, .mipsel, + .sh, + .sheb, => .eabi, else => .none, }, @@ -925,14 +919,19 @@ pub const Abi = enum { .arm, => .eabi, .powerpc, + .sh, => .eabihf, else => .none, }, .windows => .gnu, .uefi => .msvc, + .gba => .eabi, .@"3ds" => .eabihf, .wiiu => .eabihf, - .gba => .eabi, + .@"switch" => switch (arch) { + .arm => .eabihf, + else => .none, + }, .psx => .eabi, .ps3 => .ilp32, .psp => .eabihf, @@ -953,13 +952,10 @@ pub const Abi = enum { .tvos, .visionos, .watchos, - .@"switch", .ps4, .ps5, .amdhsa, - .amdpal, .cuda, - .mesa3d, .nvcl, .opencl, .opengl, @@ -1097,10 +1093,8 @@ pub fn toElfMachine(target: *const Target) std.elf.EM { .avr => .AVR, .bpfeb, .bpfel => .BPF, .csky => .CSKY, - .ez80 => .Z80, .hexagon => .QDSP6, .hppa, .hppa64 => .PARISC, - .kalimba => .CSR_KALIMBA, .kvx => .KVX, .lanai => .LANAI, .loongarch32, .loongarch64 => .LOONGARCH, @@ -1116,13 +1110,14 @@ pub fn toElfMachine(target: *const Target) std.elf.EM { .riscv32, .riscv32be, .riscv64, .riscv64be => .RISCV, .s390x => .S390, .sh, .sheb => .SH, - .sparc => if (target.cpu.hasAny(.sparc, &.{ .v8plus, .v9 })) .SPARC32PLUS else .SPARC, + .sparc => if (target.cpu.has(.sparc, .v9)) .SPARC32PLUS else .SPARC, .sparc64 => .SPARCV9, .ve => .VE, .x86_16, .x86 => .@"386", .x86_64 => .X86_64, .xcore => .XCORE, .xtensa, .xtensaeb => .XTENSA, + .z80, .ez80 => .Z80, .nvptx, .nvptx64, @@ -1166,7 +1161,6 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE { .hexagon, .hppa, .hppa64, - .kalimba, .kvx, .lanai, .m88k, @@ -1190,6 +1184,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE { .sparc64, .spirv32, .spirv64, + .spork8, .thumbeb, .ve, .wasm32, @@ -1198,7 +1193,7 @@ pub fn toCoffMachine(target: *const Target) std.coff.IMAGE.FILE.MACHINE { .xcore, .xtensa, .xtensaeb, - .spork8, + .z80, => .UNKNOWN, }; } @@ -1375,7 +1370,6 @@ pub const Cpu = struct { hexagon, hppa, hppa64, - kalimba, kvx, lanai, loongarch32, @@ -1420,6 +1414,7 @@ pub const Cpu = struct { xcore, xtensa, xtensaeb, + z80, /// An architecture family can encompass multiple architectures as represented by `Arch`. /// For a given family tag, it is guaranteed that an `std.Target.` namespace exists @@ -1435,7 +1430,6 @@ pub const Cpu = struct { csky, hexagon, hppa, - kalimba, kvx, lanai, loongarch, @@ -1472,10 +1466,8 @@ pub const Cpu = struct { .avr => .avr, .bpfeb, .bpfel => .bpf, .csky => .csky, - .ez80 => .z80, .hexagon => .hexagon, .hppa, .hppa64 => .hppa, - .kalimba => .kalimba, .kvx => .kvx, .lanai => .lanai, .loongarch32, .loongarch64 => .loongarch, @@ -1493,12 +1485,13 @@ pub const Cpu = struct { .sh, .sheb => .sh, .sparc, .sparc64 => .sparc, .spirv32, .spirv64 => .spirv, + .spork8 => .spork8, .ve => .ve, .wasm32, .wasm64 => .wasm, .x86_16, .x86, .x86_64 => .x86, .xcore => .xcore, .xtensa, .xtensaeb => .xtensa, - .spork8 => .spork8, + .z80, .ez80 => .z80, }; } @@ -1695,6 +1688,13 @@ pub const Cpu = struct { }; } + pub inline fn isZ80(arch: Arch) bool { + return switch (arch) { + .z80, .ez80 => true, + else => false, + }; + } + pub fn parseCpuModel(arch: Arch, cpu_name: []const u8) ?*const Cpu.Model { for (arch.allCpuModels()) |cpu| { if (std.mem.eql(u8, cpu_name, cpu.name)) { @@ -1713,8 +1713,8 @@ pub const Cpu = struct { .avr, .bpfel, .csky, + .ez80, .hexagon, - .kalimba, .kvx, .loongarch32, .loongarch64, @@ -1737,7 +1737,7 @@ pub const Cpu = struct { .x86_64, .xcore, .xtensa, - .ez80, + .z80, => .little, .aarch64_be, @@ -2027,12 +2027,16 @@ pub const Cpu = struct { .spirv_mesh, => &.{ .spirv32, .spirv64 }, + .spork8, + => &.{.spork8}, + + .z80_cet, + .z80_tiflags, + => &.{.z80}, + .ez80_cet, .ez80_tiflags, => &.{.ez80}, - - .spork8, - => &.{.spork8}, }; } }; @@ -2057,30 +2061,47 @@ pub const Cpu = struct { /// Clang compatibility is important, consider using `baseline` instead. pub fn generic(arch: Arch) *const Model { return switch (arch) { + .aarch64, .aarch64_be => &aarch64.cpu.armv8a, .alpha => &alpha.cpu.ev4, .amdgcn => &amdgcn.cpu.gfx600, + .arc, .arceb => &arc.cpu.arcv2, .avr => &avr.cpu.avr1, + .bpfel, .bpfeb => &bpf.cpu.v1, + .csky => &csky.cpu.e2, + .hexagon => &hexagon.cpu.hexagonv60, .hppa => &hppa.cpu.ts_1, .hppa64 => &hppa.cpu.pa_8000, .kvx => &kvx.cpu.coolidge_v1, + .lanai => &lanai.cpu.v11, .loongarch32 => &loongarch.cpu.generic_la32, .loongarch64 => &loongarch.cpu.generic_la64, + .m68k => &m68k.cpu.m68000, + .m88k => &m88k.cpu.m88000, + .microblaze, .microblazeel => µblaze.cpu.v2_00, .mips, .mipsel => &mips.cpu.mips32, .mips64, .mips64el => &mips.cpu.mips64, + .msp430 => &msp430.cpu.msp430, .nvptx, .nvptx64 => &nvptx.cpu.sm_20, - .powerpc, .powerpcle => &powerpc.cpu.ppc, + .or1k => &or1k.cpu.orbis32, + .powerpc, .powerpcle => &powerpc.cpu.ppc32, .powerpc64, .powerpc64le => &powerpc.cpu.ppc64, .propeller => &propeller.cpu.p1, - .riscv32, .riscv32be => &riscv.cpu.generic_rv32, - .riscv64, .riscv64be => &riscv.cpu.generic_rv64, + .riscv32, .riscv32be => &riscv.cpu.rv32i, + .riscv64, .riscv64be => &riscv.cpu.rv64i, + .s390x => &s390x.cpu.arch8, + .sh, .sheb => &sh.cpu.sh1, .sparc => &sparc.cpu.v7, .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up. + .spirv32, .spirv64 => &spirv.cpu.v1_0, .ve => &ve.cpu.ve10, .wasm32, .wasm64 => &wasm.cpu.mvp, .x86_16 => &x86.cpu.i86, .x86 => &x86.cpu.i386, .x86_64 => &x86.cpu.x86_64, .xcore => &xcore.cpu.xs1b, + .xtensa, .xtensaeb => &xtensa.cpu.xtensa, + .z80 => &z80.cpu.z80, + .ez80 => &z80.cpu.ez80, inline else => |a| &@field(Target, @tagName(a.family())).cpu.generic, }; } @@ -2101,6 +2122,7 @@ pub const Cpu = struct { .@"3ds" => &arm.cpu.mpcore, .vita => &arm.cpu.kermit, .gba => &arm.cpu.arm7tdmi, + .@"switch" => &arm.cpu.cortex_a57, else => &arm.cpu.baseline, }, .thumb => switch (os.tag) { @@ -2110,23 +2132,24 @@ pub const Cpu = struct { }, .armeb, .thumbeb => &arm.cpu.baseline, .aarch64 => switch (os.tag) { - .haiku => &aarch64.cpu.cortex_a55, + .haiku => &aarch64.cpu.armv8a, .driverkit, .maccatalyst, .macos => &aarch64.cpu.apple_m1, - .ios, .tvos => &aarch64.cpu.apple_a7, + .ios => &aarch64.cpu.apple_a10, + .tvos => &aarch64.cpu.apple_a7, .visionos => &aarch64.cpu.apple_m2, - .watchos => &aarch64.cpu.apple_s4, + .watchos => &aarch64.cpu.apple_s6, .@"switch" => &aarch64.cpu.cortex_a57, else => generic(arch), }, .avr => &avr.cpu.avr2, .bpfel, .bpfeb => &bpf.cpu.v3, - .csky => &csky.cpu.ck810, // gcc/clang do not have a generic csky model. - .hexagon => &hexagon.cpu.hexagonv68, // gcc/clang do not have a generic hexagon model. + .csky => &csky.cpu.ck810, + .hexagon => &hexagon.cpu.hexagonv68, .hppa => &hppa.cpu.pa_7000, - .lanai => &lanai.cpu.v11, // clang does not have a generic lanai model. .loongarch32 => &loongarch.cpu.la32v1_0, .loongarch64 => &loongarch.cpu.la64v1_0, - .m68k => &m68k.cpu.M68030, + .m68k => &m68k.cpu.m68030, + .microblaze, .microblazeel => µblaze.cpu.v7_20, .mips => &mips.cpu.mips32r2, .mipsel => switch (os.tag) { .psx => &mips.cpu.r3000a, @@ -2138,8 +2161,8 @@ pub const Cpu = struct { else => &mips.cpu.mips64r2, }, .mips64el => &mips.cpu.mips64r2, - .msp430 => &msp430.cpu.msp430, .nvptx, .nvptx64 => &nvptx.cpu.sm_52, + .or1k => &or1k.cpu.mor1kx, .powerpc => switch (os.tag) { .openbsd, .wiiu => &powerpc.cpu.@"750", else => generic(arch), @@ -2151,18 +2174,32 @@ pub const Cpu = struct { else => generic(arch), }, .powerpc64le => &powerpc.cpu.ppc64le, - .riscv32, .riscv32be => &riscv.cpu.baseline_rv32, - .riscv64, .riscv64be => &riscv.cpu.baseline_rv64, + .riscv32, .riscv32be => &riscv.cpu.rv32gc, + .riscv64, .riscv64be => &riscv.cpu.rv64gc, .s390x => &s390x.cpu.arch11, + .sh, .sheb => switch (os.tag) { + .netbsd => &sh.cpu.sh3, + else => &sh.cpu.sh4, + }, .sparc => switch (os.tag) { .linux => &sparc.cpu.v9, // glibc does not work with 'plain' v8. else => &sparc.cpu.v8, }, .sparc64 => &sparc.cpu.ultrasparc, + .spirv32 => switch (os.tag) { + .opencl => &spirv.cpu.opencl_v2_1, + .opengl => &spirv.cpu.opengl_v4_6, + .vulkan => &spirv.cpu.vulkan_v1_0, + else => generic(arch), + }, + .spirv64 => switch (os.tag) { + .opencl => &spirv.cpu.opencl_v2_1, + .vulkan => &spirv.cpu.vulkan_v1_0, + else => generic(arch), + }, .x86 => &x86.cpu.pentium4, .x86_64 => switch (os.tag) { - .driverkit, .maccatalyst => &x86.cpu.nehalem, - .macos => &x86.cpu.core2, + .driverkit, .maccatalyst, .macos => &x86.cpu.nehalem, .ps4 => &x86.cpu.btver2, .ps5 => &x86.cpu.znver2, else => generic(arch), @@ -2335,8 +2372,6 @@ pub fn requiresLibC(target: *const Target) bool { .gba, .psp, .vita, - .mesa3d, - .amdpal, .hurd, .wasi, .uefi, @@ -2512,9 +2547,7 @@ pub const DynamicLinker = struct { .wasi, .amdhsa, - .amdpal, .cuda, - .mesa3d, .nvcl, .opencl, .opengl, @@ -2959,9 +2992,7 @@ pub const DynamicLinker = struct { .wasi, .amdhsa, - .amdpal, .cuda, - .mesa3d, .nvcl, .opencl, .opengl, @@ -2998,8 +3029,9 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 { return switch (cpu_arch) { .avr, .msp430, - .x86_16, .spork8, + .x86_16, + .z80, => 16, .ez80, @@ -3012,7 +3044,6 @@ pub fn ptrBitWidth_arch_abi(cpu_arch: Cpu.Arch, abi: Abi) u16 { .csky, .hexagon, .hppa, - .kalimba, .lanai, .loongarch32, .m68k, @@ -3076,6 +3107,7 @@ pub fn stackAlignment(target: *const Target) u16 { switch (target.cpu.arch) { .avr, .ez80, + .z80, => return 1, .m68k => if (target.os.tag != .netbsd) return 2, @@ -3178,7 +3210,6 @@ pub fn cCharSignedness(target: *const Target) ?std.builtin.Signedness { .arc, .arceb, .csky, - .ez80, .hexagon, .msp430, .powerpc, @@ -3272,6 +3303,12 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 { .long, .ulong, .float => 32, .double, .longdouble, .longlong, .ulonglong => 64, }, + .z80 => switch (c_type) { + .char => 8, + .short, .ushort, .int, .uint => 16, + .long, .ulong, .float, .double => 32, + .longlong, .ulonglong, .longdouble => 64, + }, .ez80 => switch (c_type) { .char => 8, .short, .ushort => 16, @@ -3464,7 +3501,7 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 { }, }, - .cuda, .amdhsa, .amdpal, .mesa3d, .nvcl, .opencl, .vulkan => switch (c_type) { + .cuda, .amdhsa, .nvcl, .opencl, .vulkan => switch (c_type) { .char => 8, .short, .ushort => 16, .int, .uint, .float => 32, @@ -3482,8 +3519,12 @@ pub fn cTypeBitSize(target: *const Target, c_type: CType) ?u16 { .char => 8, .short, .ushort => 16, .int, .uint, .float => 32, - .long, .ulong, .longlong, .ulonglong, .double => 64, - .longdouble => 128, + .long, .ulong => target.ptrBitWidth(), + .longlong, .ulonglong, .double => 64, + .longdouble => switch (target.cpu.arch) { + .aarch64 => 128, + else => 64, + }, }, .psx, .ps3, .psp, .vita => switch (c_type) { @@ -3511,6 +3552,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) ?u16 { .avr, .ez80, .spork8, + .z80, => return 1, .x86 => switch (target.os.tag) { .windows, .uefi => switch (c_type) { @@ -3548,7 +3590,6 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) ?u16 { .arc, .arceb, .csky, - .kalimba, .microblaze, .microblazeel, .or1k, @@ -3610,6 +3651,7 @@ pub fn cTypeAlignment(target: *const Target, c_type: CType) ?u16 { .avr, .ez80, .spork8, + .z80, => unreachable, // Handled above. }), ); @@ -3620,6 +3662,7 @@ pub fn cMaxIntAlignment(target: *const Target) u16 { .avr, .ez80, .spork8, + .z80, => 1, .msp430, @@ -3629,7 +3672,6 @@ pub fn cMaxIntAlignment(target: *const Target) u16 { .arc, .arceb, .csky, - .kalimba, .microblaze, .microblazeel, .or1k, @@ -3742,7 +3784,6 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention .hexagon => .{ .hexagon_sysv = .{} }, .hppa => .{ .hppa_elf = .{} }, .hppa64 => .{ .hppa64_elf = .{} }, - .kalimba => null, .kvx => switch (target.abi) { .ilp32 => .{ .kvx_ilp32 = .{} }, else => .{ .kvx_lp64 = .{} }, @@ -3770,8 +3811,9 @@ pub fn cCallingConvention(target: *const Target) ?std.builtin.CallingConvention .amdgcn => .{ .amdgcn_device = .{} }, .nvptx, .nvptx64 => .nvptx_device, .spirv32, .spirv64 => .spirv_device, - .ez80 => .ez80_cet, .spork8 => .spork8, + .z80 => .z80_cet, + .ez80 => .ez80_cet, }; } diff --git a/lib/std/Target/Query.zig b/lib/std/Target/Query.zig index bace539353..48c215dc0e 100644 --- a/lib/std/Target/Query.zig +++ b/lib/std/Target/Query.zig @@ -669,7 +669,7 @@ test parse { { const query = try Query.parse(.{ .arch_os_abi = "aarch64-linux.3.10...4.4.1-gnu.2.27", - .cpu_features = "generic+v8a", + .cpu_features = "armv8a", }); const target = try std.zig.system.resolveTargetQuery(io, query); diff --git a/lib/std/Target/aarch64.zig b/lib/std/Target/aarch64.zig index 6cf169bd76..a872033e96 100644 --- a/lib/std/Target/aarch64.zig +++ b/lib/std/Target/aarch64.zig @@ -5,11 +5,9 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { - a320, addr_lsl_slow_14, aes, aggressive_fma, - aggressive_interleaving, align_cmp_csel_pairs, alternate_sextload_cvt_f32_pattern, altnzcv, @@ -18,22 +16,12 @@ pub const Feature = enum { amvs, arith_bcc_fusion, arith_cbz_fusion, - ascend_store_address, avoid_ldapur, balance_fp_ops, bf16, brbe, bti, btie, - call_saved_x10, - call_saved_x11, - call_saved_x12, - call_saved_x13, - call_saved_x14, - call_saved_x15, - call_saved_x18, - call_saved_x8, - call_saved_x9, ccdp, ccidx, ccpp, @@ -48,22 +36,14 @@ pub const Feature = enum { crypto, cssc, d128, - disable_distinct_predicate_dst_reg, disable_fast_inc_vl, - disable_latency_sched_heuristic, - disable_ldp, - disable_maximize_scalable_bandwidth, - disable_stp, disable_unpredicated_ld_st_lower, dit, dotprod, ecv, el2vmsa, el3, - enable_select_opt, ete, - execute_only, - exynos_cheap_as_move, f16f32dot, f16f32mm, f16mm, @@ -75,10 +55,7 @@ pub const Feature = enum { fast_ld1_single, fgt, fix_cortex_a53_835769, - fixed_load_latency_4, flagm, - fmv, - force_32bit_jump_tables, fp16fml, fp8, fp8dot2, @@ -88,7 +65,6 @@ pub const Feature = enum { fpac, fprcvt, fptoint, - fujitsu_monaka, fullfp16, fuse_address, fuse_addsub_2reg_const1, @@ -102,9 +78,6 @@ pub const Feature = enum { fuse_literals, gcie, gcs, - harden_sls_blr, - harden_sls_nocomdat, - harden_sls_retbr, has_limited_64bit_vector_mul_bandwidth, hbc, hinte, @@ -121,7 +94,6 @@ pub const Feature = enum { lsfe, lsui, lut, - max_interleave_factor_4, mec, mops, mops_go, @@ -130,16 +102,11 @@ pub const Feature = enum { mtetc, neon, nmi, - no_bti_at_return_twice, - no_lfi_loads, - no_lfi_stores, - no_neg_immediates, no_sve_fp_ld1r, + no_unaligned_access, no_zcz_fpr64, nv, occmo, - olympus, - outline_atomics, pan, pan_rwv, pauth, @@ -157,31 +124,6 @@ pub const Feature = enum { rcpc3, rcpc_immo, rdm, - reserve_lr_for_ra, - reserve_x1, - reserve_x10, - reserve_x11, - reserve_x12, - reserve_x13, - reserve_x14, - reserve_x15, - reserve_x18, - reserve_x2, - reserve_x20, - reserve_x21, - reserve_x22, - reserve_x23, - reserve_x24, - reserve_x25, - reserve_x26, - reserve_x27, - reserve_x28, - reserve_x3, - reserve_x4, - reserve_x5, - reserve_x6, - reserve_x7, - reserve_x9, rme, sb, sel2, @@ -217,9 +159,7 @@ pub const Feature = enum { ssve_fp8dot2, ssve_fp8dot4, ssve_fp8fma, - store_pair_suppress, stp_aligned_only, - strict_align, sve, sve2, sve2_aes, @@ -238,23 +178,14 @@ pub const Feature = enum { sve_f16f32mm, sve_sha3, sve_sm4, - tagged_globals, tev, the, tlb_rmi, tlbid, tlbiw, - tpidr_el1, - tpidr_el2, - tpidr_el3, - tpidrro_el0, tracev8_4, trbe, uaops, - use_experimental_zeroing_pseudos, - use_fixed_over_scalable_if_equal_cost, - use_postra_scheduler, - use_reciprocal_square_root, use_wzr_to_vec_move, v8_1a, v8_2a, @@ -299,18 +230,6 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; - result[@backingInt(Feature.a320)] = .{ - .llvm_name = "a320", - .description = "Cortex-A320 ARM processors", - .dependencies = featureSet(&[_]Feature{ - .aggressive_interleaving, - .fuse_adrp_add, - .fuse_aes, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, - .use_wzr_to_vec_move, - }), - }; result[@backingInt(Feature.addr_lsl_slow_14)] = .{ .llvm_name = "addr-lsl-slow-14", .description = "Address operands with shift amount of 1 or 4 are slow", @@ -328,11 +247,6 @@ pub const all_features = blk: { .description = "Enable Aggressive FMA for floating-point.", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.aggressive_interleaving)] = .{ - .llvm_name = "aggressive-interleaving", - .description = "Make use of aggressive interleaving during vectorization", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.align_cmp_csel_pairs)] = .{ .llvm_name = "align-cmp-csel-pairs", .description = "Align certain CMP/FCMP and CSEL/FCSEL instruction pairs", @@ -377,11 +291,6 @@ pub const all_features = blk: { .description = "CPU fuses arithmetic + cbz/cbnz operations", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.ascend_store_address)] = .{ - .llvm_name = "ascend-store-address", - .description = "Schedule vector stores by ascending address", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.avoid_ldapur)] = .{ .llvm_name = "avoid-ldapur", .description = "Prefer add+ldapr to offset ldapur", @@ -414,51 +323,6 @@ pub const all_features = blk: { .description = "Enable Enhanced Branch Target Identification extension", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.call_saved_x10)] = .{ - .llvm_name = "call-saved-x10", - .description = "Make X10 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.call_saved_x11)] = .{ - .llvm_name = "call-saved-x11", - .description = "Make X11 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.call_saved_x12)] = .{ - .llvm_name = "call-saved-x12", - .description = "Make X12 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.call_saved_x13)] = .{ - .llvm_name = "call-saved-x13", - .description = "Make X13 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.call_saved_x14)] = .{ - .llvm_name = "call-saved-x14", - .description = "Make X14 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.call_saved_x15)] = .{ - .llvm_name = "call-saved-x15", - .description = "Make X15 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.call_saved_x18)] = .{ - .llvm_name = "call-saved-x18", - .description = "Make X18 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.call_saved_x8)] = .{ - .llvm_name = "call-saved-x8", - .description = "Make X8 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.call_saved_x9)] = .{ - .llvm_name = "call-saved-x9", - .description = "Make X9 callee saved.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.ccdp)] = .{ .llvm_name = "ccdp", .description = "Enable Armv8.5-A Cache Clean to Point of Deep Persistence", @@ -538,36 +402,11 @@ pub const all_features = blk: { .lse128, }), }; - result[@backingInt(Feature.disable_distinct_predicate_dst_reg)] = .{ - .llvm_name = "disable-distinct-predicate-dst-reg", - .description = "Disabling selecting a distinct predicate register for the destination operand of instructions that take a governing predicate", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.disable_fast_inc_vl)] = .{ .llvm_name = "disable-fast-inc-vl", .description = "Do not prefer INC/DEC, ALL, { 1, 2, 4 } over ADDVL", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.disable_latency_sched_heuristic)] = .{ - .llvm_name = "disable-latency-sched-heuristic", - .description = "Disable latency scheduling heuristic", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.disable_ldp)] = .{ - .llvm_name = "disable-ldp", - .description = "Prefer not to emit ldp", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.disable_maximize_scalable_bandwidth)] = .{ - .llvm_name = "disable-maximize-scalable-bandwidth", - .description = "Determine the maximum scalable vector length for a loop by the largest scalar type rather than the smallest", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.disable_stp)] = .{ - .llvm_name = "disable-stp", - .description = "Prefer not to emit stp", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.disable_unpredicated_ld_st_lower)] = .{ .llvm_name = "disable-unpredicated-ld-st-lower", .description = "Disable lowering unpredicated loads/stores as LDR/STR", @@ -600,11 +439,6 @@ pub const all_features = blk: { .description = "Enable Exception Level 3", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.enable_select_opt)] = .{ - .llvm_name = "enable-select-opt", - .description = "Enable the select optimize pass for select loop heuristics", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.ete)] = .{ .llvm_name = "ete", .description = "Enable Embedded Trace Extension", @@ -612,16 +446,6 @@ pub const all_features = blk: { .trbe, }), }; - result[@backingInt(Feature.execute_only)] = .{ - .llvm_name = "execute-only", - .description = "Enable the generation of execute only code.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.exynos_cheap_as_move)] = .{ - .llvm_name = "exynos-cheap-as-move", - .description = "Use Exynos specific handling of cheap instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.f16f32dot)] = .{ .llvm_name = "f16f32dot", .description = "Enable Armv9.7-A Advanced SIMD half-precision dot product accumulate to single-precision", @@ -696,26 +520,11 @@ pub const all_features = blk: { .description = "Mitigate Cortex-A53 Erratum 835769", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.fixed_load_latency_4)] = .{ - .llvm_name = "fixed-load-latency-4", - .description = "Use a fixed latency of 4 for loads instead of querying the scheduling model", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.flagm)] = .{ .llvm_name = "flagm", .description = "Enable Armv8.4-A Flag Manipulation instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.fmv)] = .{ - .llvm_name = "fmv", - .description = "Enable Function Multi Versioning support.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.force_32bit_jump_tables)] = .{ - .llvm_name = "force-32bit-jump-tables", - .description = "Force jump table entries to be 32-bits wide except at MinSize", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.fp16fml)] = .{ .llvm_name = "fp16fml", .description = "Enable FP16 FML instructions", @@ -776,16 +585,6 @@ pub const all_features = blk: { .fp_armv8, }), }; - result[@backingInt(Feature.fujitsu_monaka)] = .{ - .llvm_name = "fujitsu-monaka", - .description = "Fujitsu FUJITSU-MONAKA processors", - .dependencies = featureSet(&[_]Feature{ - .arith_bcc_fusion, - .enable_select_opt, - .predictable_select_expensive, - .use_postra_scheduler, - }), - }; result[@backingInt(Feature.fullfp16)] = .{ .llvm_name = "fullfp16", .description = "Enable half-precision floating-point data processing", @@ -855,21 +654,6 @@ pub const all_features = blk: { .chk, }), }; - result[@backingInt(Feature.harden_sls_blr)] = .{ - .llvm_name = "harden-sls-blr", - .description = "Harden against straight line speculation across BLR instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.harden_sls_nocomdat)] = .{ - .llvm_name = "harden-sls-nocomdat", - .description = "Generate thunk code for SLS mitigation in the normal text section", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.harden_sls_retbr)] = .{ - .llvm_name = "harden-sls-retbr", - .description = "Harden against straight line speculation across RET and BR instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.has_limited_64bit_vector_mul_bandwidth)] = .{ .llvm_name = "has-limited-64bit-vector-mul-bandwidth", .description = "Has limited 64bit vector multiply bandwidth compared to scalar multiply", @@ -962,11 +746,6 @@ pub const all_features = blk: { .neon, }), }; - result[@backingInt(Feature.max_interleave_factor_4)] = .{ - .llvm_name = "max-interleave-factor-4", - .description = "Set the MaxInterleaveFactor to 4 (from the default 2)", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.mec)] = .{ .llvm_name = "mec", .description = "Enable Memory Encryption Contexts Extension", @@ -1016,31 +795,16 @@ pub const all_features = blk: { .description = "Enable Armv8.8-A Non-maskable Interrupts", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.no_bti_at_return_twice)] = .{ - .llvm_name = "no-bti-at-return-twice", - .description = "Don't place a BTI instruction after a return-twice", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.no_lfi_loads)] = .{ - .llvm_name = "no-lfi-loads", - .description = "Disable LFI sandboxing for load instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.no_lfi_stores)] = .{ - .llvm_name = "no-lfi-stores", - .description = "Disable LFI sandboxing for store instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.no_neg_immediates)] = .{ - .llvm_name = "no-neg-immediates", - .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.no_sve_fp_ld1r)] = .{ .llvm_name = "no-sve-fp-ld1r", .description = "Avoid using LD1RX instructions for FP", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.no_unaligned_access)] = .{ + .llvm_name = "strict-align", + .description = "Disallow all unaligned memory access", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.no_zcz_fpr64)] = .{ .llvm_name = "no-zcz-fpr64", .description = "Has no zero-cycle zeroing instructions for FPR64 registers", @@ -1056,26 +820,6 @@ pub const all_features = blk: { .description = "Enable Armv9.6-A Outer cacheable cache maintenance operations", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.olympus)] = .{ - .llvm_name = "olympus", - .description = "NVIDIA Olympus processors", - .dependencies = featureSet(&[_]Feature{ - .alu_lsl_fast, - .cmp_bcc_fusion, - .enable_select_opt, - .fuse_adrp_add, - .fuse_aes, - .max_interleave_factor_4, - .predictable_select_expensive, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, - }), - }; - result[@backingInt(Feature.outline_atomics)] = .{ - .llvm_name = "outline-atomics", - .description = "Enable out of line atomics to support LSE instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.pan)] = .{ .llvm_name = "pan", .description = "Enable Armv8.1-A Privileged Access-Never extension", @@ -1171,131 +915,6 @@ pub const all_features = blk: { .neon, }), }; - result[@backingInt(Feature.reserve_lr_for_ra)] = .{ - .llvm_name = "reserve-lr-for-ra", - .description = "Reserve LR for call use only", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x1)] = .{ - .llvm_name = "reserve-x1", - .description = "Reserve X1, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x10)] = .{ - .llvm_name = "reserve-x10", - .description = "Reserve X10, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x11)] = .{ - .llvm_name = "reserve-x11", - .description = "Reserve X11, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x12)] = .{ - .llvm_name = "reserve-x12", - .description = "Reserve X12, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x13)] = .{ - .llvm_name = "reserve-x13", - .description = "Reserve X13, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x14)] = .{ - .llvm_name = "reserve-x14", - .description = "Reserve X14, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x15)] = .{ - .llvm_name = "reserve-x15", - .description = "Reserve X15, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x18)] = .{ - .llvm_name = "reserve-x18", - .description = "Reserve X18, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x2)] = .{ - .llvm_name = "reserve-x2", - .description = "Reserve X2, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x20)] = .{ - .llvm_name = "reserve-x20", - .description = "Reserve X20, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x21)] = .{ - .llvm_name = "reserve-x21", - .description = "Reserve X21, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x22)] = .{ - .llvm_name = "reserve-x22", - .description = "Reserve X22, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x23)] = .{ - .llvm_name = "reserve-x23", - .description = "Reserve X23, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x24)] = .{ - .llvm_name = "reserve-x24", - .description = "Reserve X24, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x25)] = .{ - .llvm_name = "reserve-x25", - .description = "Reserve X25, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x26)] = .{ - .llvm_name = "reserve-x26", - .description = "Reserve X26, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x27)] = .{ - .llvm_name = "reserve-x27", - .description = "Reserve X27, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x28)] = .{ - .llvm_name = "reserve-x28", - .description = "Reserve X28, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x3)] = .{ - .llvm_name = "reserve-x3", - .description = "Reserve X3, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x4)] = .{ - .llvm_name = "reserve-x4", - .description = "Reserve X4, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x5)] = .{ - .llvm_name = "reserve-x5", - .description = "Reserve X5, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x6)] = .{ - .llvm_name = "reserve-x6", - .description = "Reserve X6, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x7)] = .{ - .llvm_name = "reserve-x7", - .description = "Reserve X7, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x9)] = .{ - .llvm_name = "reserve-x9", - .description = "Reserve X9, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.rme)] = .{ .llvm_name = "rme", .description = "Enable Realm Management Extension", @@ -1531,21 +1150,11 @@ pub const all_features = blk: { .sme2, }), }; - result[@backingInt(Feature.store_pair_suppress)] = .{ - .llvm_name = "store-pair-suppress", - .description = "Enable Store Pair Suppression heuristics", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.stp_aligned_only)] = .{ .llvm_name = "stp-aligned-only", .description = "In order to emit stp, first check if the store will be aligned to 2 * element_size", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.strict_align)] = .{ - .llvm_name = "strict-align", - .description = "Disallow all unaligned memory access", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.sve)] = .{ .llvm_name = "sve", .description = "Enable Scalable Vector Extension (SVE) instructions", @@ -1668,11 +1277,6 @@ pub const all_features = blk: { .sm4, }), }; - result[@backingInt(Feature.tagged_globals)] = .{ - .llvm_name = "tagged-globals", - .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.tev)] = .{ .llvm_name = "tev", .description = "Enable TIndex Exception-like Vector instructions", @@ -1698,26 +1302,6 @@ pub const all_features = blk: { .description = "Enable Armv9.5-A TLBI VMALL for Dirty State", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.tpidr_el1)] = .{ - .llvm_name = "tpidr-el1", - .description = "Permit use of TPIDR_EL1 for the TLS base", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.tpidr_el2)] = .{ - .llvm_name = "tpidr-el2", - .description = "Permit use of TPIDR_EL2 for the TLS base", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.tpidr_el3)] = .{ - .llvm_name = "tpidr-el3", - .description = "Permit use of TPIDR_EL3 for the TLS base", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.tpidrro_el0)] = .{ - .llvm_name = "tpidrro-el0", - .description = "Permit use of TPIDRRO_EL0 for the TLS base", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.tracev8_4)] = .{ .llvm_name = "tracev8.4", .description = "Enable Armv8.4-A Trace extension", @@ -1733,26 +1317,6 @@ pub const all_features = blk: { .description = "Enable Armv8.2-A UAO PState", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.use_experimental_zeroing_pseudos)] = .{ - .llvm_name = "use-experimental-zeroing-pseudos", - .description = "Hint to the compiler that the MOVPRFX instruction is merged with destructive operations", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.use_fixed_over_scalable_if_equal_cost)] = .{ - .llvm_name = "use-fixed-over-scalable-if-equal-cost", - .description = "Prefer fixed width loop vectorization over scalable if the cost-model assigns equal costs", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.use_postra_scheduler)] = .{ - .llvm_name = "use-postra-scheduler", - .description = "Schedule again after register allocation", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.use_reciprocal_square_root)] = .{ - .llvm_name = "use-reciprocal-square-root", - .description = "Use the reciprocal square root approximation", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.use_wzr_to_vec_move)] = .{ .llvm_name = "use-wzr-to-vec-move", .description = "Move from WZR to insert 0 into vector registers", @@ -2064,13 +1628,10 @@ pub const cpu = struct { .arith_bcc_fusion, .complxnum, .disable_unpredicated_ld_st_lower, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .sha2, - .store_pair_suppress, .sve, - .use_postra_scheduler, .v8_2a, }), }; @@ -2089,13 +1650,10 @@ pub const cpu = struct { .fuse_aes, .fuse_literals, .ldp_aligned_only, - .max_interleave_factor_4, .perfmon, .rand, .sha3, - .store_pair_suppress, .stp_aligned_only, - .use_postra_scheduler, .v8_6a, }), }; @@ -2115,15 +1673,12 @@ pub const cpu = struct { .fuse_aes, .fuse_literals, .ldp_aligned_only, - .max_interleave_factor_4, .mte, .perfmon, .rand, .sha3, .sm4, - .store_pair_suppress, .stp_aligned_only, - .use_postra_scheduler, .v8_6a, }), }; @@ -2137,23 +1692,19 @@ pub const cpu = struct { .arith_bcc_fusion, .cmp_bcc_fusion, .cssc, - .enable_select_opt, .fullfp16, .fuse_address, .fuse_adrp_add, .fuse_aes, .fuse_literals, .ldp_aligned_only, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .rand, .sha3, .sm4, - .store_pair_suppress, .stp_aligned_only, - .use_postra_scheduler, .v8_7a, }), }; @@ -2166,7 +1717,6 @@ pub const cpu = struct { .arith_bcc_fusion, .cmp_bcc_fusion, .cssc, - .enable_select_opt, .faminmax, .fp16fml, .fp8fma, @@ -2175,17 +1725,14 @@ pub const cpu = struct { .fuse_aes, .fuse_literals, .lut, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .rand, - .store_pair_suppress, .sve_aes, .sve_b16b16, .sve_sha3, .sve_sm4, - .use_postra_scheduler, .v9_2a, }), }; @@ -2198,7 +1745,6 @@ pub const cpu = struct { .arith_bcc_fusion, .arith_cbz_fusion, .crc, - .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .lor, @@ -2207,7 +1753,6 @@ pub const cpu = struct { .perfmon, .rdm, .sha2, - .store_pair_suppress, .v8a, .vh, .zcm_fpr128, @@ -2225,14 +1770,12 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fullfp16, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha2, - .store_pair_suppress, .v8_2a, .zcm_fpr128, .zcm_gpr64, @@ -2249,14 +1792,12 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fullfp16, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha2, - .store_pair_suppress, .v8_3a, .zcm_fpr128, .zcm_gpr64, @@ -2273,14 +1814,12 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fp16fml, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_4a, .zcm_fpr128, .zcm_gpr64, @@ -2301,7 +1840,6 @@ pub const cpu = struct { .arith_bcc_fusion, .arith_cbz_fusion, .ccdp, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fptoint, @@ -2311,7 +1849,6 @@ pub const cpu = struct { .fuse_crypto_eor, .fuse_csel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .predres, @@ -2319,7 +1856,6 @@ pub const cpu = struct { .sha3, .specrestrict, .ssbs, - .store_pair_suppress, .v8_4a, .zcm_fpr128, .zcm_gpr64, @@ -2337,7 +1873,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2348,11 +1883,9 @@ pub const cpu = struct { .fuse_crypto_eor, .fuse_csel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_6a, .zcm_fpr128, .zcm_gpr64, @@ -2370,7 +1903,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2382,11 +1914,9 @@ pub const cpu = struct { .fuse_csel, .fuse_fcsel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_6a, .zcm_fpr128, .zcm_gpr64, @@ -2404,7 +1934,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2416,11 +1945,9 @@ pub const cpu = struct { .fuse_csel, .fuse_fcsel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_6a, .zcm_fpr128, .zcm_gpr64, @@ -2438,7 +1965,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2450,7 +1976,6 @@ pub const cpu = struct { .fuse_csel, .fuse_fcsel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, @@ -2475,7 +2000,6 @@ pub const cpu = struct { .arith_bcc_fusion, .arith_cbz_fusion, .cssc, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2488,7 +2012,6 @@ pub const cpu = struct { .fuse_fcsel, .fuse_literals, .hbc, - .max_interleave_factor_4, .mte, .no_zcz_fpr64, .perfmon, @@ -2515,13 +2038,11 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha2, - .store_pair_suppress, .v8a, .zcm_fpr128, .zcm_gpr64, @@ -2539,13 +2060,11 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha2, - .store_pair_suppress, .v8a, .zcm_fpr128, .zcm_gpr64, @@ -2563,13 +2082,11 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha2, - .store_pair_suppress, .v8a, .zcm_fpr128, .zcm_gpr64, @@ -2591,7 +2108,6 @@ pub const cpu = struct { .arith_bcc_fusion, .arith_cbz_fusion, .ccdp, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fptoint, @@ -2601,7 +2117,6 @@ pub const cpu = struct { .fuse_crypto_eor, .fuse_csel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .predres, @@ -2609,7 +2124,6 @@ pub const cpu = struct { .sha3, .specrestrict, .ssbs, - .store_pair_suppress, .v8_4a, .zcm_fpr128, .zcm_gpr64, @@ -2627,7 +2141,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2638,11 +2151,9 @@ pub const cpu = struct { .fuse_crypto_eor, .fuse_csel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_6a, .zcm_fpr128, .zcm_gpr64, @@ -2660,7 +2171,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2672,11 +2182,9 @@ pub const cpu = struct { .fuse_csel, .fuse_fcsel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_6a, .zcm_fpr128, .zcm_gpr64, @@ -2694,7 +2202,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2706,7 +2213,6 @@ pub const cpu = struct { .fuse_csel, .fuse_fcsel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, @@ -2731,7 +2237,6 @@ pub const cpu = struct { .arith_bcc_fusion, .arith_cbz_fusion, .cssc, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2744,7 +2249,6 @@ pub const cpu = struct { .fuse_fcsel, .fuse_literals, .hbc, - .max_interleave_factor_4, .mte, .no_zcz_fpr64, .perfmon, @@ -2772,7 +2276,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2784,11 +2287,9 @@ pub const cpu = struct { .fuse_csel, .fuse_fcsel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_6a, .zcm_fpr128, .zcm_gpr64, @@ -2805,14 +2306,12 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fullfp16, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha2, - .store_pair_suppress, .v8_3a, .zcm_fpr128, .zcm_gpr64, @@ -2829,14 +2328,12 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fullfp16, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha2, - .store_pair_suppress, .v8_3a, .zcm_fpr128, .zcm_gpr64, @@ -2853,14 +2350,12 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fp16fml, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_4a, .zcm_fpr128, .zcm_gpr64, @@ -2877,14 +2372,12 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fp16fml, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_4a, .zcm_fpr128, .zcm_gpr64, @@ -2901,14 +2394,12 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fp16fml, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_4a, .zcm_fpr128, .zcm_gpr64, @@ -2926,7 +2417,6 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fast_ld1_single, .fp16fml, .fpac, @@ -2938,11 +2428,9 @@ pub const cpu = struct { .fuse_csel, .fuse_fcsel, .fuse_literals, - .max_interleave_factor_4, .no_zcz_fpr64, .perfmon, .sha3, - .store_pair_suppress, .v8_6a, .zcm_fpr128, .zcm_gpr64, @@ -2958,7 +2446,6 @@ pub const cpu = struct { .alu_lsl_fast, .avoid_ldapur, .brbe, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -2974,11 +2461,142 @@ pub const cpu = struct { .rand, .spe, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9_2a, }), }; + pub const armv8_1a: CpuModel = .{ + .name = "armv8_1a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_1a, + }), + }; + pub const armv8_2a: CpuModel = .{ + .name = "armv8_2a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_2a, + }), + }; + pub const armv8_3a: CpuModel = .{ + .name = "armv8_3a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_3a, + }), + }; + pub const armv8_4a: CpuModel = .{ + .name = "armv8_4a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_4a, + }), + }; + pub const armv8_5a: CpuModel = .{ + .name = "armv8_5a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_5a, + }), + }; + pub const armv8_6a: CpuModel = .{ + .name = "armv8_6a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_6a, + }), + }; + pub const armv8_7a: CpuModel = .{ + .name = "armv8_7a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_7a, + }), + }; + pub const armv8_8a: CpuModel = .{ + .name = "armv8_8a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_8a, + }), + }; + pub const armv8_9a: CpuModel = .{ + .name = "armv8_9a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8_9a, + }), + }; + pub const armv8a: CpuModel = .{ + .name = "armv8a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8a, + }), + }; + pub const armv8r: CpuModel = .{ + .name = "armv8r", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v8r, + }), + }; + pub const armv9_1a: CpuModel = .{ + .name = "armv9_1a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v9_1a, + }), + }; + pub const armv9_2a: CpuModel = .{ + .name = "armv9_2a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v9_2a, + }), + }; + pub const armv9_3a: CpuModel = .{ + .name = "armv9_3a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v9_3a, + }), + }; + pub const armv9_4a: CpuModel = .{ + .name = "armv9_4a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v9_4a, + }), + }; + pub const armv9_5a: CpuModel = .{ + .name = "armv9_5a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v9_5a, + }), + }; + pub const armv9_6a: CpuModel = .{ + .name = "armv9_6a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v9_6a, + }), + }; + pub const armv9_7a: CpuModel = .{ + .name = "armv9_7a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v9_7a, + }), + }; + pub const armv9a: CpuModel = .{ + .name = "armv9a", + .llvm_name = "generic", + .features = featureSet(&[_]Feature{ + .v9a, + }), + }; pub const c1_nano: CpuModel = .{ .name = "c1_nano", .llvm_name = "c1-nano", @@ -2996,8 +2614,6 @@ pub const cpu = struct { .sme2, .specres2, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .use_wzr_to_vec_move, .v9_3a, }), @@ -3010,7 +2626,6 @@ pub const cpu = struct { .avoid_ldapur, .chk, .clrbhb, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3026,8 +2641,6 @@ pub const cpu = struct { .spe, .specres2, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9_3a, }), }; @@ -3039,7 +2652,6 @@ pub const cpu = struct { .chk, .clrbhb, .cmp_bcc_fusion, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3055,7 +2667,6 @@ pub const cpu = struct { .spe, .specres2, .sve_bitperm, - .use_postra_scheduler, .v9_3a, }), }; @@ -3067,7 +2678,6 @@ pub const cpu = struct { .avoid_ldapur, .chk, .clrbhb, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3075,7 +2685,6 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -3084,8 +2693,6 @@ pub const cpu = struct { .spe, .specres2, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9_3a, }), }; @@ -3105,7 +2712,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .bf16, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3119,8 +2725,6 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9a, }), }; @@ -3128,12 +2732,14 @@ pub const cpu = struct { .name = "cortex_a320", .llvm_name = "cortex-a320", .features = featureSet(&[_]Feature{ - .a320, .ete, .fp16fml, + .fuse_adrp_add, + .fuse_aes, .mte, .perfmon, .sve_bitperm, + .use_wzr_to_vec_move, .v9_2a, }), }; @@ -3173,8 +2779,6 @@ pub const cpu = struct { .mte, .perfmon, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .use_wzr_to_vec_move, .v9a, }), @@ -3191,8 +2795,6 @@ pub const cpu = struct { .mte, .perfmon, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .use_wzr_to_vec_move, .v9_2a, }), @@ -3209,7 +2811,6 @@ pub const cpu = struct { .mte, .perfmon, .sve_bitperm, - .use_postra_scheduler, .use_wzr_to_vec_move, .v9_2a, }), @@ -3225,7 +2826,6 @@ pub const cpu = struct { .fuse_aes, .perfmon, .sha2, - .use_postra_scheduler, .use_wzr_to_vec_move, .v8a, }), @@ -3243,7 +2843,6 @@ pub const cpu = struct { .perfmon, .rcpc, .sha2, - .use_postra_scheduler, .use_wzr_to_vec_move, .v8_2a, }), @@ -3256,15 +2855,12 @@ pub const cpu = struct { .aes, .balance_fp_ops, .crc, - .enable_select_opt, .fuse_adrp_add, .fuse_aes, .fuse_literals, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .sha2, - .use_postra_scheduler, .v8a, }), }; @@ -3274,7 +2870,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .aes, .dotprod, - .enable_select_opt, .fullfp16, .fuse_address, .fuse_adrp_add, @@ -3294,7 +2889,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .aes, .dotprod, - .enable_select_opt, .fullfp16, .fuse_address, .fuse_adrp_add, @@ -3315,7 +2909,6 @@ pub const cpu = struct { .alu_lsl_fast, .bf16, .cmp_bcc_fusion, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3328,7 +2921,6 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .sve_bitperm, - .use_postra_scheduler, .v9a, }), }; @@ -3339,7 +2931,6 @@ pub const cpu = struct { .alu_lsl_fast, .bf16, .cmp_bcc_fusion, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3353,7 +2944,6 @@ pub const cpu = struct { .predictable_select_expensive, .spe, .sve_bitperm, - .use_postra_scheduler, .v9a, }), }; @@ -3364,7 +2954,6 @@ pub const cpu = struct { .addr_lsl_slow_14, .aes, .crc, - .enable_select_opt, .fuse_adrp_add, .fuse_aes, .fuse_literals, @@ -3380,7 +2969,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .cmp_bcc_fusion, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3393,7 +2981,6 @@ pub const cpu = struct { .predictable_select_expensive, .spe, .sve_bitperm, - .use_postra_scheduler, .v9_2a, }), }; @@ -3403,7 +2990,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .cmp_bcc_fusion, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3416,7 +3002,6 @@ pub const cpu = struct { .predictable_select_expensive, .spe, .sve_bitperm, - .use_postra_scheduler, .v9_2a, }), }; @@ -3426,7 +3011,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .cmp_bcc_fusion, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3439,7 +3023,6 @@ pub const cpu = struct { .predictable_select_expensive, .spe, .sve_bitperm, - .use_postra_scheduler, .v9_2a, }), }; @@ -3450,7 +3033,6 @@ pub const cpu = struct { .addr_lsl_slow_14, .aes, .crc, - .enable_select_opt, .fuse_adrp_add, .fuse_aes, .perfmon, @@ -3466,7 +3048,6 @@ pub const cpu = struct { .addr_lsl_slow_14, .aes, .dotprod, - .enable_select_opt, .fullfp16, .fuse_adrp_add, .fuse_aes, @@ -3485,7 +3066,6 @@ pub const cpu = struct { .aes, .alu_lsl_fast, .dotprod, - .enable_select_opt, .fullfp16, .fuse_adrp_add, .fuse_aes, @@ -3505,7 +3085,6 @@ pub const cpu = struct { .aes, .alu_lsl_fast, .dotprod, - .enable_select_opt, .fullfp16, .fuse_adrp_add, .fuse_aes, @@ -3526,7 +3105,6 @@ pub const cpu = struct { .alu_lsl_fast, .cmp_bcc_fusion, .dotprod, - .enable_select_opt, .fullfp16, .fuse_adrp_add, .fuse_aes, @@ -3547,7 +3125,6 @@ pub const cpu = struct { .alu_lsl_fast, .cmp_bcc_fusion, .dotprod, - .enable_select_opt, .fullfp16, .fuse_adrp_add, .fuse_aes, @@ -3559,7 +3136,6 @@ pub const cpu = struct { .sha2, .spe, .ssbs, - .use_postra_scheduler, .v8_2a, }), }; @@ -3572,7 +3148,6 @@ pub const cpu = struct { .alu_lsl_fast, .cmp_bcc_fusion, .dotprod, - .enable_select_opt, .fullfp16, .fuse_adrp_add, .fuse_aes, @@ -3584,7 +3159,6 @@ pub const cpu = struct { .sha2, .spe, .ssbs, - .use_postra_scheduler, .v8_2a, }), }; @@ -3597,7 +3171,6 @@ pub const cpu = struct { .alu_lsl_fast, .cmp_bcc_fusion, .dotprod, - .enable_select_opt, .flagm, .fullfp16, .fuse_adrp_add, @@ -3611,7 +3184,6 @@ pub const cpu = struct { .sha2, .spe, .ssbs, - .use_postra_scheduler, .v8_2a, }), }; @@ -3623,7 +3195,6 @@ pub const cpu = struct { .fpac, .perfmon, .predres, - .use_postra_scheduler, .v8r, }), }; @@ -3635,7 +3206,6 @@ pub const cpu = struct { .fpac, .perfmon, .predres, - .use_postra_scheduler, .v8r, }), }; @@ -3648,18 +3218,15 @@ pub const cpu = struct { .alu_lsl_fast, .cmp_bcc_fusion, .dotprod, - .enable_select_opt, .fullfp16, .fuse_adrp_add, .fuse_aes, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .rcpc, .sha2, .spe, .ssbs, - .use_postra_scheduler, .v8_2a, }), }; @@ -3672,13 +3239,11 @@ pub const cpu = struct { .alu_lsl_fast, .cmp_bcc_fusion, .dotprod, - .enable_select_opt, .flagm, .fullfp16, .fuse_adrp_add, .fuse_aes, .lse2, - .max_interleave_factor_4, .pauth, .perfmon, .predictable_select_expensive, @@ -3686,7 +3251,6 @@ pub const cpu = struct { .sha2, .spe, .ssbs, - .use_postra_scheduler, .v8_2a, }), }; @@ -3697,20 +3261,16 @@ pub const cpu = struct { .alu_lsl_fast, .bf16, .cmp_bcc_fusion, - .enable_select_opt, .ete, .fp16fml, .fpac, .fuse_adrp_add, .fuse_aes, .i8mm, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9a, }), }; @@ -3721,21 +3281,17 @@ pub const cpu = struct { .alu_lsl_fast, .avoid_ldapur, .bf16, - .enable_select_opt, .ete, .fp16fml, .fpac, .fuse_adrp_add, .fuse_aes, .i8mm, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .spe, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9a, }), }; @@ -3745,7 +3301,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .avoid_ldapur, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3753,14 +3308,11 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .spe, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9_2a, }), }; @@ -3770,7 +3322,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .avoid_ldapur, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3778,14 +3329,11 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .spe, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9_2a, }), }; @@ -3797,13 +3345,11 @@ pub const cpu = struct { .alternate_sextload_cvt_f32_pattern, .arith_bcc_fusion, .arith_cbz_fusion, - .disable_latency_sched_heuristic, .fuse_aes, .fuse_crypto_eor, .no_zcz_fpr64, .perfmon, .sha2, - .store_pair_suppress, .v8a, .zcm_fpr128, .zcm_gpr64, @@ -3815,7 +3361,7 @@ pub const cpu = struct { }; pub const emag: CpuModel = .{ .name = "emag", - .llvm_name = null, + .llvm_name = "generic", .features = featureSet(&[_]Feature{ .crc, .crypto, @@ -3825,34 +3371,27 @@ pub const cpu = struct { }; pub const exynos_m1: CpuModel = .{ .name = "exynos_m1", - .llvm_name = null, + .llvm_name = "generic", .features = featureSet(&[_]Feature{ .crc, .crypto, - .exynos_cheap_as_move, - .force_32bit_jump_tables, .fuse_aes, .perfmon, .slow_misaligned_128store, .slow_paired_128, - .use_postra_scheduler, - .use_reciprocal_square_root, .v8a, }), }; pub const exynos_m2: CpuModel = .{ .name = "exynos_m2", - .llvm_name = null, + .llvm_name = "generic", .features = featureSet(&[_]Feature{ .crc, .crypto, - .exynos_cheap_as_move, - .force_32bit_jump_tables, .fuse_aes, .perfmon, .slow_misaligned_128store, .slow_paired_128, - .use_postra_scheduler, .v8a, }), }; @@ -3863,19 +3402,14 @@ pub const cpu = struct { .aes, .alu_lsl_fast, .crc, - .exynos_cheap_as_move, - .force_32bit_jump_tables, .fuse_address, .fuse_adrp_add, .fuse_aes, .fuse_csel, .fuse_literals, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8a, }), }; @@ -3888,8 +3422,6 @@ pub const cpu = struct { .arith_bcc_fusion, .arith_cbz_fusion, .dotprod, - .exynos_cheap_as_move, - .force_32bit_jump_tables, .fullfp16, .fuse_address, .fuse_adrp_add, @@ -3897,11 +3429,8 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_csel, .fuse_literals, - .max_interleave_factor_4, .perfmon, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8_2a, .zcz_gpr32, .zcz_gpr64, @@ -3916,8 +3445,6 @@ pub const cpu = struct { .arith_bcc_fusion, .arith_cbz_fusion, .dotprod, - .exynos_cheap_as_move, - .force_32bit_jump_tables, .fullfp16, .fuse_address, .fuse_adrp_add, @@ -3925,11 +3452,8 @@ pub const cpu = struct { .fuse_arith_logic, .fuse_csel, .fuse_literals, - .max_interleave_factor_4, .perfmon, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8_2a, .zcz_gpr32, .zcz_gpr64, @@ -3942,14 +3466,11 @@ pub const cpu = struct { .aes, .alu_lsl_fast, .crc, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .rdm, .sha2, .slow_strqro_store, - .store_pair_suppress, - .use_postra_scheduler, .v8a, .zcz_gpr32, .zcz_gpr64, @@ -3959,6 +3480,7 @@ pub const cpu = struct { .name = "fujitsu_monaka", .llvm_name = "fujitsu-monaka", .features = featureSet(&[_]Feature{ + .arith_bcc_fusion, .clrbhb, .ete, .faminmax, @@ -3967,10 +3489,10 @@ pub const cpu = struct { .fp8dot4, .fp8fma, .fpac, - .fujitsu_monaka, .ls64, .lut, .perfmon, + .predictable_select_expensive, .rand, .specres2, .sve_aes, @@ -3986,7 +3508,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .avoid_ldapur, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -3994,7 +3515,6 @@ pub const cpu = struct { .fuse_aes, .fuse_csel, .fuse_cset, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -4003,24 +3523,9 @@ pub const cpu = struct { .sve_bitperm, .sve_sha3, .sve_sm4, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9_2a, }), }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{ - .enable_select_opt, - .ete, - .fixed_load_latency_4, - .fuse_adrp_add, - .fuse_aes, - .neon, - .use_postra_scheduler, - }), - }; pub const grace: CpuModel = .{ .name = "grace", .llvm_name = "grace", @@ -4029,8 +3534,6 @@ pub const cpu = struct { .avoid_ldapur, .bf16, .cmp_bcc_fusion, - .disable_latency_sched_heuristic, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -4039,7 +3542,6 @@ pub const cpu = struct { .fuse_csel, .fuse_cset, .i8mm, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, @@ -4048,8 +3550,6 @@ pub const cpu = struct { .sve_bitperm, .sve_sha3, .sve_sm4, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9a, }), }; @@ -4073,13 +3573,11 @@ pub const cpu = struct { .rcpc3, .rme, .spe, - .store_pair_suppress, .sve2, .sve_aes, .sve_bitperm, .sve_sha3, .sve_sm4, - .use_postra_scheduler, .v8_7a, }), }; @@ -4090,12 +3588,9 @@ pub const cpu = struct { .aes, .alu_lsl_fast, .crc, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8a, .zcz_gpr32, .zcz_gpr64, @@ -4109,13 +3604,11 @@ pub const cpu = struct { .alu_lsl_fast, .bf16, .ccdp, - .enable_select_opt, .fp16fml, .fpac, .fuse_adrp_add, .fuse_aes, .i8mm, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .rand, @@ -4124,7 +3617,6 @@ pub const cpu = struct { .spe, .ssbs, .sve, - .use_postra_scheduler, .v8_4a, }), }; @@ -4141,7 +3633,6 @@ pub const cpu = struct { .rcpc, .sha2, .ssbs, - .use_postra_scheduler, .v8_2a, }), }; @@ -4153,7 +3644,6 @@ pub const cpu = struct { .aes, .alu_lsl_fast, .dotprod, - .enable_select_opt, .fullfp16, .fuse_adrp_add, .fuse_aes, @@ -4163,7 +3653,6 @@ pub const cpu = struct { .sha2, .spe, .ssbs, - .use_postra_scheduler, .v8_2a, }), }; @@ -4173,7 +3662,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .alu_lsl_fast, .bf16, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -4187,8 +3675,6 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9a, }), }; @@ -4197,7 +3683,6 @@ pub const cpu = struct { .llvm_name = "neoverse-n3", .features = featureSet(&[_]Feature{ .alu_lsl_fast, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -4211,7 +3696,6 @@ pub const cpu = struct { .rand, .spe, .sve_bitperm, - .use_postra_scheduler, .v9_2a, }), }; @@ -4224,8 +3708,6 @@ pub const cpu = struct { .alu_lsl_fast, .bf16, .ccdp, - .disable_maximize_scalable_bandwidth, - .enable_select_opt, .fp16fml, .fuse_adrp_add, .fuse_aes, @@ -4241,7 +3723,6 @@ pub const cpu = struct { .spe, .ssbs, .sve, - .use_postra_scheduler, .v8_4a, }), }; @@ -4253,8 +3734,6 @@ pub const cpu = struct { .avoid_ldapur, .bf16, .cmp_bcc_fusion, - .disable_latency_sched_heuristic, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -4263,15 +3742,12 @@ pub const cpu = struct { .fuse_csel, .fuse_cset, .i8mm, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .rand, .spe, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9a, }), }; @@ -4282,7 +3758,6 @@ pub const cpu = struct { .alu_lsl_fast, .avoid_ldapur, .brbe, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -4291,15 +3766,12 @@ pub const cpu = struct { .fuse_csel, .fuse_cset, .ls64, - .max_interleave_factor_4, .mte, .perfmon, .predictable_select_expensive, .rand, .spe, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9_2a, }), }; @@ -4310,7 +3782,6 @@ pub const cpu = struct { .alu_lsl_fast, .avoid_ldapur, .brbe, - .enable_select_opt, .ete, .fp16fml, .fpac, @@ -4326,8 +3797,6 @@ pub const cpu = struct { .rand, .spe, .sve_bitperm, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, .v9_2a, }), }; @@ -4335,8 +3804,10 @@ pub const cpu = struct { .name = "olympus", .llvm_name = "olympus", .features = featureSet(&[_]Feature{ + .alu_lsl_fast, .brbe, .chk, + .cmp_bcc_fusion, .ete, .faminmax, .fp16fml, @@ -4344,11 +3815,13 @@ pub const cpu = struct { .fp8dot4, .fp8fma, .fpac, + .fuse_adrp_add, + .fuse_aes, .ls64, .lut, .mte, - .olympus, .perfmon, + .predictable_select_expensive, .rand, .spe, .sve_aes, @@ -4363,19 +3836,16 @@ pub const cpu = struct { .llvm_name = "oryon-1", .features = featureSet(&[_]Feature{ .aes, - .enable_select_opt, .fp16fml, .fuse_address, .fuse_adrp_add, .fuse_aes, .fuse_crypto_eor, - .max_interleave_factor_4, .perfmon, .rand, .sha3, .sm4, .spe, - .use_postra_scheduler, .v8_6a, }), }; @@ -4383,8 +3853,10 @@ pub const cpu = struct { .name = "rigel", .llvm_name = "rigel", .features = featureSet(&[_]Feature{ + .alu_lsl_fast, .brbe, .chk, + .cmp_bcc_fusion, .ete, .faminmax, .fp16fml, @@ -4392,11 +3864,13 @@ pub const cpu = struct { .fp8dot4, .fp8fma, .fpac, + .fuse_adrp_add, + .fuse_aes, .ls64, .lut, .mte, - .olympus, .perfmon, + .predictable_select_expensive, .rand, .spe, .sve_aes, @@ -4412,13 +3886,10 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .aes, .alu_lsl_fast, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .sha2, .spe, - .store_pair_suppress, - .use_postra_scheduler, .v8_4a, .zcz_gpr32, .zcz_gpr64, @@ -4433,8 +3904,6 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8a, }), }; @@ -4445,11 +3914,8 @@ pub const cpu = struct { .aes, .aggressive_fma, .arith_bcc_fusion, - .max_interleave_factor_4, .predictable_select_expensive, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8_1a, }), }; @@ -4461,13 +3927,9 @@ pub const cpu = struct { .aggressive_fma, .arith_bcc_fusion, .balance_fp_ops, - .max_interleave_factor_4, .perfmon, .predictable_select_expensive, .sha2, - .store_pair_suppress, - .strict_align, - .use_postra_scheduler, .v8_3a, }), }; @@ -4480,8 +3942,6 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8a, }), }; @@ -4494,8 +3954,6 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8a, }), }; @@ -4508,8 +3966,6 @@ pub const cpu = struct { .perfmon, .predictable_select_expensive, .sha2, - .store_pair_suppress, - .use_postra_scheduler, .v8a, }), }; @@ -4526,14 +3982,12 @@ pub const cpu = struct { .perfmon, .sha2, .spe, - .store_pair_suppress, - .use_postra_scheduler, .v8_2a, }), }; pub const xgene1: CpuModel = .{ .name = "xgene1", - .llvm_name = null, + .llvm_name = "generic", .features = featureSet(&[_]Feature{ .perfmon, .v8a, diff --git a/lib/std/Target/amdgcn.zig b/lib/std/Target/amdgcn.zig index 9493dc2bf7..b6c11fb696 100644 --- a/lib/std/Target/amdgcn.zig +++ b/lib/std/Target/amdgcn.zig @@ -23,7 +23,6 @@ pub const Feature = enum { architected_flat_scratch, architected_sgprs, ashr_pk_insts, - assembler_permissive_wavesize, asynccnt, atomic_buffer_global_pk_add_f16_insts, atomic_buffer_global_pk_add_f16_no_rtn_insts, @@ -45,12 +44,9 @@ pub const Feature = enum { bf16_trans_insts, bf8_cvt_scale_insts, bitop3_insts, - block_vgpr_csr, bvh_dual_bvh_8_insts, - ci_insts, clusters, cube_insts, - cumode, cvt_fp8_vop1_bug, cvt_norm_insts, cvt_pk_f16_f32_inst, @@ -79,7 +75,6 @@ pub const Feature = enum { dpp_row_bcast, dpp_src1_sgpr, dpp_wavefront_shifts, - ds128, ds_src2_insts, dx10_clamp_and_ieee_mode, emulated_system_scope_atomics, @@ -91,20 +86,17 @@ pub const Feature = enum { flat_address_space, flat_atomic_fadd_f32_inst, flat_buffer_global_fadd_f64_inst, - flat_for_global, flat_global_insts, flat_gvs_mode, flat_inst_offsets, flat_offset_bits_12, flat_offset_bits_24, - flat_scratch, flat_scratch_insts, flat_segment_offset_bug, flat_signed_offset, fma_mix_bf16_insts, fma_mix_insts, fmacf64_inst, - fmaf, formatted_mubuf_insts, fp4_cvt_scale_insts, fp64, @@ -119,27 +111,23 @@ pub const Feature = enum { gds, get_wave_id_inst, gfx10, - gfx10_3_insts, + gfx10_3, gfx10_a_encoding, gfx10_b_encoding, - gfx10_insts, gfx11, - gfx11_7_insts, - gfx11_insts, + gfx11_7, gfx12, - gfx1250_insts, gfx1251_gemm_insts, gfx125x_lowest_rate_wmma, - gfx12_insts, + gfx12_5, gfx13, - gfx13_insts, + gfx7, gfx7_gfx8_gfx9_insts, - gfx8_insts, + gfx8, gfx9, - gfx90a_insts, - gfx940_insts, - gfx950_insts, - gfx9_insts, + gfx9_0a, + gfx9_4, + gfx9_5, globally_addressable_scratch, gws, half_rate_64_ops, @@ -159,7 +147,6 @@ pub const Feature = enum { ldsbankcount16, ldsbankcount32, lerp_inst, - load_store_opt, lshl_add_u64_inst, mad_intra_fwd_bug, mad_mac_f32_insts, @@ -169,9 +156,6 @@ pub const Feature = enum { mai_insts, max_hard_clause_length_32, max_hard_clause_length_63, - max_private_element_size_16, - max_private_element_size_4, - max_private_element_size_8, mcast_load_insts, memory_atomic_fadd_f32_denormal_support, mfma_inline_literal_bug, @@ -207,14 +191,11 @@ pub const Feature = enum { pk_add_min_max_insts, pk_fmac_f16_inst, point_sample_accel, - precise_memory, priv_enabled_trap2_nop_bug, prng_inst, - prt_strict_null, pseudo_scalar_trans, qsad_insts, r128_a16, - real_true16, required_export_priority, requires_cov6, requires_initial_unclause_vmem, @@ -239,17 +220,13 @@ pub const Feature = enum { sdwa_out_mods_vopc, sdwa_scalar, sdwa_sdst, - sea_islands, setprio_inc_wg_inst, setreg_vgpr_msb_fixup, sgpr_init_bug, shader_cycles_hi_lo_registers, shader_cycles_register, - si_scheduler, smem_prefetch_insts, smem_to_vector_write_hazard, - southern_islands, - sramecc, sramecc_support, swmmac_gfx1200_insts, swmmac_gfx1250_insts, @@ -258,16 +235,12 @@ pub const Feature = enum { tgsplit_support, trans_coexecution_hazard, transpose_load_f4f6_insts, - trap_handler, trig_reduced_range, true16, - unaligned_access_mode, unaligned_buffer_access, unaligned_ds_access, unaligned_scratch_access, unpacked_d16_vmem, - unsafe_ds_offset_folding, - use_add_pc64_inst, user_sgpr_init16_bug, v_mov_b64_inst, v_mul_u64_inst, @@ -280,7 +253,6 @@ pub const Feature = enum { vmem_to_lds_load_insts, vmem_to_scalar_write_hazard, vmem_write_vgpr_in_order, - volcanic_islands, vop3_literal, vop3p, vop3px2_increments_va_vdst_twice, @@ -295,7 +267,6 @@ pub const Feature = enum { wmma_256b_insts, wmma_coexecution_hazards, xf32_insts, - xnack, xnack_on_off_modes, xnack_support, }; @@ -400,11 +371,6 @@ pub const all_features = blk: { .description = "Has Arithmetic Shift Pack instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.assembler_permissive_wavesize)] = .{ - .llvm_name = "assembler-permissive-wavesize", - .description = "Allow parsing wave32 and wave64 variants of instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.asynccnt)] = .{ .llvm_name = "asynccnt", .description = "Has separate asynccnt counter", @@ -524,21 +490,11 @@ pub const all_features = blk: { .description = "Has v_bitop3_b32/v_bitop3_b16 instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.block_vgpr_csr)] = .{ - .llvm_name = "block-vgpr-csr", - .description = "Use block load/store for VGPR callee saved registers", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.bvh_dual_bvh_8_insts)] = .{ .llvm_name = "bvh-dual-bvh-8-insts", .description = "Has image_bvh_dual_intersect_ray and image_bvh8_intersect_ray instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.ci_insts)] = .{ - .llvm_name = "ci-insts", - .description = "Additional instructions for CI+", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.clusters)] = .{ .llvm_name = "clusters", .description = "Has clusters of workgroups support", @@ -549,11 +505,6 @@ pub const all_features = blk: { .description = "Has v_cube* instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.cumode)] = .{ - .llvm_name = "cumode", - .description = "Enable CU wavefront execution mode", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.cvt_fp8_vop1_bug)] = .{ .llvm_name = "cvt-fp8-vop1-bug", .description = "FP8/BF8 VOP1 form of conversion to F32 is unreliable", @@ -696,11 +647,6 @@ pub const all_features = blk: { .description = "Support DPP wave_shl/wave_rol/wave_shr/wave_ror", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.ds128)] = .{ - .llvm_name = "enable-ds128", - .description = "Use ds_{read|write}_b128", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.ds_src2_insts)] = .{ .llvm_name = "ds-src2-insts", .description = "Has ds_*_src2 instructions", @@ -758,11 +704,6 @@ pub const all_features = blk: { .description = "Has flat, buffer, and global instructions for f64 atomic fadd", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.flat_for_global)] = .{ - .llvm_name = "flat-for-global", - .description = "Force to generate flat instruction for global", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.flat_global_insts)] = .{ .llvm_name = "flat-global-insts", .description = "Have global_* flat memory instructions", @@ -792,11 +733,6 @@ pub const all_features = blk: { .description = "Number of bits for flat offset encoding", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.flat_scratch)] = .{ - .llvm_name = "enable-flat-scratch", - .description = "Use scratch_* flat memory instructions to access scratch", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.flat_scratch_insts)] = .{ .llvm_name = "flat-scratch-insts", .description = "Have scratch_* flat memory instructions", @@ -829,11 +765,6 @@ pub const all_features = blk: { .description = "Has v_fmac_f64 instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.fmaf)] = .{ - .llvm_name = "fmaf", - .description = "Enable single precision FMA (not as fast as mul+add, but fused)", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.formatted_mubuf_insts)] = .{ .llvm_name = "formatted-mubuf-insts", .description = "Has formatted memory untyped buffer instructions.", @@ -900,81 +831,18 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.gfx10)] = .{ - .llvm_name = "gfx10", - .description = "GFX10 GPU generation", + .llvm_name = "gfx10-insts", + .description = "Additional instructions for GFX10+", .dependencies = featureSet(&[_]Feature{ - .@"16_bit_insts", - .a16, - .add_no_carry_insts, - .addressablelocalmemorysize65536, - .aperture_regs, - .atomic_fmin_fmax_flat_f32, - .atomic_fmin_fmax_flat_f64, - .atomic_fmin_fmax_global_f32, - .atomic_fmin_fmax_global_f64, - .ci_insts, - .cube_insts, - .cvt_norm_insts, - .cvt_pknorm_vop2_insts, - .cvt_pknorm_vop3_insts, - .default_component_zero, - .dpp, - .dpp8, - .dx10_clamp_and_ieee_mode, - .extended_image_insts, - .fast_denormal_f32, - .fast_fmaf, - .flat_global_insts, - .flat_inst_offsets, - .flat_offset_bits_12, - .flat_scratch_insts, - .fma_mix_insts, - .formatted_mubuf_insts, - .fp64, - .g16, - .gds, - .gfx10_insts, - .gfx8_insts, - .gfx9_insts, - .gws, - .image_insts, - .instcachelinesize64, - .int_clamp_insts, - .inv_2pi_inline_imm, - .lerp_inst, - .max_hard_clause_length_63, - .mimg_r128, - .movrel, - .mqsad_insts, - .mqsad_pk_insts, - .msad_insts, - .mtbuf_insts, - .no_data_dep_hazard, - .no_sdst_cmpx, - .permlane16_insts, - .pk_fmac_f16_inst, - .qsad_insts, - .s_memrealtime, - .s_memtime_inst, - .sad_insts, - .sdwa, - .sdwa_omod, - .sdwa_scalar, - .sdwa_sdst, - .unaligned_buffer_access, - .unaligned_ds_access, - .unaligned_scratch_access, - .vmem_to_lds_load_insts, - .vmem_write_vgpr_in_order, - .vop3_literal, - .vop3p, - .vscnt, + .gfx9, }), }; - result[@backingInt(Feature.gfx10_3_insts)] = .{ + result[@backingInt(Feature.gfx10_3)] = .{ .llvm_name = "gfx10-3-insts", .description = "Additional instructions for GFX10.3", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .gfx10, + }), }; result[@backingInt(Feature.gfx10_a_encoding)] = .{ .llvm_name = "gfx10_a-encoding", @@ -986,148 +854,26 @@ pub const all_features = blk: { .description = "Encoding format GFX10_B", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.gfx10_insts)] = .{ - .llvm_name = "gfx10-insts", - .description = "Additional instructions for GFX10+", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.gfx11)] = .{ - .llvm_name = "gfx11", - .description = "GFX11 GPU generation", - .dependencies = featureSet(&[_]Feature{ - .@"16_bit_insts", - .a16, - .add_no_carry_insts, - .addressablelocalmemorysize65536, - .aperture_regs, - .atomic_fmin_fmax_flat_f32, - .atomic_fmin_fmax_global_f32, - .ci_insts, - .cube_insts, - .cvt_norm_insts, - .cvt_pknorm_vop2_insts, - .cvt_pknorm_vop3_insts, - .default_component_zero, - .dpp, - .dpp8, - .extended_image_insts, - .fast_denormal_f32, - .fast_fmaf, - .flat_global_insts, - .flat_inst_offsets, - .flat_scratch_insts, - .fma_mix_insts, - .formatted_mubuf_insts, - .fp64, - .g16, - .gds, - .gfx10_3_insts, - .gfx10_a_encoding, - .gfx10_b_encoding, - .gfx10_insts, - .gfx11_insts, - .gfx8_insts, - .gfx9_insts, - .gws, - .instcachelinesize128, - .int_clamp_insts, - .inv_2pi_inline_imm, - .lerp_inst, - .max_hard_clause_length_32, - .mimg_r128, - .movrel, - .mqsad_insts, - .mqsad_pk_insts, - .msad_insts, - .mtbuf_insts, - .no_data_dep_hazard, - .no_sdst_cmpx, - .permlane16_insts, - .pk_fmac_f16_inst, - .qsad_insts, - .sad_insts, - .true16, - .unaligned_buffer_access, - .unaligned_ds_access, - .unaligned_scratch_access, - .vmem_write_vgpr_in_order, - .vop3_literal, - .vop3p, - .vopd, - .vscnt, - }), - }; - result[@backingInt(Feature.gfx11_7_insts)] = .{ - .llvm_name = "gfx11-7-insts", - .description = "Additional instructions for GFX11.7", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.gfx11_insts)] = .{ .llvm_name = "gfx11-insts", .description = "Additional instructions for GFX11+", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.gfx12)] = .{ - .llvm_name = "gfx12", - .description = "GFX12 GPU generation", .dependencies = featureSet(&[_]Feature{ - .@"16_bit_insts", - .a16, - .add_no_carry_insts, - .agent_scope_fine_grained_remote_memory_atomics, - .aperture_regs, - .atomic_fmin_fmax_flat_f32, - .atomic_fmin_fmax_global_f32, - .ci_insts, - .default_component_broadcast, - .dpp, - .dpp8, - .fast_denormal_f32, - .fast_fmaf, - .flat_global_insts, - .flat_inst_offsets, - .flat_offset_bits_24, - .flat_scratch_insts, - .flat_signed_offset, - .fma_mix_insts, - .fp64, - .g16, - .gfx10_3_insts, - .gfx10_a_encoding, - .gfx10_b_encoding, - .gfx10_insts, - .gfx11_insts, - .gfx12_insts, - .gfx8_insts, - .gfx9_insts, - .ieee_minimum_maximum_insts, - .instcachelinesize128, - .int_clamp_insts, - .inv_2pi_inline_imm, - .max_hard_clause_length_32, - .mimg_r128, - .minimum3_maximum3_f16, - .minimum3_maximum3_f32, - .movrel, - .no_data_dep_hazard, - .no_sdst_cmpx, - .permlane16_insts, - .pk_fmac_f16_inst, - .salu_minimum_maximum_insts, - .true16, - .unaligned_buffer_access, - .unaligned_ds_access, - .unaligned_scratch_access, - .vop3_literal, - .vop3p, - .vopd, - .vscnt, + .gfx10_3, }), }; - result[@backingInt(Feature.gfx1250_insts)] = .{ - .llvm_name = "gfx1250-insts", - .description = "Additional instructions for GFX1250+", - .dependencies = featureSet(&[_]Feature{}), + result[@backingInt(Feature.gfx11_7)] = .{ + .llvm_name = "gfx11-7-insts", + .description = "Additional instructions for GFX11.7", + .dependencies = featureSet(&[_]Feature{ + .gfx11, + }), + }; + result[@backingInt(Feature.gfx12)] = .{ + .llvm_name = "gfx12-insts", + .description = "Additional instructions for GFX12+", + .dependencies = featureSet(&[_]Feature{ + .gfx11, + }), }; result[@backingInt(Feature.gfx1251_gemm_insts)] = .{ .llvm_name = "gfx1251-gemm-insts", @@ -1139,164 +885,61 @@ pub const all_features = blk: { .description = "Has the lowest rate wmma in the gfx125x family, mainly for the gfx12-5-generic", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.gfx12_insts)] = .{ - .llvm_name = "gfx12-insts", - .description = "Additional instructions for GFX12+", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.gfx13)] = .{ - .llvm_name = "gfx13", - .description = "GFX13 GPU generation", + result[@backingInt(Feature.gfx12_5)] = .{ + .llvm_name = "gfx1250-insts", + .description = "Additional instructions for GFX1250+", .dependencies = featureSet(&[_]Feature{ - .@"16_bit_insts", - .a16, - .add_no_carry_insts, - .agent_scope_fine_grained_remote_memory_atomics, - .aperture_regs, - .atomic_fmin_fmax_flat_f32, - .atomic_fmin_fmax_global_f32, - .ci_insts, - .default_component_broadcast, - .dpp, - .dpp8, - .extended_image_insts, - .fast_denormal_f32, - .fast_fmaf, - .flat_global_insts, - .flat_inst_offsets, - .flat_offset_bits_24, - .flat_scratch_insts, - .flat_signed_offset, - .fma_mix_insts, - .formatted_mubuf_insts, - .fp64, - .g16, - .gfx10_3_insts, - .gfx10_a_encoding, - .gfx10_b_encoding, - .gfx10_insts, - .gfx11_insts, - .gfx12_insts, - .gfx13_insts, - .gfx8_insts, - .gfx9_insts, - .ieee_minimum_maximum_insts, - .image_insts, - .instcachelinesize128, - .int_clamp_insts, - .inv_2pi_inline_imm, - .max_hard_clause_length_32, - .mimg_r128, - .minimum3_maximum3_f16, - .minimum3_maximum3_f32, - .movrel, - .mtbuf_insts, - .no_data_dep_hazard, - .no_sdst_cmpx, - .permlane16_insts, - .pk_fmac_f16_inst, - .salu_minimum_maximum_insts, - .true16, - .unaligned_buffer_access, - .unaligned_ds_access, - .unaligned_scratch_access, - .vop3_literal, - .vop3p, - .vopd, - .vscnt, + .gfx12, }), }; - result[@backingInt(Feature.gfx13_insts)] = .{ + result[@backingInt(Feature.gfx13)] = .{ .llvm_name = "gfx13-insts", .description = "Additional instructions for GFX13+", .dependencies = featureSet(&[_]Feature{ + .gfx12, .s_barrier_leave_imm, .s_wakeup_imm, }), }; + result[@backingInt(Feature.gfx7)] = .{ + .llvm_name = "ci-insts", + .description = "Additional instructions for CI+", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.gfx7_gfx8_gfx9_insts)] = .{ .llvm_name = "gfx7-gfx8-gfx9-insts", .description = "Instructions shared in GFX7, GFX8, GFX9", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.gfx8_insts)] = .{ + result[@backingInt(Feature.gfx8)] = .{ .llvm_name = "gfx8-insts", .description = "Additional instructions for GFX8+", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.gfx9)] = .{ - .llvm_name = "gfx9", - .description = "GFX9 GPU generation", .dependencies = featureSet(&[_]Feature{ - .@"16_bit_insts", - .a16, - .add_no_carry_insts, - .aperture_regs, - .ci_insts, - .cube_insts, - .cvt_norm_insts, - .cvt_pknorm_vop2_insts, - .cvt_pknorm_vop3_insts, - .default_component_zero, - .dpp, - .dpp_row_bcast, - .dpp_wavefront_shifts, - .dx10_clamp_and_ieee_mode, - .fast_denormal_f32, - .fast_fmaf, - .flat_global_insts, - .flat_inst_offsets, - .flat_scratch_insts, - .formatted_mubuf_insts, - .fp64, - .gcn3_encoding, - .gfx7_gfx8_gfx9_insts, - .gfx8_insts, - .gfx9_insts, - .gws, - .instcachelinesize64, - .int_clamp_insts, - .inv_2pi_inline_imm, - .lerp_inst, - .mqsad_insts, - .mqsad_pk_insts, - .msad_insts, - .mtbuf_insts, - .negative_scratch_offset_bug, - .qsad_insts, - .r128_a16, - .s_memrealtime, - .s_memtime_inst, - .sad_insts, - .scalar_atomics, - .scalar_flat_scratch_insts, - .scalar_stores, - .sdwa, - .sdwa_omod, - .sdwa_scalar, - .sdwa_sdst, - .unaligned_buffer_access, - .unaligned_ds_access, - .unaligned_scratch_access, - .vgpr_index_mode, - .vmem_to_lds_load_insts, - .vmem_write_vgpr_in_order, - .vop3p, - .wavefrontsize64, - .xnack_on_off_modes, + .gfx7, }), }; - result[@backingInt(Feature.gfx90a_insts)] = .{ + result[@backingInt(Feature.gfx9)] = .{ + .llvm_name = "gfx9-insts", + .description = "Additional instructions for GFX9+", + .dependencies = featureSet(&[_]Feature{ + .gfx8, + }), + }; + result[@backingInt(Feature.gfx9_0a)] = .{ .llvm_name = "gfx90a-insts", .description = "Additional instructions for GFX90A+", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .gfx9, + }), }; - result[@backingInt(Feature.gfx940_insts)] = .{ + result[@backingInt(Feature.gfx9_4)] = .{ .llvm_name = "gfx940-insts", .description = "Additional instructions for GFX940+", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .gfx9_0a, + }), }; - result[@backingInt(Feature.gfx950_insts)] = .{ + result[@backingInt(Feature.gfx9_5)] = .{ .llvm_name = "gfx950-insts", .description = "Additional instructions for GFX950+", .dependencies = featureSet(&[_]Feature{ @@ -1308,17 +951,13 @@ pub const all_features = blk: { .fp4_cvt_scale_insts, .fp6bf6_cvt_scale_insts, .fp8_cvt_scale_insts, + .gfx9_4, .minimum3_maximum3_f32, .minimum3_maximum3_pkf16, .permlane16_swap, .permlane32_swap, }), }; - result[@backingInt(Feature.gfx9_insts)] = .{ - .llvm_name = "gfx9-insts", - .description = "Additional instructions for GFX9+", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.globally_addressable_scratch)] = .{ .llvm_name = "globally-addressable-scratch", .description = "FLAT instructions can access scratch memory for any thread in any wave", @@ -1414,11 +1053,6 @@ pub const all_features = blk: { .description = "Has v_lerp_u8 instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.load_store_opt)] = .{ - .llvm_name = "load-store-opt", - .description = "Enable SI load/store optimizer pass", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.lshl_add_u64_inst)] = .{ .llvm_name = "lshl-add-u64-inst", .description = "Has v_lshl_add_u64 instruction", @@ -1464,21 +1098,6 @@ pub const all_features = blk: { .description = "Maximum number of instructions in an explicit S_CLAUSE is 63", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.max_private_element_size_16)] = .{ - .llvm_name = "max-private-element-size-16", - .description = "Maximum private access size may be 16", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.max_private_element_size_4)] = .{ - .llvm_name = "max-private-element-size-4", - .description = "Maximum private access size may be 4", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.max_private_element_size_8)] = .{ - .llvm_name = "max-private-element-size-8", - .description = "Maximum private access size may be 8", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.mcast_load_insts)] = .{ .llvm_name = "mcast-load-insts", .description = "Has multicast load instructions", @@ -1654,11 +1273,6 @@ pub const all_features = blk: { .description = "Has point sample acceleration feature", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.precise_memory)] = .{ - .llvm_name = "precise-memory", - .description = "Enable precise memory mode", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.priv_enabled_trap2_nop_bug)] = .{ .llvm_name = "priv-enabled-trap2-nop-bug", .description = "Hardware that runs with PRIV=1 interpreting 's_trap 2' as a nop bug", @@ -1669,11 +1283,6 @@ pub const all_features = blk: { .description = "Has v_prng_b32 instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.prt_strict_null)] = .{ - .llvm_name = "enable-prt-strict-null", - .description = "Enable zeroing of result registers for sparse texture fetches", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.pseudo_scalar_trans)] = .{ .llvm_name = "pseudo-scalar-trans", .description = "Has Pseudo Scalar Transcendental instructions", @@ -1689,11 +1298,6 @@ pub const all_features = blk: { .description = "Support gfx9-style A16 for 16-bit coordinates/gradients/lod/clamp/mip image operands, where a16 is aliased with r128", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.real_true16)] = .{ - .llvm_name = "real-true16", - .description = "Use true 16-bit registers", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.required_export_priority)] = .{ .llvm_name = "required-export-priority", .description = "Export priority must be explicitly manipulated on GFX11.5", @@ -1814,46 +1418,6 @@ pub const all_features = blk: { .description = "Support scalar dst for VOPC with SDWA (Sub-DWORD Addressing) extension", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.sea_islands)] = .{ - .llvm_name = "sea-islands", - .description = "SEA_ISLANDS GPU generation", - .dependencies = featureSet(&[_]Feature{ - .addressablelocalmemorysize65536, - .atomic_fmin_fmax_flat_f32, - .atomic_fmin_fmax_flat_f64, - .atomic_fmin_fmax_global_f32, - .atomic_fmin_fmax_global_f64, - .ci_insts, - .cube_insts, - .cvt_pknorm_vop2_insts, - .default_component_zero, - .ds_src2_insts, - .dx10_clamp_and_ieee_mode, - .extended_image_insts, - .formatted_mubuf_insts, - .fp64, - .gds, - .gfx7_gfx8_gfx9_insts, - .gws, - .image_insts, - .instcachelinesize64, - .lerp_inst, - .mad_mac_f32_insts, - .mimg_r128, - .movrel, - .mqsad_insts, - .mqsad_pk_insts, - .msad_insts, - .mtbuf_insts, - .qsad_insts, - .s_memtime_inst, - .sad_insts, - .trig_reduced_range, - .unaligned_buffer_access, - .vmem_write_vgpr_in_order, - .wavefrontsize64, - }), - }; result[@backingInt(Feature.setprio_inc_wg_inst)] = .{ .llvm_name = "setprio-inc-wg-inst", .description = "Has s_setprio_inc_wg instruction.", @@ -1879,11 +1443,6 @@ pub const all_features = blk: { .description = "Has SHADER_CYCLES hardware register", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.si_scheduler)] = .{ - .llvm_name = "si-scheduler", - .description = "Enable SI Machine Scheduler", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.smem_prefetch_insts)] = .{ .llvm_name = "smem-prefetch-insts", .description = "Has s_prefetch_inst, s_prefetch_inst_pc_rel, s_prefetch_data and s_prefetch_data_pc_rel instructions", @@ -1894,45 +1453,6 @@ pub const all_features = blk: { .description = "s_load_dword followed by v_cmp page faults", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.southern_islands)] = .{ - .llvm_name = "southern-islands", - .description = "SOUTHERN_ISLANDS GPU generation", - .dependencies = featureSet(&[_]Feature{ - .addressablelocalmemorysize32768, - .atomic_fmin_fmax_global_f32, - .atomic_fmin_fmax_global_f64, - .cube_insts, - .cvt_pknorm_vop2_insts, - .default_component_zero, - .ds_src2_insts, - .dx10_clamp_and_ieee_mode, - .extended_image_insts, - .formatted_mubuf_insts, - .fp64, - .gds, - .gws, - .image_insts, - .instcachelinesize64, - .ldsbankcount32, - .lerp_inst, - .mad_mac_f32_insts, - .mimg_r128, - .movrel, - .mqsad_pk_insts, - .msad_insts, - .mtbuf_insts, - .s_memtime_inst, - .sad_insts, - .trig_reduced_range, - .vmem_write_vgpr_in_order, - .wavefrontsize64, - }), - }; - result[@backingInt(Feature.sramecc)] = .{ - .llvm_name = "sramecc", - .description = "Enable SRAMECC", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.sramecc_support)] = .{ .llvm_name = "sramecc-support", .description = "Hardware supports SRAMECC", @@ -1973,11 +1493,6 @@ pub const all_features = blk: { .description = "Has ds_load_tr4/tr6 and global_load_tr4/tr6 instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.trap_handler)] = .{ - .llvm_name = "trap-handler", - .description = "Trap handler support", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.trig_reduced_range)] = .{ .llvm_name = "trig-reduced-range", .description = "Requires use of fract on arguments to trig instructions", @@ -1988,11 +1503,6 @@ pub const all_features = blk: { .description = "True 16-bit operand instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.unaligned_access_mode)] = .{ - .llvm_name = "unaligned-access-mode", - .description = "Enable unaligned global, local and region loads and stores if the hardware supports it", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.unaligned_buffer_access)] = .{ .llvm_name = "unaligned-buffer-access", .description = "Hardware supports unaligned global loads and stores", @@ -2013,16 +1523,6 @@ pub const all_features = blk: { .description = "Has unpacked d16 vmem instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.unsafe_ds_offset_folding)] = .{ - .llvm_name = "unsafe-ds-offset-folding", - .description = "Force using DS instruction immediate offsets on SI", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.use_add_pc64_inst)] = .{ - .llvm_name = "use-add-pc64-inst", - .description = "Use s_add_pc_i64 instruction.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.user_sgpr_init16_bug)] = .{ .llvm_name = "user-sgpr-init16-bug", .description = "Bug requiring at least 16 user+system SGPRs to be enabled", @@ -2083,58 +1583,6 @@ pub const all_features = blk: { .description = "VMEM instructions of the same type write VGPR results in order", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.volcanic_islands)] = .{ - .llvm_name = "volcanic-islands", - .description = "VOLCANIC_ISLANDS GPU generation", - .dependencies = featureSet(&[_]Feature{ - .@"16_bit_insts", - .addressablelocalmemorysize65536, - .ci_insts, - .cube_insts, - .cvt_pknorm_vop2_insts, - .default_component_zero, - .dpp, - .dpp_row_bcast, - .dpp_wavefront_shifts, - .ds_src2_insts, - .dx10_clamp_and_ieee_mode, - .extended_image_insts, - .fast_denormal_f32, - .flat_address_space, - .formatted_mubuf_insts, - .fp64, - .gcn3_encoding, - .gds, - .gfx7_gfx8_gfx9_insts, - .gfx8_insts, - .gws, - .image_insts, - .instcachelinesize64, - .int_clamp_insts, - .inv_2pi_inline_imm, - .lerp_inst, - .mad_mac_f32_insts, - .mimg_r128, - .movrel, - .mqsad_insts, - .mqsad_pk_insts, - .msad_insts, - .mtbuf_insts, - .qsad_insts, - .s_memrealtime, - .s_memtime_inst, - .sad_insts, - .scalar_stores, - .sdwa, - .sdwa_mav, - .sdwa_out_mods_vopc, - .trig_reduced_range, - .unaligned_buffer_access, - .vgpr_index_mode, - .vmem_write_vgpr_in_order, - .wavefrontsize64, - }), - }; result[@backingInt(Feature.vop3_literal)] = .{ .llvm_name = "vop3-literal", .description = "Can use one literal in VOP3", @@ -2205,13 +1653,6 @@ pub const all_features = blk: { .description = "Has instructions that support xf32 format, such as v_mfma_f32_16x16x8_xf32 and v_mfma_f32_32x32x4_xf32", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.xnack)] = .{ - .llvm_name = "xnack", - .description = "Enable XNACK support", - .dependencies = featureSet(&[_]Feature{ - .xnack_support, - }), - }; result[@backingInt(Feature.xnack_on_off_modes)] = .{ .llvm_name = "xnack-on-off-modes", .description = "Target supports XNACK on/off modes", @@ -2237,19 +1678,96 @@ pub const cpu = struct { .name = "bonaire", .llvm_name = "bonaire", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount32, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const carrizo: CpuModel = .{ .name = "carrizo", .llvm_name = "carrizo", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, .fast_fmaf, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, .half_rate_64_ops, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, .xnack_on_off_modes, }), }; @@ -2257,50 +1775,144 @@ pub const cpu = struct { .name = "fiji", .llvm_name = "fiji", .features = featureSet(&[_]Feature{ - .ldsbankcount32, - .unpacked_d16_vmem, - .volcanic_islands, - }), - }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{}), - }; - pub const generic_hsa: CpuModel = .{ - .name = "generic_hsa", - .llvm_name = "generic-hsa", - .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, + .trig_reduced_range, + .unaligned_buffer_access, + .unpacked_d16_vmem, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx1010: CpuModel = .{ .name = "gfx1010", .llvm_name = "gfx1010", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, + .dpp, + .dpp8, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, .flat_segment_offset_bug, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, .get_wave_id_inst, .gfx10, + .gws, + .image_insts, .inst_fwd_prefetch_bug, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .lds_branch_vmem_war_hazard, .lds_misaligned_bug, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .negative_unaligned_scratch_offset_bug, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_clause_bug, .nsa_encoding, .nsa_to_vmem_bug, .offset_3f_bug, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .smem_to_vector_write_hazard, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, + .vmem_to_lds_load_insts, .vmem_to_scalar_write_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, .xnack_on_off_modes, }), }; @@ -2308,7 +1920,21 @@ pub const cpu = struct { .name = "gfx1011", .llvm_name = "gfx1011", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2316,27 +1942,75 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, + .dpp, + .dpp8, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, .flat_segment_offset_bug, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, .get_wave_id_inst, .gfx10, + .gws, + .image_insts, .inst_fwd_prefetch_bug, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .lds_branch_vmem_war_hazard, .lds_misaligned_bug, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .negative_unaligned_scratch_offset_bug, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_clause_bug, .nsa_encoding, .nsa_to_vmem_bug, .offset_3f_bug, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .smem_to_vector_write_hazard, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, + .vmem_to_lds_load_insts, .vmem_to_scalar_write_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, .xnack_on_off_modes, }), }; @@ -2344,7 +2018,21 @@ pub const cpu = struct { .name = "gfx1012", .llvm_name = "gfx1012", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2352,27 +2040,75 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, + .dpp, + .dpp8, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, .flat_segment_offset_bug, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, .get_wave_id_inst, .gfx10, + .gws, + .image_insts, .inst_fwd_prefetch_bug, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .lds_branch_vmem_war_hazard, .lds_misaligned_bug, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .negative_unaligned_scratch_offset_bug, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_clause_bug, .nsa_encoding, .nsa_to_vmem_bug, .offset_3f_bug, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .smem_to_vector_write_hazard, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, + .vmem_to_lds_load_insts, .vmem_to_scalar_write_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, .xnack_on_off_modes, }), }; @@ -2380,30 +2116,92 @@ pub const cpu = struct { .name = "gfx1013", .llvm_name = "gfx1013", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, + .dpp, + .dpp8, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, .flat_segment_offset_bug, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, .get_wave_id_inst, .gfx10, .gfx10_a_encoding, + .gws, + .image_insts, .inst_fwd_prefetch_bug, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .lds_branch_vmem_war_hazard, .lds_misaligned_bug, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .negative_unaligned_scratch_offset_bug, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_clause_bug, .nsa_encoding, .nsa_to_vmem_bug, .offset_3f_bug, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .smem_to_vector_write_hazard, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, + .vmem_to_lds_load_insts, .vmem_to_scalar_write_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, .xnack_on_off_modes, }), }; @@ -2411,7 +2209,21 @@ pub const cpu = struct { .name = "gfx1030", .llvm_name = "gfx1030", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2419,20 +2231,81 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, - .gfx10, - .gfx10_3_insts, + .dpp, + .dpp8, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_3, .gfx10_a_encoding, .gfx10_b_encoding, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .shader_cycles_register, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, }), }; pub const gfx1031: CpuModel = .{ .name = "gfx1031", .llvm_name = "gfx1031", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2440,20 +2313,81 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, - .gfx10, - .gfx10_3_insts, + .dpp, + .dpp8, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_3, .gfx10_a_encoding, .gfx10_b_encoding, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .shader_cycles_register, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, }), }; pub const gfx1032: CpuModel = .{ .name = "gfx1032", .llvm_name = "gfx1032", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2461,20 +2395,81 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, - .gfx10, - .gfx10_3_insts, + .dpp, + .dpp8, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_3, .gfx10_a_encoding, .gfx10_b_encoding, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .shader_cycles_register, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, }), }; pub const gfx1033: CpuModel = .{ .name = "gfx1033", .llvm_name = "gfx1033", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2482,20 +2477,81 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, - .gfx10, - .gfx10_3_insts, + .dpp, + .dpp8, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_3, .gfx10_a_encoding, .gfx10_b_encoding, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .shader_cycles_register, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, }), }; pub const gfx1034: CpuModel = .{ .name = "gfx1034", .llvm_name = "gfx1034", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2503,20 +2559,81 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, - .gfx10, - .gfx10_3_insts, + .dpp, + .dpp8, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_3, .gfx10_a_encoding, .gfx10_b_encoding, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .shader_cycles_register, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, }), }; pub const gfx1035: CpuModel = .{ .name = "gfx1035", .llvm_name = "gfx1035", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2524,20 +2641,81 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, - .gfx10, - .gfx10_3_insts, + .dpp, + .dpp8, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_3, .gfx10_a_encoding, .gfx10_b_encoding, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .shader_cycles_register, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, }), }; pub const gfx1036: CpuModel = .{ .name = "gfx1036", .llvm_name = "gfx1036", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2545,43 +2723,152 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, - .gfx10, - .gfx10_3_insts, + .dpp, + .dpp8, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_3, .gfx10_a_encoding, .gfx10_b_encoding, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .shader_cycles_register, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, }), }; pub const gfx10_1_generic: CpuModel = .{ .name = "gfx10_1_generic", .llvm_name = "gfx10-1-generic", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, + .dpp, + .dpp8, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, .flat_segment_offset_bug, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, .get_wave_id_inst, .gfx10, + .gws, + .image_insts, .inst_fwd_prefetch_bug, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .lds_branch_vmem_war_hazard, .lds_misaligned_bug, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, .negative_unaligned_scratch_offset_bug, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_clause_bug, .nsa_encoding, .nsa_to_vmem_bug, .offset_3f_bug, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, .requires_cov6, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, .scalar_atomics, .scalar_flat_scratch_insts, .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .smem_to_vector_write_hazard, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_exec_war_hazard, .vcmpx_permlane_hazard, + .vmem_to_lds_load_insts, .vmem_to_scalar_write_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, .xnack_on_off_modes, }), }; @@ -2589,7 +2876,21 @@ pub const cpu = struct { .name = "gfx10_3_generic", .llvm_name = "gfx10-3-generic", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -2597,14 +2898,61 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, - .gfx10, - .gfx10_3_insts, + .dpp, + .dpp8, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_offset_bits_12, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_3, .gfx10_a_encoding, .gfx10_b_encoding, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_63, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, .requires_cov6, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .shader_cycles_register, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vscnt, }), }; pub const gfx1100: CpuModel = .{ @@ -2612,11 +2960,23 @@ pub const cpu = struct { .llvm_name = "gfx1100", .features = featureSet(&[_]Feature{ .@"1536_physical_vgprs", + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2624,23 +2984,63 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_intra_fwd_bug, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, .msaa_load_dst_sel_bug, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .priv_enabled_trap2_nop_bug, - .real_true16, + .qsad_insts, + .sad_insts, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .user_sgpr_init16_bug, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2649,11 +3049,23 @@ pub const cpu = struct { .llvm_name = "gfx1101", .features = featureSet(&[_]Feature{ .@"1536_physical_vgprs", + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2661,22 +3073,62 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_intra_fwd_bug, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, .msaa_load_dst_sel_bug, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .priv_enabled_trap2_nop_bug, - .real_true16, + .qsad_insts, + .sad_insts, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2684,11 +3136,23 @@ pub const cpu = struct { .name = "gfx1102", .llvm_name = "gfx1102", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2696,23 +3160,63 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_intra_fwd_bug, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, .msaa_load_dst_sel_bug, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .priv_enabled_trap2_nop_bug, - .real_true16, + .qsad_insts, + .sad_insts, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .user_sgpr_init16_bug, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2720,11 +3224,23 @@ pub const cpu = struct { .name = "gfx1103", .llvm_name = "gfx1103", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2732,22 +3248,62 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_intra_fwd_bug, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, .msaa_load_dst_sel_bug, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .priv_enabled_trap2_nop_bug, - .real_true16, + .qsad_insts, + .sad_insts, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2755,11 +3311,23 @@ pub const cpu = struct { .name = "gfx1150", .llvm_name = "gfx1150", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2767,22 +3335,62 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .point_sample_accel, - .real_true16, + .qsad_insts, .required_export_priority, + .sad_insts, .salu_float, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2791,11 +3399,23 @@ pub const cpu = struct { .llvm_name = "gfx1151", .features = featureSet(&[_]Feature{ .@"1536_physical_vgprs", + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2803,22 +3423,62 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .point_sample_accel, - .real_true16, + .qsad_insts, .required_export_priority, + .sad_insts, .salu_float, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2826,11 +3486,23 @@ pub const cpu = struct { .name = "gfx1152", .llvm_name = "gfx1152", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2838,22 +3510,62 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .point_sample_accel, - .real_true16, + .qsad_insts, .required_export_priority, + .sad_insts, .salu_float, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2861,11 +3573,23 @@ pub const cpu = struct { .name = "gfx1153", .llvm_name = "gfx1153", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2873,21 +3597,61 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, - .real_true16, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, .required_export_priority, + .sad_insts, .salu_float, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2895,11 +3659,23 @@ pub const cpu = struct { .name = "gfx1154", .llvm_name = "gfx1154", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -2907,21 +3683,61 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, - .real_true16, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, .required_export_priority, + .sad_insts, .salu_float, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -2929,11 +3745,23 @@ pub const cpu = struct { .name = "gfx1170", .llvm_name = "gfx1170", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot11_insts, @@ -2941,26 +3769,65 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, - .gfx11, - .gfx11_7_insts, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, + .gfx11_7, + .gws, .ieee_minimum_maximum_insts, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, .minimum3_maximum3_f16, .minimum3_maximum3_f32, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, - .real_true16, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .sad_insts, .salu_float, .shader_cycles_register, .swmmac_gfx1200_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_128b_insts, }), }; @@ -2968,11 +3835,23 @@ pub const cpu = struct { .name = "gfx1171", .llvm_name = "gfx1171", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot11_insts, @@ -2980,26 +3859,65 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, - .gfx11, - .gfx11_7_insts, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, + .gfx11_7, + .gws, .ieee_minimum_maximum_insts, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, .minimum3_maximum3_f16, .minimum3_maximum3_f32, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, - .real_true16, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .sad_insts, .salu_float, .shader_cycles_register, .swmmac_gfx1200_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_128b_insts, }), }; @@ -3007,11 +3925,23 @@ pub const cpu = struct { .name = "gfx1172", .llvm_name = "gfx1172", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot11_insts, @@ -3019,26 +3949,65 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, - .gfx11, - .gfx11_7_insts, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, + .gfx11_7, + .gws, .ieee_minimum_maximum_insts, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, .minimum3_maximum3_f16, .minimum3_maximum3_f32, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, - .real_true16, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, + .sad_insts, .salu_float, .shader_cycles_register, .swmmac_gfx1200_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_128b_insts, }), }; @@ -3046,11 +4015,23 @@ pub const cpu = struct { .name = "gfx11_7_generic", .llvm_name = "gfx11-7-generic", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot11_insts, @@ -3058,27 +4039,66 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, - .gfx11, - .gfx11_7_insts, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, + .gfx11_7, + .gws, .ieee_minimum_maximum_insts, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, .minimum3_maximum3_f16, .minimum3_maximum3_f32, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, - .real_true16, + .permlane16_insts, + .pk_fmac_f16_inst, + .qsad_insts, .requires_cov6, + .sad_insts, .salu_float, .shader_cycles_register, .swmmac_gfx1200_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_128b_insts, }), }; @@ -3086,11 +4106,23 @@ pub const cpu = struct { .name = "gfx11_generic", .llvm_name = "gfx11-generic", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, + .addressablelocalmemorysize65536, + .aperture_regs, .architected_flat_scratch, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -3098,25 +4130,65 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_scratch_insts, + .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .g16, + .gds, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx11, + .gws, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_intra_fwd_bug, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, .msaa_load_dst_sel_bug, + .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .priv_enabled_trap2_nop_bug, - .real_true16, + .qsad_insts, .required_export_priority, .requires_cov6, + .sad_insts, .shader_cycles_register, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .user_sgpr_init16_bug, .valu_trans_use_hazard, .vcmpx_permlane_hazard, + .vmem_write_vgpr_in_order, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wmma_256b_insts, }), }; @@ -3125,7 +4197,12 @@ pub const cpu = struct { .llvm_name = "gfx1200", .features = featureSet(&[_]Feature{ .@"1536_physical_vgprs", + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .architected_sgprs, .atomic_buffer_global_pk_add_f16_insts, @@ -3134,6 +4211,8 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .atomic_global_pk_add_bf16_inst, .back_off_barrier, .bvh_dual_bvh_8_insts, @@ -3142,6 +4221,7 @@ pub const cpu = struct { .cvt_pknorm_vop2_insts, .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_broadcast, .dl_insts, .dot10_insts, .dot11_insts, @@ -3149,35 +4229,69 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, + .fma_mix_insts, .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, + .g16, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx12, + .ieee_minimum_maximum_insts, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .movrel, .mqsad_insts, .mqsad_pk_insts, .msad_insts, .mtbuf_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .pseudo_scalar_trans, .qsad_insts, - .real_true16, .restricted_soffset, .sad_insts, .salu_float, + .salu_minimum_maximum_insts, .scalar_dwordx3_loads, .shader_cycles_hi_lo_registers, .smem_prefetch_insts, .swmmac_gfx1200_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .waits_before_system_scope_stores, .wmma_128b_insts, }), @@ -3187,7 +4301,12 @@ pub const cpu = struct { .llvm_name = "gfx1201", .features = featureSet(&[_]Feature{ .@"1536_physical_vgprs", + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .architected_sgprs, .atomic_buffer_global_pk_add_f16_insts, @@ -3196,6 +4315,8 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .atomic_global_pk_add_bf16_inst, .back_off_barrier, .bvh_dual_bvh_8_insts, @@ -3204,6 +4325,7 @@ pub const cpu = struct { .cvt_pknorm_vop2_insts, .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_broadcast, .dl_insts, .dot10_insts, .dot11_insts, @@ -3211,35 +4333,69 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, + .fma_mix_insts, .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, + .g16, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx12, + .ieee_minimum_maximum_insts, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .movrel, .mqsad_insts, .mqsad_pk_insts, .msad_insts, .mtbuf_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .pseudo_scalar_trans, .qsad_insts, - .real_true16, .restricted_soffset, .sad_insts, .salu_float, + .salu_minimum_maximum_insts, .scalar_dwordx3_loads, .shader_cycles_hi_lo_registers, .smem_prefetch_insts, .swmmac_gfx1200_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .waits_before_system_scope_stores, .wmma_128b_insts, }), @@ -3249,11 +4405,16 @@ pub const cpu = struct { .llvm_name = "gfx1250", .features = featureSet(&[_]Feature{ .@"1024_addressable_vgprs", + .@"16_bit_insts", .@"45_bit_num_records_buffer_resource", .@"64_bit_literals", + .a16, .add_min_max_insts, + .add_no_carry_insts, .add_sub_u64_insts, .addressablelocalmemorysize327680, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .architected_sgprs, .ashr_pk_insts, @@ -3264,7 +4425,9 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f32, .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .back_off_barrier, @@ -3274,27 +4437,43 @@ pub const cpu = struct { .bitop3_insts, .clusters, .cube_insts, - .cumode, .cvt_norm_insts, .cvt_pk_f16_f32_inst, .cvt_pknorm_vop2_insts, .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_broadcast, .dl_insts, .dot7_insts, .dot8_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .emulated_system_scope_atomics, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, .flat_buffer_global_fadd_f64_inst, .flat_gvs_mode, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, .fma_mix_bf16_insts, + .fma_mix_insts, .fmacf64_inst, + .fp64, .fp8_conversion_insts, .fp8e5m3_insts, - .gfx12, - .gfx1250_insts, + .g16, + .gfx10_a_encoding, + .gfx10_b_encoding, + .gfx12_5, .globally_addressable_scratch, + .ieee_minimum_maximum_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .kernarg_preload, .lds_barrier_arrive_atomic, .ldsbankcount32, @@ -3302,29 +4481,38 @@ pub const cpu = struct { .lshl_add_u64_inst, .mad_nc_64_32_insts, .mad_u32_inst, + .max_hard_clause_length_32, .max_hard_clause_length_63, .mcast_load_insts, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, .min3_max3_pkf16, .min_max_i64_insts, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, .minimum3_maximum3_pkf16, + .movrel, .mqsad_insts, .mqsad_pk_insts, .msad_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .packed_fp32_ops, .packed_tid, + .permlane16_insts, .permlane16_swap, .pk_add_min_max_insts, + .pk_fmac_f16_inst, .prng_inst, .pseudo_scalar_trans, .qsad_insts, - .real_true16, .requires_initial_unclause_vmem, .restricted_soffset, .s_wakeup_barrier_inst, .sad_insts, .salu_float, + .salu_minimum_maximum_insts, .scalar_dwordx3_loads, .setprio_inc_wg_inst, .setreg_vgpr_msb_fixup, @@ -3337,16 +4525,24 @@ pub const cpu = struct { .tensor_cvt_lut_insts, .trans_coexecution_hazard, .transpose_load_f4f6_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .v_mov_b64_inst, .v_mul_u64_inst, .vcmpx_permlane_hazard, .vgpr_align2, .vmem_pref_insts, + .vop3_literal, + .vop3p, .vop3px2_increments_va_vdst_twice, + .vopd, + .vscnt, .wait_xcnt, .wavefrontsize32, .wmma_coexecution_hazards, - .xnack, + .xnack_support, }), }; pub const gfx1251: CpuModel = .{ @@ -3354,11 +4550,16 @@ pub const cpu = struct { .llvm_name = "gfx1251", .features = featureSet(&[_]Feature{ .@"1024_addressable_vgprs", + .@"16_bit_insts", .@"45_bit_num_records_buffer_resource", .@"64_bit_literals", + .a16, .add_min_max_insts, + .add_no_carry_insts, .add_sub_u64_insts, .addressablelocalmemorysize327680, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .architected_sgprs, .ashr_pk_insts, @@ -3369,7 +4570,9 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f32, .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .back_off_barrier, @@ -3379,31 +4582,47 @@ pub const cpu = struct { .bitop3_insts, .clusters, .cube_insts, - .cumode, .cvt_norm_insts, .cvt_pk_f16_f32_inst, .cvt_pknorm_vop2_insts, .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_broadcast, .dl_insts, .dot7_insts, .dot8_insts, + .dpp, + .dpp8, .dpp_64bit, .dpp_src1_sgpr, .emulated_system_scope_atomics, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, .flat_buffer_global_fadd_f64_inst, .flat_gvs_mode, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, .fma_mix_bf16_insts, + .fma_mix_insts, .fmacf64_inst, + .fp64, .fp8_conversion_insts, .fp8e5m3_insts, .full_rate_64_ops, - .gfx12, - .gfx1250_insts, + .g16, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx1251_gemm_insts, .gfx125x_lowest_rate_wmma, + .gfx12_5, .globally_addressable_scratch, + .ieee_minimum_maximum_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .kernarg_preload, .lds_barrier_arrive_atomic, .ldsbankcount32, @@ -3411,31 +4630,40 @@ pub const cpu = struct { .lshl_add_u64_inst, .mad_nc_64_32_insts, .mad_u32_inst, + .max_hard_clause_length_32, .max_hard_clause_length_63, .mcast_load_insts, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, .min3_max3_pkf16, .min_max_i64_insts, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, .minimum3_maximum3_pkf16, + .movrel, .mqsad_insts, .mqsad_pk_insts, .msad_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .packed_fp32_ops, .packed_fp64_ops, .packed_tid, .packed_u64_ops, + .permlane16_insts, .permlane16_swap, .pk_add_min_max_insts, + .pk_fmac_f16_inst, .prng_inst, .pseudo_scalar_trans, .qsad_insts, - .real_true16, .requires_initial_unclause_vmem, .restricted_soffset, .s_wakeup_barrier_inst, .sad_insts, .salu_float, + .salu_minimum_maximum_insts, .scalar_dwordx3_loads, .setprio_inc_wg_inst, .shader_cycles_hi_lo_registers, @@ -3447,17 +4675,24 @@ pub const cpu = struct { .tensor_cvt_lut_insts, .trans_coexecution_hazard, .transpose_load_f4f6_insts, - .use_add_pc64_inst, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .v_mov_b64_inst, .v_mul_u64_inst, .vcmpx_permlane_hazard, .vgpr_align2, .vmem_pref_insts, + .vop3_literal, + .vop3p, .vop3px2_increments_va_vdst_twice, + .vopd, + .vscnt, .wait_xcnt, .wavefrontsize32, .wmma_coexecution_hazards, - .xnack, + .xnack_support, }), }; pub const gfx12_5_generic: CpuModel = .{ @@ -3465,11 +4700,16 @@ pub const cpu = struct { .llvm_name = "gfx12-5-generic", .features = featureSet(&[_]Feature{ .@"1024_addressable_vgprs", + .@"16_bit_insts", .@"45_bit_num_records_buffer_resource", .@"64_bit_literals", + .a16, .add_min_max_insts, + .add_no_carry_insts, .add_sub_u64_insts, .addressablelocalmemorysize327680, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .architected_sgprs, .ashr_pk_insts, @@ -3480,7 +4720,9 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f32, .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .back_off_barrier, @@ -3489,50 +4731,75 @@ pub const cpu = struct { .bf16_trans_insts, .bitop3_insts, .clusters, - .cumode, .cvt_pk_f16_f32_inst, .d16_write_vgpr32, + .default_component_broadcast, .dl_insts, .dot7_insts, .dot8_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .emulated_system_scope_atomics, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, .flat_buffer_global_fadd_f64_inst, .flat_gvs_mode, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, .fma_mix_bf16_insts, + .fma_mix_insts, .fmacf64_inst, + .fp64, .fp8_conversion_insts, .fp8e5m3_insts, - .gfx12, - .gfx1250_insts, + .g16, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx125x_lowest_rate_wmma, + .gfx12_5, .globally_addressable_scratch, + .ieee_minimum_maximum_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .kernarg_preload, .lds_barrier_arrive_atomic, .ldsbankcount32, .lshl_add_u64_inst, .mad_nc_64_32_insts, .mad_u32_inst, + .max_hard_clause_length_32, .max_hard_clause_length_63, .mcast_load_insts, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, .min3_max3_pkf16, .min_max_i64_insts, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, .minimum3_maximum3_pkf16, + .movrel, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .packed_fp32_ops, .packed_tid, + .permlane16_insts, .permlane16_swap, .pk_add_min_max_insts, + .pk_fmac_f16_inst, .prng_inst, .pseudo_scalar_trans, - .real_true16, .requires_cov6, .requires_initial_unclause_vmem, .restricted_soffset, .s_wakeup_barrier_inst, .salu_float, + .salu_minimum_maximum_insts, .scalar_dwordx3_loads, .setprio_inc_wg_inst, .setreg_vgpr_msb_fixup, @@ -3543,15 +4810,23 @@ pub const cpu = struct { .tensor_cvt_lut_insts, .trans_coexecution_hazard, .transpose_load_f4f6_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .v_mov_b64_inst, .v_mul_u64_inst, .vcmpx_permlane_hazard, .vgpr_align2, .vmem_pref_insts, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .wait_xcnt, .wavefrontsize32, .wmma_coexecution_hazards, - .xnack, + .xnack_support, }), }; pub const gfx12_generic: CpuModel = .{ @@ -3559,7 +4834,12 @@ pub const cpu = struct { .llvm_name = "gfx12-generic", .features = featureSet(&[_]Feature{ .@"1536_physical_vgprs", + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .architected_sgprs, .atomic_buffer_global_pk_add_f16_insts, @@ -3568,6 +4848,8 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_global_f32, .atomic_global_pk_add_bf16_inst, .back_off_barrier, .bvh_dual_bvh_8_insts, @@ -3576,6 +4858,7 @@ pub const cpu = struct { .cvt_pknorm_vop2_insts, .cvt_pknorm_vop3_insts, .d16_write_vgpr32, + .default_component_broadcast, .dl_insts, .dot10_insts, .dot11_insts, @@ -3583,36 +4866,70 @@ pub const cpu = struct { .dot7_insts, .dot8_insts, .dot9_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, + .fma_mix_insts, .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, + .g16, + .gfx10_a_encoding, + .gfx10_b_encoding, .gfx12, + .ieee_minimum_maximum_insts, .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, .lerp_inst, + .max_hard_clause_length_32, .memory_atomic_fadd_f32_denormal_support, + .mimg_r128, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .movrel, .mqsad_insts, .mqsad_pk_insts, .msad_insts, .mtbuf_insts, + .no_data_dep_hazard, .no_f16_pseudo_scalar_trans_inline_constants, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, + .pk_fmac_f16_inst, .pseudo_scalar_trans, .qsad_insts, - .real_true16, .requires_cov6, .restricted_soffset, .sad_insts, .salu_float, + .salu_minimum_maximum_insts, .scalar_dwordx3_loads, .shader_cycles_hi_lo_registers, .smem_prefetch_insts, .swmmac_gfx1200_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, .waits_before_system_scope_stores, .wmma_128b_insts, }), @@ -3622,8 +4939,13 @@ pub const cpu = struct { .llvm_name = "gfx1310", .features = featureSet(&[_]Feature{ .@"1536_physical_vgprs", + .@"16_bit_insts", .@"64_bit_literals", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .architected_sgprs, .ashr_pk_insts, @@ -3633,7 +4955,9 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f32, .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .bf16_cvt_insts, @@ -3646,28 +4970,59 @@ pub const cpu = struct { .cvt_pk_f16_f32_inst, .cvt_pknorm_vop2_insts, .cvt_pknorm_vop3_insts, + .default_component_broadcast, .dl_insts, .dot7_insts, .dot8_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, + .extended_image_insts, .f16bf16_to_fp6bf6_cvt_scale_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, .flat_gvs_mode, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, .fma_mix_bf16_insts, + .fma_mix_insts, .fmacf64_inst, + .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, - .gfx1250_insts, + .g16, + .gfx10_a_encoding, + .gfx10_b_encoding, + .gfx12_5, .gfx13, .globally_addressable_scratch, + .ieee_minimum_maximum_insts, + .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, .lerp_inst, + .max_hard_clause_length_32, + .mimg_r128, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .movrel, .mqsad_insts, .mqsad_pk_insts, .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, .permlane16_swap, + .pk_fmac_f16_inst, .prng_inst, .pseudo_scalar_trans, .qsad_insts, @@ -3675,13 +5030,22 @@ pub const cpu = struct { .s_wakeup_barrier_inst, .sad_insts, .salu_float, + .salu_minimum_maximum_insts, .scalar_dwordx3_loads, .shader_cycles_register, .smem_prefetch_insts, .tanh_insts, .tensor_cvt_lut_insts, .transpose_load_f4f6_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, }), }; pub const gfx13_generic: CpuModel = .{ @@ -3689,8 +5053,13 @@ pub const cpu = struct { .llvm_name = "gfx13-generic", .features = featureSet(&[_]Feature{ .@"1536_physical_vgprs", + .@"16_bit_insts", .@"64_bit_literals", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .architected_sgprs, .ashr_pk_insts, @@ -3700,7 +5069,9 @@ pub const cpu = struct { .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_flat_pk_add_16_insts, + .atomic_fmin_fmax_flat_f32, .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .bf16_cvt_insts, @@ -3713,28 +5084,59 @@ pub const cpu = struct { .cvt_pk_f16_f32_inst, .cvt_pknorm_vop2_insts, .cvt_pknorm_vop3_insts, + .default_component_broadcast, .dl_insts, .dot7_insts, .dot8_insts, + .dpp, + .dpp8, .dpp_src1_sgpr, + .extended_image_insts, .f16bf16_to_fp6bf6_cvt_scale_insts, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, .flat_gvs_mode, + .flat_inst_offsets, + .flat_offset_bits_24, + .flat_scratch_insts, + .flat_signed_offset, .fma_mix_bf16_insts, + .fma_mix_insts, .fmacf64_inst, + .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, - .gfx1250_insts, + .g16, + .gfx10_a_encoding, + .gfx10_b_encoding, + .gfx12_5, .gfx13, .globally_addressable_scratch, + .ieee_minimum_maximum_insts, + .image_insts, + .instcachelinesize128, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, .lerp_inst, + .max_hard_clause_length_32, + .mimg_r128, + .minimum3_maximum3_f16, + .minimum3_maximum3_f32, + .movrel, .mqsad_insts, .mqsad_pk_insts, .msad_insts, + .mtbuf_insts, + .no_data_dep_hazard, + .no_sdst_cmpx, .nsa_encoding, .packed_tid, .partial_nsa_encoding, + .permlane16_insts, .permlane16_swap, + .pk_fmac_f16_inst, .prng_inst, .pseudo_scalar_trans, .qsad_insts, @@ -3743,98 +5145,430 @@ pub const cpu = struct { .s_wakeup_barrier_inst, .sad_insts, .salu_float, + .salu_minimum_maximum_insts, .scalar_dwordx3_loads, .shader_cycles_register, .smem_prefetch_insts, .tanh_insts, .tensor_cvt_lut_insts, .transpose_load_f4f6_insts, + .true16, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vcmpx_permlane_hazard, + .vop3_literal, + .vop3p, + .vopd, + .vscnt, }), }; pub const gfx600: CpuModel = .{ .name = "gfx600", .llvm_name = "gfx600", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize32768, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, .fast_fmaf, + .formatted_mubuf_insts, + .fp64, + .gds, + .gws, .half_rate_64_ops, - .southern_islands, + .image_insts, + .instcachelinesize64, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx601: CpuModel = .{ .name = "gfx601", .llvm_name = "gfx601", .features = featureSet(&[_]Feature{ - .southern_islands, + .addressablelocalmemorysize32768, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gws, + .image_insts, + .instcachelinesize64, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx602: CpuModel = .{ .name = "gfx602", .llvm_name = "gfx602", .features = featureSet(&[_]Feature{ - .southern_islands, + .addressablelocalmemorysize32768, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gws, + .image_insts, + .instcachelinesize64, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx700: CpuModel = .{ .name = "gfx700", .llvm_name = "gfx700", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount32, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx701: CpuModel = .{ .name = "gfx701", .llvm_name = "gfx701", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, .fast_fmaf, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, .half_rate_64_ops, + .image_insts, + .instcachelinesize64, .ldsbankcount32, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx702: CpuModel = .{ .name = "gfx702", .llvm_name = "gfx702", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, .fast_fmaf, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount16, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx703: CpuModel = .{ .name = "gfx703", .llvm_name = "gfx703", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount16, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx704: CpuModel = .{ .name = "gfx704", .llvm_name = "gfx704", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount32, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx705: CpuModel = .{ .name = "gfx705", .llvm_name = "gfx705", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount16, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx801: CpuModel = .{ .name = "gfx801", .llvm_name = "gfx801", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, .fast_fmaf, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, .half_rate_64_ops, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, .xnack_on_off_modes, }), }; @@ -3842,39 +5576,215 @@ pub const cpu = struct { .name = "gfx802", .llvm_name = "gfx802", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, .sgpr_init_bug, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx803: CpuModel = .{ .name = "gfx803", .llvm_name = "gfx803", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx805: CpuModel = .{ .name = "gfx805", .llvm_name = "gfx805", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, .sgpr_init_bug, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const gfx810: CpuModel = .{ .name = "gfx810", .llvm_name = "gfx810", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, .image_gather4_d16_bug, + .image_insts, .image_store_d16_bug, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount16, - .volcanic_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, + .trig_reduced_range, + .unaligned_buffer_access, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, .xnack_on_off_modes, }), }; @@ -3882,80 +5792,301 @@ pub const cpu = struct { .name = "gfx900", .llvm_name = "gfx900", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_scratch_insts, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, .gds, + .gfx7_gfx8_gfx9_insts, .gfx9, + .gws, .image_gather4_d16_bug, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, .mad_mix_insts, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx902: CpuModel = .{ .name = "gfx902", .llvm_name = "gfx902", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_scratch_insts, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, .gds, + .gfx7_gfx8_gfx9_insts, .gfx9, + .gws, .image_gather4_d16_bug, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, .mad_mix_insts, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx904: CpuModel = .{ .name = "gfx904", .llvm_name = "gfx904", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_scratch_insts, .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, .gds, + .gfx7_gfx8_gfx9_insts, .gfx9, + .gws, .image_gather4_d16_bug, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx906: CpuModel = .{ .name = "gfx906", .llvm_name = "gfx906", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, .dot2_insts, .dot7_insts, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_scratch_insts, .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, .gds, + .gfx7_gfx8_gfx9_insts, .gfx9, + .gws, .half_rate_64_ops, .image_gather4_d16_bug, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .sramecc_support, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx908: CpuModel = .{ .name = "gfx908", .llvm_name = "gfx908", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, .atomic_buffer_global_pk_add_f16_no_rtn_insts, .atomic_fadd_no_rtn_insts, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -3965,49 +6096,154 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_inst_offsets, + .flat_scratch_insts, .fma_mix_insts, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, .gds, + .gfx7_gfx8_gfx9_insts, .gfx9, + .gws, .half_rate_64_ops, .image_gather4_d16_bug, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, .mai_insts, .mfma_inline_literal_bug, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, .pk_fmac_f16_inst, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .sramecc_support, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx909: CpuModel = .{ .name = "gfx909", .llvm_name = "gfx909", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_scratch_insts, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, .gds, + .gfx7_gfx8_gfx9_insts, .gfx9, + .gws, .image_gather4_d16_bug, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, .mad_mix_insts, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx90a: CpuModel = .{ .name = "gfx90a", .llvm_name = "gfx90a", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, .atomic_buffer_global_pk_add_f16_insts, .atomic_fadd_no_rtn_insts, .atomic_fadd_rtn_insts, .atomic_fmin_fmax_flat_f64, .atomic_fmin_fmax_global_f64, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -4017,48 +6253,147 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, + .dpp, .dpp_64bit, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .dx10_clamp_and_ieee_mode, + .fast_denormal_f32, + .fast_fmaf, .flat_buffer_global_fadd_f64_inst, + .flat_inst_offsets, + .flat_scratch_insts, .fma_mix_insts, .fmacf64_inst, + .formatted_mubuf_insts, + .fp64, .full_rate_64_ops, - .gfx9, - .gfx90a_insts, + .gcn3_encoding, + .gfx7_gfx8_gfx9_insts, + .gfx9_0a, + .gws, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .kernarg_preload, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, .mai_insts, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, .packed_fp32_ops, .packed_tid, .pk_fmac_f16_inst, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .sramecc_support, .tgsplit_support, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .vgpr_align2, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx90c: CpuModel = .{ .name = "gfx90c", .llvm_name = "gfx90c", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_scratch_insts, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, .gds, + .gfx7_gfx8_gfx9_insts, .gfx9, + .gws, .image_gather4_d16_bug, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, .mad_mix_insts, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx942: CpuModel = .{ .name = "gfx942", .llvm_name = "gfx942", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .atomic_buffer_global_pk_add_f16_insts, .atomic_ds_pk_add_16_insts, @@ -4069,7 +6404,12 @@ pub const cpu = struct { .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .back_off_barrier, + .cube_insts, .cvt_fp8_vop1_bug, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -4079,37 +6419,82 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, + .dpp, .dpp_64bit, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .dx10_clamp_and_ieee_mode, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, .flat_buffer_global_fadd_f64_inst, + .flat_inst_offsets, + .flat_scratch_insts, .fma_mix_insts, .fmacf64_inst, + .formatted_mubuf_insts, + .fp64, .fp8_insts, .full_rate_64_ops, - .gfx9, - .gfx90a_insts, - .gfx940_insts, + .gcn3_encoding, + .gfx7_gfx8_gfx9_insts, + .gfx9_4, + .gws, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .kernarg_preload, .ldsbankcount32, + .lerp_inst, .lshl_add_u64_inst, .mai_insts, .memory_atomic_fadd_f32_denormal_support, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, .packed_fp32_ops, .packed_tid, .pk_fmac_f16_inst, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .sramecc_support, .tgsplit_support, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .v_mov_b64_inst, .vgpr_align2, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, .xf32_insts, + .xnack_on_off_modes, }), }; pub const gfx950: CpuModel = .{ .name = "gfx950", .llvm_name = "gfx950", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize163840, .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .atomic_buffer_global_pk_add_f16_insts, .atomic_buffer_pk_add_bf16_inst, @@ -4123,6 +6508,11 @@ pub const cpu = struct { .back_off_barrier, .bf16_cvt_insts, .bitop3_insts, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot12_insts, @@ -4134,39 +6524,83 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, + .dpp, .dpp_64bit, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .dx10_clamp_and_ieee_mode, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, .flat_buffer_global_fadd_f64_inst, + .flat_inst_offsets, + .flat_scratch_insts, .fma_mix_insts, .fmacf64_inst, + .formatted_mubuf_insts, + .fp64, .fp8_conversion_insts, .fp8_insts, .full_rate_64_ops, - .gfx9, - .gfx90a_insts, - .gfx940_insts, - .gfx950_insts, + .gcn3_encoding, + .gfx7_gfx8_gfx9_insts, + .gfx9_5, + .gws, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .kernarg_preload, .ldsbankcount32, + .lerp_inst, .lshl_add_u64_inst, .mai_insts, .memory_atomic_fadd_f32_denormal_support, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, .packed_fp32_ops, .packed_tid, .pk_fmac_f16_inst, .prng_inst, + .qsad_insts, + .r128_a16, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .sramecc_support, .tgsplit_support, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .v_mov_b64_inst, .vgpr_align2, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx9_4_generic: CpuModel = .{ .name = "gfx9_4_generic", .llvm_name = "gfx9-4-generic", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, .agent_scope_fine_grained_remote_memory_atomics, + .aperture_regs, .architected_flat_scratch, .atomic_buffer_global_pk_add_f16_insts, .atomic_ds_pk_add_16_insts, @@ -4177,6 +6611,11 @@ pub const cpu = struct { .atomic_fmin_fmax_global_f64, .atomic_global_pk_add_bf16_inst, .back_off_barrier, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, .dl_insts, .dot10_insts, .dot1_insts, @@ -4186,137 +6625,620 @@ pub const cpu = struct { .dot5_insts, .dot6_insts, .dot7_insts, + .dpp, .dpp_64bit, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .dx10_clamp_and_ieee_mode, + .fast_denormal_f32, + .fast_fmaf, .flat_atomic_fadd_f32_inst, .flat_buffer_global_fadd_f64_inst, + .flat_inst_offsets, + .flat_scratch_insts, .fma_mix_insts, .fmacf64_inst, + .formatted_mubuf_insts, + .fp64, .full_rate_64_ops, - .gfx9, - .gfx90a_insts, - .gfx940_insts, + .gcn3_encoding, + .gfx7_gfx8_gfx9_insts, + .gfx9_4, + .gws, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .kernarg_preload, .ldsbankcount32, + .lerp_inst, .lshl_add_u64_inst, .mai_insts, .memory_atomic_fadd_f32_denormal_support, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, .packed_fp32_ops, .packed_tid, .pk_fmac_f16_inst, + .qsad_insts, + .r128_a16, .requires_cov6, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, .sramecc_support, .tgsplit_support, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, .v_mov_b64_inst, .vgpr_align2, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const gfx9_generic: CpuModel = .{ .name = "gfx9_generic", .llvm_name = "gfx9-generic", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .a16, + .add_no_carry_insts, .addressablelocalmemorysize65536, + .aperture_regs, + .cube_insts, + .cvt_norm_insts, + .cvt_pknorm_vop2_insts, + .cvt_pknorm_vop3_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, .ds_src2_insts, + .dx10_clamp_and_ieee_mode, .extended_image_insts, + .fast_denormal_f32, + .fast_fmaf, + .flat_global_insts, + .flat_inst_offsets, + .flat_scratch_insts, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, .gds, + .gfx7_gfx8_gfx9_insts, .gfx9, + .gws, .image_gather4_d16_bug, .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, .mad_mac_f32_insts, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .negative_scratch_offset_bug, + .qsad_insts, + .r128_a16, .requires_cov6, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_atomics, + .scalar_flat_scratch_insts, + .scalar_stores, + .sdwa, + .sdwa_omod, + .sdwa_scalar, + .sdwa_sdst, + .unaligned_buffer_access, + .unaligned_ds_access, + .unaligned_scratch_access, + .vgpr_index_mode, + .vmem_to_lds_load_insts, + .vmem_write_vgpr_in_order, + .vop3p, + .wavefrontsize64, + .xnack_on_off_modes, }), }; pub const hainan: CpuModel = .{ .name = "hainan", .llvm_name = "hainan", .features = featureSet(&[_]Feature{ - .southern_islands, + .addressablelocalmemorysize32768, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gws, + .image_insts, + .instcachelinesize64, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const hawaii: CpuModel = .{ .name = "hawaii", .llvm_name = "hawaii", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, .fast_fmaf, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, .half_rate_64_ops, + .image_insts, + .instcachelinesize64, .ldsbankcount32, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const iceland: CpuModel = .{ .name = "iceland", .llvm_name = "iceland", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, .sgpr_init_bug, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const kabini: CpuModel = .{ .name = "kabini", .llvm_name = "kabini", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount16, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const kaveri: CpuModel = .{ .name = "kaveri", .llvm_name = "kaveri", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount32, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const mullins: CpuModel = .{ .name = "mullins", .llvm_name = "mullins", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize65536, + .atomic_fmin_fmax_flat_f32, + .atomic_fmin_fmax_flat_f64, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gfx7, + .gfx7_gfx8_gfx9_insts, + .gws, + .image_insts, + .instcachelinesize64, .ldsbankcount16, - .sea_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .unaligned_buffer_access, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const oland: CpuModel = .{ .name = "oland", .llvm_name = "oland", .features = featureSet(&[_]Feature{ - .southern_islands, + .addressablelocalmemorysize32768, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gws, + .image_insts, + .instcachelinesize64, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const pitcairn: CpuModel = .{ .name = "pitcairn", .llvm_name = "pitcairn", .features = featureSet(&[_]Feature{ - .southern_islands, + .addressablelocalmemorysize32768, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gws, + .image_insts, + .instcachelinesize64, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const polaris10: CpuModel = .{ .name = "polaris10", .llvm_name = "polaris10", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const polaris11: CpuModel = .{ .name = "polaris11", .llvm_name = "polaris11", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const stoney: CpuModel = .{ .name = "stoney", .llvm_name = "stoney", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, .image_gather4_d16_bug, + .image_insts, .image_store_d16_bug, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount16, - .volcanic_islands, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, + .trig_reduced_range, + .unaligned_buffer_access, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, .xnack_on_off_modes, }), }; @@ -4324,36 +7246,178 @@ pub const cpu = struct { .name = "tahiti", .llvm_name = "tahiti", .features = featureSet(&[_]Feature{ + .addressablelocalmemorysize32768, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, .fast_fmaf, + .formatted_mubuf_insts, + .fp64, + .gds, + .gws, .half_rate_64_ops, - .southern_islands, + .image_insts, + .instcachelinesize64, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const tonga: CpuModel = .{ .name = "tonga", .llvm_name = "tonga", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, .sgpr_init_bug, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const tongapro: CpuModel = .{ .name = "tongapro", .llvm_name = "tongapro", .features = featureSet(&[_]Feature{ + .@"16_bit_insts", + .addressablelocalmemorysize65536, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .dpp, + .dpp_row_bcast, + .dpp_wavefront_shifts, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .fast_denormal_f32, + .flat_address_space, + .formatted_mubuf_insts, + .fp64, + .gcn3_encoding, + .gds, + .gfx7_gfx8_gfx9_insts, + .gfx8, + .gws, + .image_insts, + .instcachelinesize64, + .int_clamp_insts, + .inv_2pi_inline_imm, .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_insts, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .qsad_insts, + .s_memrealtime, + .s_memtime_inst, + .sad_insts, + .scalar_stores, + .sdwa, + .sdwa_mav, + .sdwa_out_mods_vopc, .sgpr_init_bug, + .trig_reduced_range, + .unaligned_buffer_access, .unpacked_d16_vmem, - .volcanic_islands, + .vgpr_index_mode, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; pub const verde: CpuModel = .{ .name = "verde", .llvm_name = "verde", .features = featureSet(&[_]Feature{ - .southern_islands, + .addressablelocalmemorysize32768, + .atomic_fmin_fmax_global_f32, + .atomic_fmin_fmax_global_f64, + .cube_insts, + .cvt_pknorm_vop2_insts, + .default_component_zero, + .ds_src2_insts, + .dx10_clamp_and_ieee_mode, + .extended_image_insts, + .formatted_mubuf_insts, + .fp64, + .gds, + .gws, + .image_insts, + .instcachelinesize64, + .ldsbankcount32, + .lerp_inst, + .mad_mac_f32_insts, + .mimg_r128, + .movrel, + .mqsad_pk_insts, + .msad_insts, + .mtbuf_insts, + .s_memtime_inst, + .sad_insts, + .trig_reduced_range, + .vmem_write_vgpr_in_order, + .wavefrontsize64, }), }; }; diff --git a/lib/std/Target/arc.zig b/lib/std/Target/arc.zig index ac48a10ffe..c6ce2ab0f3 100644 --- a/lib/std/Target/arc.zig +++ b/lib/std/Target/arc.zig @@ -31,8 +31,8 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", + pub const arcv2: CpuModel = .{ + .name = "arcv2", .llvm_name = "generic", .features = featureSet(&[_]Feature{}), }; diff --git a/lib/std/Target/arm.zig b/lib/std/Target/arm.zig index 9d7810b7db..44e04594ca 100644 --- a/lib/std/Target/arm.zig +++ b/lib/std/Target/arm.zig @@ -5,9 +5,7 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { - @"32bit", @"8msecext", - aapcs_frame_chain, aclass, acquire_release, aes, @@ -16,7 +14,6 @@ pub const Feature = enum { avoid_muls, avoid_partial_cpsr, bf16, - big_endian_instructions, branch_align_64, cde, cdecp0, @@ -29,17 +26,14 @@ pub const Feature = enum { cdecp7, cheap_predicable_cpsr, clrbhb, - cortex_a510, crc, crypto, d32, db, dfb, - disable_postra_scheduler, dont_widen_vmovs, dotprod, dsp, - execute_only, expand_fp_mlx, fix_cmse_cve_2021_35465, fix_cortex_a57_aes_1742098, @@ -57,9 +51,6 @@ pub const Feature = enum { fullfp16, fuse_aes, fuse_literals, - harden_sls_blr, - harden_sls_nocomdat, - harden_sls_retbr, has_v4t, has_v5t, has_v5te, @@ -96,10 +87,7 @@ pub const Feature = enum { iwmmxt, iwmmxt2, lob, - long_calls, loop_align, - m55, - m85, mclass, mp, muxed_units, @@ -112,9 +100,7 @@ pub const Feature = enum { neon_fpmovs, neonfp, no_branch_predictor, - no_bti_at_return_twice, - no_movt, - no_neg_immediates, + no_unaligned_access, noarm, nonpipelined_vfp, pacbti, @@ -124,10 +110,6 @@ pub const Feature = enum { prof_unpr, ras, rclass, - read_tp_tpidrprw, - read_tp_tpidruro, - read_tp_tpidrurw, - reserve_r9, ret_addr_stack, sb, sha2, @@ -138,14 +120,9 @@ pub const Feature = enum { slow_vgetlni32, slowfpvfmx, slowfpvmlx, - soft_float, splat_vfp_neon, - strict_align, thumb2, - thumb_mode, trustzone, - use_mipipeliner, - use_misched, v2, v2a, v3, @@ -218,21 +195,11 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; - result[@backingInt(Feature.@"32bit")] = .{ - .llvm_name = "32bit", - .description = "Prefer 32-bit Thumb instrs", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.@"8msecext")] = .{ .llvm_name = "8msecext", .description = "Enable support for ARMv8-M Security Extensions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.aapcs_frame_chain)] = .{ - .llvm_name = "aapcs-frame-chain", - .description = "Create an AAPCS compliant frame chain", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.aclass)] = .{ .llvm_name = "aclass", .description = "Is application profile ('A' series)", @@ -277,11 +244,6 @@ pub const all_features = blk: { .neon, }), }; - result[@backingInt(Feature.big_endian_instructions)] = .{ - .llvm_name = "big-endian-instructions", - .description = "Expect instructions to be stored big-endian.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.branch_align_64)] = .{ .llvm_name = "branch-align-64", .description = "Prefer 64-bit alignment for branch targets", @@ -360,11 +322,6 @@ pub const all_features = blk: { .description = "Enable Clear BHB instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.cortex_a510)] = .{ - .llvm_name = "cortex-a510", - .description = "Cortex-A510 ARM processors", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.crc)] = .{ .llvm_name = "crc", .description = "Enable support for CRC instructions", @@ -393,11 +350,6 @@ pub const all_features = blk: { .description = "Has full data barrier (dfb) instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.disable_postra_scheduler)] = .{ - .llvm_name = "disable-postra-scheduler", - .description = "Don't schedule again after register allocation", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.dont_widen_vmovs)] = .{ .llvm_name = "dont-widen-vmovs", .description = "Don't widen VMOVS to VMOVD", @@ -415,11 +367,6 @@ pub const all_features = blk: { .description = "Supports DSP instructions in ARM and/or Thumb2", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.execute_only)] = .{ - .llvm_name = "execute-only", - .description = "Enable the generation of execute only code.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.expand_fp_mlx)] = .{ .llvm_name = "expand-fp-mlx", .description = "Expand VFP/NEON MLA/MLS instructions", @@ -528,21 +475,6 @@ pub const all_features = blk: { .description = "CPU fuses literal generation operations", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.harden_sls_blr)] = .{ - .llvm_name = "harden-sls-blr", - .description = "Harden against straight line speculation across indirect calls", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.harden_sls_nocomdat)] = .{ - .llvm_name = "harden-sls-nocomdat", - .description = "Generate thunk code for SLS mitigation in the normal text section", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.harden_sls_retbr)] = .{ - .llvm_name = "harden-sls-retbr", - .description = "Harden against straight line speculation across RETurn and BranchRegister instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.has_v4t)] = .{ .llvm_name = "v4t", .description = "Support ARM v4T instructions", @@ -799,26 +731,11 @@ pub const all_features = blk: { .description = "Enable Low Overhead Branch extensions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.long_calls)] = .{ - .llvm_name = "long-calls", - .description = "Generate calls via indirect call instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.loop_align)] = .{ .llvm_name = "loop-align", .description = "Prefer 32-bit alignment for branch targets", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.m55)] = .{ - .llvm_name = "m55", - .description = "Cortex-M55 ARM processors", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.m85)] = .{ - .llvm_name = "m85", - .description = "Cortex-M85 ARM processors", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.mclass)] = .{ .llvm_name = "mclass", .description = "Is microcontroller profile ('M' series)", @@ -889,19 +806,9 @@ pub const all_features = blk: { .description = "Has no branch predictor", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.no_bti_at_return_twice)] = .{ - .llvm_name = "no-bti-at-return-twice", - .description = "Don't place a BTI instruction after a return-twice", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.no_movt)] = .{ - .llvm_name = "no-movt", - .description = "Don't use movt/movw pairs for 32-bit imms", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.no_neg_immediates)] = .{ - .llvm_name = "no-neg-immediates", - .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", + result[@backingInt(Feature.no_unaligned_access)] = .{ + .llvm_name = "strict-align", + .description = "Disallow all unaligned memory access", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.noarm)] = .{ @@ -949,26 +856,6 @@ pub const all_features = blk: { .description = "Is realtime profile ('R' series)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.read_tp_tpidrprw)] = .{ - .llvm_name = "read-tp-tpidrprw", - .description = "Reading thread pointer from TPIDRPRW register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.read_tp_tpidruro)] = .{ - .llvm_name = "read-tp-tpidruro", - .description = "Reading thread pointer from TPIDRURO register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.read_tp_tpidrurw)] = .{ - .llvm_name = "read-tp-tpidrurw", - .description = "Reading thread pointer from TPIDRURW register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r9)] = .{ - .llvm_name = "reserve-r9", - .description = "Reserve R9, making it unavailable as GPR", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.ret_addr_stack)] = .{ .llvm_name = "ret-addr-stack", .description = "Has return address stack", @@ -1021,11 +908,6 @@ pub const all_features = blk: { .description = "Disable VFP / NEON MAC instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.soft_float)] = .{ - .llvm_name = "soft-float", - .description = "Use software floating point features.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.splat_vfp_neon)] = .{ .llvm_name = "splat-vfp-neon", .description = "Splat register from VFP to NEON", @@ -1033,69 +915,49 @@ pub const all_features = blk: { .dont_widen_vmovs, }), }; - result[@backingInt(Feature.strict_align)] = .{ - .llvm_name = "strict-align", - .description = "Disallow all unaligned memory access", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.thumb2)] = .{ .llvm_name = "thumb2", .description = "Enable Thumb2 instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.thumb_mode)] = .{ - .llvm_name = "thumb-mode", - .description = "Thumb mode", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.trustzone)] = .{ .llvm_name = "trustzone", .description = "Enable support for TrustZone security extensions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.use_mipipeliner)] = .{ - .llvm_name = "use-mipipeliner", - .description = "Use the MachinePipeliner", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.use_misched)] = .{ - .llvm_name = "use-misched", - .description = "Use the MachineScheduler", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.v2)] = .{ .llvm_name = null, .description = "ARMv2 architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v2a)] = .{ .llvm_name = null, .description = "ARMv2a architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v3)] = .{ .llvm_name = null, .description = "ARMv3 architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v3m)] = .{ .llvm_name = null, .description = "ARMv3m architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v4)] = .{ .llvm_name = "armv4", .description = "ARMv4 architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v4t)] = .{ @@ -1103,7 +965,7 @@ pub const all_features = blk: { .description = "ARMv4t architecture", .dependencies = featureSet(&[_]Feature{ .has_v4t, - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v5t)] = .{ @@ -1111,7 +973,7 @@ pub const all_features = blk: { .description = "ARMv5t architecture", .dependencies = featureSet(&[_]Feature{ .has_v5t, - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v5te)] = .{ @@ -1119,7 +981,7 @@ pub const all_features = blk: { .description = "ARMv5te architecture", .dependencies = featureSet(&[_]Feature{ .has_v5te, - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v5tej)] = .{ @@ -1127,7 +989,7 @@ pub const all_features = blk: { .description = "ARMv5tej architecture", .dependencies = featureSet(&[_]Feature{ .has_v5te, - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v6)] = .{ @@ -1167,9 +1029,8 @@ pub const all_features = blk: { .db, .has_v6m, .mclass, + .no_unaligned_access, .noarm, - .strict_align, - .thumb_mode, }), }; result[@backingInt(Feature.v6sm)] = .{ @@ -1179,9 +1040,8 @@ pub const all_features = blk: { .db, .has_v6m, .mclass, + .no_unaligned_access, .noarm, - .strict_align, - .thumb_mode, }), }; result[@backingInt(Feature.v6t2)] = .{ @@ -1213,7 +1073,6 @@ pub const all_features = blk: { .hwdiv, .mclass, .noarm, - .thumb_mode, }), }; result[@backingInt(Feature.v7m)] = .{ @@ -1225,7 +1084,6 @@ pub const all_features = blk: { .hwdiv, .mclass, .noarm, - .thumb_mode, }), }; result[@backingInt(Feature.v7r)] = .{ @@ -1282,7 +1140,6 @@ pub const all_features = blk: { .mclass, .noarm, .ras, - .thumb_mode, }), }; result[@backingInt(Feature.v8_2a)] = .{ @@ -1441,9 +1298,8 @@ pub const all_features = blk: { .has_v8m, .hwdiv, .mclass, + .no_unaligned_access, .noarm, - .strict_align, - .thumb_mode, }), }; result[@backingInt(Feature.v8m_main)] = .{ @@ -1456,7 +1312,6 @@ pub const all_features = blk: { .hwdiv, .mclass, .noarm, - .thumb_mode, }), }; result[@backingInt(Feature.v8r)] = .{ @@ -2211,7 +2066,6 @@ pub const cpu = struct { .llvm_name = "cortex-m23", .features = featureSet(&[_]Feature{ .no_branch_predictor, - .no_movt, .v8m, }), }; @@ -2221,7 +2075,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .loop_align, .no_branch_predictor, - .use_misched, .v7m, }), }; @@ -2235,7 +2088,6 @@ pub const cpu = struct { .no_branch_predictor, .slowfpvfmx, .slowfpvmlx, - .use_misched, .v8m_main, }), }; @@ -2248,7 +2100,6 @@ pub const cpu = struct { .no_branch_predictor, .slowfpvfmx, .slowfpvmlx, - .use_misched, .v8m_main, }), }; @@ -2260,7 +2111,6 @@ pub const cpu = struct { .no_branch_predictor, .slowfpvfmx, .slowfpvmlx, - .use_misched, .v7em, }), }; @@ -2273,7 +2123,6 @@ pub const cpu = struct { .mve1beat, .no_branch_predictor, .slowfpvmlx, - .use_misched, .v8_1m_main, }), }; @@ -2284,10 +2133,8 @@ pub const cpu = struct { .dsp, .fix_cmse_cve_2021_35465, .loop_align, - .m55, .no_branch_predictor, .slowfpvmlx, - .use_misched, .v8_1m_main, }), }; @@ -2296,8 +2143,6 @@ pub const cpu = struct { .llvm_name = "cortex-m7", .features = featureSet(&[_]Feature{ .branch_align_64, - .use_mipipeliner, - .use_misched, .v7em, }), }; @@ -2308,8 +2153,6 @@ pub const cpu = struct { .@"8msecext", .branch_align_64, .dsp, - .m85, - .use_misched, .v8_1m_main, }), }; @@ -2353,7 +2196,6 @@ pub const cpu = struct { .llvm_name = "cortex-r52", .features = featureSet(&[_]Feature{ .fpao, - .use_misched, .v8r, }), }; @@ -2362,7 +2204,6 @@ pub const cpu = struct { .llvm_name = "cortex-r52plus", .features = featureSet(&[_]Feature{ .fpao, - .use_misched, .v8r, }), }; @@ -2419,12 +2260,10 @@ pub const cpu = struct { .avoid_movs_shop, .avoid_partial_cpsr, .crypto, - .disable_postra_scheduler, .neonfp, .ret_addr_stack, .slowfpvfmx, .slowfpvmlx, - .use_misched, .v8a, .zcz, }), @@ -2438,7 +2277,7 @@ pub const cpu = struct { }; pub const exynos_m1: CpuModel = .{ .name = "exynos_m1", - .llvm_name = null, + .llvm_name = "generic", .features = featureSet(&[_]Feature{ .crypto, .expand_fp_mlx, @@ -2459,7 +2298,7 @@ pub const cpu = struct { }; pub const exynos_m2: CpuModel = .{ .name = "exynos_m2", - .llvm_name = null, + .llvm_name = "generic", .features = featureSet(&[_]Feature{ .crypto, .expand_fp_mlx, @@ -2658,7 +2497,6 @@ pub const cpu = struct { .llvm_name = "sc300", .features = featureSet(&[_]Feature{ .no_branch_predictor, - .use_misched, .v7m, }), }; @@ -2672,7 +2510,6 @@ pub const cpu = struct { .no_branch_predictor, .slowfpvfmx, .slowfpvmlx, - .use_misched, .v8m_main, }), }; @@ -2685,7 +2522,6 @@ pub const cpu = struct { .mve1beat, .no_branch_predictor, .slowfpvmlx, - .use_misched, .v8_1m_main, }), }; @@ -2723,7 +2559,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .avoid_movs_shop, .avoid_partial_cpsr, - .disable_postra_scheduler, .hwdiv, .hwdiv_arm, .mp, @@ -2738,7 +2573,6 @@ pub const cpu = struct { .slow_vgetlni32, .slowfpvfmx, .slowfpvmlx, - .use_misched, .v7a, .vfp4, .vmlx_hazards, diff --git a/lib/std/Target/avr.zig b/lib/std/Target/avr.zig index 0d0f1e9109..5a13013b3b 100644 --- a/lib/std/Target/avr.zig +++ b/lib/std/Target/avr.zig @@ -33,7 +33,6 @@ pub const Feature = enum { mul, rmw, smallstack, - special, spm, spmx, sram, @@ -249,29 +248,6 @@ pub const all_features = blk: { .description = "The device has an 8-bit stack pointer", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.special)] = .{ - .llvm_name = "special", - .description = "Enable use of the entire instruction set - used for debugging", - .dependencies = featureSet(&[_]Feature{ - .addsubiw, - .@"break", - .des, - .eijmpcall, - .elpm, - .elpmx, - .ijmpcall, - .jmpcall, - .lpm, - .lpmx, - .memmappedregs, - .movw, - .mul, - .rmw, - .spm, - .spmx, - .sram, - }), - }; result[@backingInt(Feature.spm)] = .{ .llvm_name = "spm", .description = "The device supports the `SPM` instruction", diff --git a/lib/std/Target/bpf.zig b/lib/std/Target/bpf.zig index 9251304a31..a8bb9abfb3 100644 --- a/lib/std/Target/bpf.zig +++ b/lib/std/Target/bpf.zig @@ -5,8 +5,8 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { - allows_misaligned_mem_access, alu32, + unaligned_access, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -18,16 +18,16 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; - result[@backingInt(Feature.allows_misaligned_mem_access)] = .{ - .llvm_name = "allows-misaligned-mem-access", - .description = "Allows misaligned memory access", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.alu32)] = .{ .llvm_name = "alu32", .description = "Enable ALU32 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.unaligned_access)] = .{ + .llvm_name = "allows-misaligned-mem-access", + .description = "Allows misaligned memory access", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { elem.index = i; @@ -37,16 +37,6 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{}), - }; - pub const probe: CpuModel = .{ - .name = "probe", - .llvm_name = "probe", - .features = featureSet(&[_]Feature{}), - }; pub const v1: CpuModel = .{ .name = "v1", .llvm_name = "v1", diff --git a/lib/std/Target/csky.zig b/lib/std/Target/csky.zig index 5057078878..21a5f04fd6 100644 --- a/lib/std/Target/csky.zig +++ b/lib/std/Target/csky.zig @@ -35,17 +35,12 @@ pub const Feature = enum { fpuv3_hf, fpuv3_hi, fpuv3_sf, - hard_float, - hard_float_abi, - hard_tp, high_registers, hwdiv, istack, java, mp, mp1e2, - soft_tp, - stack_size, trust, vdsp2e3, vdsp2e60f, @@ -229,21 +224,6 @@ pub const all_features = blk: { .description = "Enable FPUv3 single float instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.hard_float)] = .{ - .llvm_name = "hard-float", - .description = "Use hard floating point features", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.hard_float_abi)] = .{ - .llvm_name = "hard-float-abi", - .description = "Use hard floating point ABI to pass args", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.hard_tp)] = .{ - .llvm_name = "hard-tp", - .description = "Enable TLS Pointer register", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.high_registers)] = .{ .llvm_name = "high-registers", .description = "Enable r16-r31 registers", @@ -278,16 +258,6 @@ pub const all_features = blk: { .@"3e7", }), }; - result[@backingInt(Feature.soft_tp)] = .{ - .llvm_name = "soft-tp", - .description = "Disable TLS Pointer register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.stack_size)] = .{ - .llvm_name = "stack-size", - .description = "Output stack size information", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.trust)] = .{ .llvm_name = "trust", .description = "Enable trust instructions", @@ -330,7 +300,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -353,7 +322,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -375,7 +343,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -397,7 +364,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -419,7 +385,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -442,7 +407,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -466,7 +430,6 @@ pub const cpu = struct { .fpuv3_hf, .fpuv3_hi, .fpuv3_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -489,7 +452,6 @@ pub const cpu = struct { .fpuv3_hf, .fpuv3_hi, .fpuv3_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2014,7 +1976,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2030,7 +1991,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2053,7 +2013,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2076,7 +2035,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2093,7 +2051,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2110,7 +2067,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2132,7 +2088,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2154,7 +2109,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2176,7 +2130,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2199,7 +2152,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2217,7 +2169,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2234,7 +2185,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2252,7 +2202,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2275,7 +2224,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2297,7 +2245,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2319,7 +2266,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2342,7 +2288,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2360,7 +2305,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2377,7 +2321,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2395,7 +2338,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2414,7 +2356,6 @@ pub const cpu = struct { .btst16, .cache, .dspe60, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2437,7 +2378,6 @@ pub const cpu = struct { .fpuv3_hf, .fpuv3_hi, .fpuv3_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2460,7 +2400,6 @@ pub const cpu = struct { .fpuv3_hf, .fpuv3_hi, .fpuv3_sf, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2480,7 +2419,6 @@ pub const cpu = struct { .btst16, .cache, .dspe60, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2490,6 +2428,13 @@ pub const cpu = struct { .vdspv2, }), }; + pub const e2: CpuModel = .{ + .name = "e2", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .e2, + }), + }; pub const e801: CpuModel = .{ .name = "e801", .llvm_name = "e801", @@ -2633,13 +2578,6 @@ pub const cpu = struct { .trust, }), }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{ - .btst16, - }), - }; pub const @"i805": CpuModel = .{ .name = "i805", .llvm_name = "i805", @@ -2681,7 +2619,6 @@ pub const cpu = struct { .dsp1e2, .dspe60, .edsp, - .hard_tp, .high_registers, .hwdiv, .mp, @@ -2704,7 +2641,6 @@ pub const cpu = struct { .floate1, .fpuv2_df, .fpuv2_sf, - .hard_tp, .high_registers, .hwdiv, .mp, diff --git a/lib/std/Target/hexagon.zig b/lib/std/Target/hexagon.zig index 14e1d7725e..0e0dc7fe04 100644 --- a/lib/std/Target/hexagon.zig +++ b/lib/std/Target/hexagon.zig @@ -7,8 +7,6 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { audio, cabac, - compound, - duplex, hvx, hvx_ieee_fp, hvx_length128b, @@ -26,50 +24,8 @@ pub const Feature = enum { hvxv75, hvxv79, hvxv81, - long_calls, mem_noshuf, - memops, - noreturn_stack_elim, - nvj, - nvs, - packets, prev65, - reserved_r10, - reserved_r11, - reserved_r12, - reserved_r13, - reserved_r14, - reserved_r15, - reserved_r16, - reserved_r17, - reserved_r18, - reserved_r19, - reserved_r20, - reserved_r21, - reserved_r22, - reserved_r23, - reserved_r24, - reserved_r25, - reserved_r26, - reserved_r27, - reserved_r28, - reserved_r6, - reserved_r7, - reserved_r8, - reserved_r9, - scs_reg_r16, - scs_reg_r17, - scs_reg_r18, - scs_reg_r19, - scs_reg_r20, - scs_reg_r21, - scs_reg_r22, - scs_reg_r23, - scs_reg_r24, - scs_reg_r25, - scs_reg_r26, - scs_reg_r27, - small_data, tinycore, v5, v55, @@ -107,16 +63,6 @@ pub const all_features = blk: { .description = "Emit the CABAC instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.compound)] = .{ - .llvm_name = "compound", - .description = "Use compound instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.duplex)] = .{ - .llvm_name = "duplex", - .description = "Enable generation of duplex instruction", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.hvx)] = .{ .llvm_name = "hvx", .description = "Hexagon HVX instructions", @@ -125,7 +71,9 @@ pub const all_features = blk: { result[@backingInt(Feature.hvx_ieee_fp)] = .{ .llvm_name = "hvx-ieee-fp", .description = "Hexagon HVX IEEE floating point instructions", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .hvxv68, + }), }; result[@backingInt(Feature.hvx_length128b)] = .{ .llvm_name = "hvx-length128b", @@ -144,7 +92,9 @@ pub const all_features = blk: { result[@backingInt(Feature.hvx_qfloat)] = .{ .llvm_name = "hvx-qfloat", .description = "Hexagon HVX QFloating point instructions", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .hvxv68, + }), }; result[@backingInt(Feature.hvxv60)] = .{ .llvm_name = "hvxv60", @@ -231,230 +181,16 @@ pub const all_features = blk: { .hvxv79, }), }; - result[@backingInt(Feature.long_calls)] = .{ - .llvm_name = "long-calls", - .description = "Use constant-extended calls", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.mem_noshuf)] = .{ .llvm_name = "mem_noshuf", .description = "Supports mem_noshuf feature", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.memops)] = .{ - .llvm_name = "memops", - .description = "Use memop instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.noreturn_stack_elim)] = .{ - .llvm_name = "noreturn-stack-elim", - .description = "Eliminate stack allocation in a noreturn function when possible", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.nvj)] = .{ - .llvm_name = "nvj", - .description = "Support for new-value jumps", - .dependencies = featureSet(&[_]Feature{ - .packets, - }), - }; - result[@backingInt(Feature.nvs)] = .{ - .llvm_name = "nvs", - .description = "Support for new-value stores", - .dependencies = featureSet(&[_]Feature{ - .packets, - }), - }; - result[@backingInt(Feature.packets)] = .{ - .llvm_name = "packets", - .description = "Support for instruction packets", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.prev65)] = .{ .llvm_name = "prev65", .description = "Support features deprecated in v65", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.reserved_r10)] = .{ - .llvm_name = "reserved-r10", - .description = "Reserve register R10", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r11)] = .{ - .llvm_name = "reserved-r11", - .description = "Reserve register R11", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r12)] = .{ - .llvm_name = "reserved-r12", - .description = "Reserve register R12", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r13)] = .{ - .llvm_name = "reserved-r13", - .description = "Reserve register R13", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r14)] = .{ - .llvm_name = "reserved-r14", - .description = "Reserve register R14", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r15)] = .{ - .llvm_name = "reserved-r15", - .description = "Reserve register R15", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r16)] = .{ - .llvm_name = "reserved-r16", - .description = "Reserve register R16", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r17)] = .{ - .llvm_name = "reserved-r17", - .description = "Reserve register R17", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r18)] = .{ - .llvm_name = "reserved-r18", - .description = "Reserve register R18", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r19)] = .{ - .llvm_name = "reserved-r19", - .description = "Reserve register R19", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r20)] = .{ - .llvm_name = "reserved-r20", - .description = "Reserve register R20", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r21)] = .{ - .llvm_name = "reserved-r21", - .description = "Reserve register R21", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r22)] = .{ - .llvm_name = "reserved-r22", - .description = "Reserve register R22", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r23)] = .{ - .llvm_name = "reserved-r23", - .description = "Reserve register R23", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r24)] = .{ - .llvm_name = "reserved-r24", - .description = "Reserve register R24", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r25)] = .{ - .llvm_name = "reserved-r25", - .description = "Reserve register R25", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r26)] = .{ - .llvm_name = "reserved-r26", - .description = "Reserve register R26", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r27)] = .{ - .llvm_name = "reserved-r27", - .description = "Reserve register R27", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r28)] = .{ - .llvm_name = "reserved-r28", - .description = "Reserve register R28", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r6)] = .{ - .llvm_name = "reserved-r6", - .description = "Reserve register R6", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r7)] = .{ - .llvm_name = "reserved-r7", - .description = "Reserve register R7", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r8)] = .{ - .llvm_name = "reserved-r8", - .description = "Reserve register R8", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserved_r9)] = .{ - .llvm_name = "reserved-r9", - .description = "Reserve register R9", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r16)] = .{ - .llvm_name = "scs-reg-r16", - .description = "Use register R16 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r17)] = .{ - .llvm_name = "scs-reg-r17", - .description = "Use register R17 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r18)] = .{ - .llvm_name = "scs-reg-r18", - .description = "Use register R18 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r19)] = .{ - .llvm_name = "scs-reg-r19", - .description = "Use register R19 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r20)] = .{ - .llvm_name = "scs-reg-r20", - .description = "Use register R20 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r21)] = .{ - .llvm_name = "scs-reg-r21", - .description = "Use register R21 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r22)] = .{ - .llvm_name = "scs-reg-r22", - .description = "Use register R22 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r23)] = .{ - .llvm_name = "scs-reg-r23", - .description = "Use register R23 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r24)] = .{ - .llvm_name = "scs-reg-r24", - .description = "Use register R24 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r25)] = .{ - .llvm_name = "scs-reg-r25", - .description = "Use register R25 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r26)] = .{ - .llvm_name = "scs-reg-r26", - .description = "Use register R26 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.scs_reg_r27)] = .{ - .llvm_name = "scs-reg-r27", - .description = "Use register R27 as the shadow call stack pointer", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.small_data)] = .{ - .llvm_name = "small-data", - .description = "Allow GP-relative addressing of global variables", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.tinycore)] = .{ .llvm_name = "tinycore", .description = "Hexagon Tiny Core", @@ -468,67 +204,93 @@ pub const all_features = blk: { result[@backingInt(Feature.v55)] = .{ .llvm_name = "v55", .description = "Enable Hexagon V55 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v5, + }), }; result[@backingInt(Feature.v60)] = .{ .llvm_name = "v60", .description = "Enable Hexagon V60 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v55, + }), }; result[@backingInt(Feature.v62)] = .{ .llvm_name = "v62", .description = "Enable Hexagon V62 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v60, + }), }; result[@backingInt(Feature.v65)] = .{ .llvm_name = "v65", .description = "Enable Hexagon V65 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v62, + }), }; result[@backingInt(Feature.v66)] = .{ .llvm_name = "v66", .description = "Enable Hexagon V66 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v65, + }), }; result[@backingInt(Feature.v67)] = .{ .llvm_name = "v67", .description = "Enable Hexagon V67 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v66, + }), }; result[@backingInt(Feature.v68)] = .{ .llvm_name = "v68", .description = "Enable Hexagon V68 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v67, + }), }; result[@backingInt(Feature.v69)] = .{ .llvm_name = "v69", .description = "Enable Hexagon V69 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v68, + }), }; result[@backingInt(Feature.v71)] = .{ .llvm_name = "v71", .description = "Enable Hexagon V71 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v69, + }), }; result[@backingInt(Feature.v73)] = .{ .llvm_name = "v73", .description = "Enable Hexagon V73 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v71, + }), }; result[@backingInt(Feature.v75)] = .{ .llvm_name = "v75", .description = "Enable Hexagon V75 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v73, + }), }; result[@backingInt(Feature.v79)] = .{ .llvm_name = "v79", .description = "Enable Hexagon V79 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v75, + }), }; result[@backingInt(Feature.v81)] = .{ .llvm_name = "v81", .description = "Enable Hexagon V81 architecture", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .v79, + }), }; result[@backingInt(Feature.zreg)] = .{ .llvm_name = "zreg", @@ -544,35 +306,12 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{ - .cabac, - .compound, - .duplex, - .memops, - .nvj, - .nvs, - .prev65, - .small_data, - .v5, - .v55, - .v60, - }), - }; pub const hexagonv5: CpuModel = .{ .name = "hexagonv5", .llvm_name = "hexagonv5", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, - .memops, - .nvj, - .nvs, .prev65, - .small_data, .v5, }), }; @@ -581,14 +320,7 @@ pub const cpu = struct { .llvm_name = "hexagonv55", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, - .memops, - .nvj, - .nvs, .prev65, - .small_data, - .v5, .v55, }), }; @@ -597,15 +329,7 @@ pub const cpu = struct { .llvm_name = "hexagonv60", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, - .memops, - .nvj, - .nvs, .prev65, - .small_data, - .v5, - .v55, .v60, }), }; @@ -614,16 +338,7 @@ pub const cpu = struct { .llvm_name = "hexagonv62", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, - .memops, - .nvj, - .nvs, .prev65, - .small_data, - .v5, - .v55, - .v60, .v62, }), }; @@ -632,17 +347,7 @@ pub const cpu = struct { .llvm_name = "hexagonv65", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, .v65, }), }; @@ -651,18 +356,7 @@ pub const cpu = struct { .llvm_name = "hexagonv66", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, .v66, }), }; @@ -671,19 +365,7 @@ pub const cpu = struct { .llvm_name = "hexagonv67", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, .v67, }), }; @@ -692,18 +374,8 @@ pub const cpu = struct { .llvm_name = "hexagonv67t", .features = featureSet(&[_]Feature{ .audio, - .compound, .mem_noshuf, - .memops, - .nvs, - .small_data, .tinycore, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, .v67, }), }; @@ -712,20 +384,7 @@ pub const cpu = struct { .llvm_name = "hexagonv68", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, - .v67, .v68, }), }; @@ -734,21 +393,7 @@ pub const cpu = struct { .llvm_name = "hexagonv69", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, - .v67, - .v68, .v69, }), }; @@ -757,22 +402,7 @@ pub const cpu = struct { .llvm_name = "hexagonv71", .features = featureSet(&[_]Feature{ .cabac, - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, - .v67, - .v68, - .v69, .v71, }), }; @@ -781,21 +411,8 @@ pub const cpu = struct { .llvm_name = "hexagonv71t", .features = featureSet(&[_]Feature{ .audio, - .compound, .mem_noshuf, - .memops, - .nvs, - .small_data, .tinycore, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, - .v67, - .v68, - .v69, .v71, }), }; @@ -803,23 +420,7 @@ pub const cpu = struct { .name = "hexagonv73", .llvm_name = "hexagonv73", .features = featureSet(&[_]Feature{ - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, - .v67, - .v68, - .v69, - .v71, .v73, }), }; @@ -827,24 +428,7 @@ pub const cpu = struct { .name = "hexagonv75", .llvm_name = "hexagonv75", .features = featureSet(&[_]Feature{ - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, - .v67, - .v68, - .v69, - .v71, - .v73, .v75, }), }; @@ -852,25 +436,7 @@ pub const cpu = struct { .name = "hexagonv79", .llvm_name = "hexagonv79", .features = featureSet(&[_]Feature{ - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, - .v67, - .v68, - .v69, - .v71, - .v73, - .v75, .v79, }), }; @@ -878,26 +444,7 @@ pub const cpu = struct { .name = "hexagonv81", .llvm_name = "hexagonv81", .features = featureSet(&[_]Feature{ - .compound, - .duplex, .mem_noshuf, - .memops, - .nvj, - .nvs, - .small_data, - .v5, - .v55, - .v60, - .v62, - .v65, - .v66, - .v67, - .v68, - .v69, - .v71, - .v73, - .v75, - .v79, .v81, }), }; diff --git a/lib/std/Target/lanai.zig b/lib/std/Target/lanai.zig index 0ba921c539..42ab9811bb 100644 --- a/lib/std/Target/lanai.zig +++ b/lib/std/Target/lanai.zig @@ -24,11 +24,6 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{}), - }; pub const v11: CpuModel = .{ .name = "v11", .llvm_name = "v11", diff --git a/lib/std/Target/loongarch.zig b/lib/std/Target/loongarch.zig index ca86eda817..7a3978fc2c 100644 --- a/lib/std/Target/loongarch.zig +++ b/lib/std/Target/loongarch.zig @@ -12,9 +12,6 @@ pub const Feature = enum { div32, f, frecipe, - la_global_with_abs, - la_global_with_pcrel, - la_local_with_abs, lam_bh, lamcas, lasx, @@ -22,10 +19,8 @@ pub const Feature = enum { ld_seq_sa, lsx, lvz, - prefer_w_inst, - relax, scq, - ual, + unaligned_access, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -76,21 +71,6 @@ pub const all_features = blk: { .description = "Support frecipe.{s/d} and frsqrte.{s/d} instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.la_global_with_abs)] = .{ - .llvm_name = "la-global-with-abs", - .description = "Expand la.global as la.abs", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.la_global_with_pcrel)] = .{ - .llvm_name = "la-global-with-pcrel", - .description = "Expand la.global as la.pcrel", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.la_local_with_abs)] = .{ - .llvm_name = "la-local-with-abs", - .description = "Expand la.local as la.abs", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.lam_bh)] = .{ .llvm_name = "lam-bh", .description = "Support amswap[_db].{b/h} and amadd[_db].{b/h} instructions", @@ -130,22 +110,12 @@ pub const all_features = blk: { .description = "'LVZ' (Loongson Virtualization Extension)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.prefer_w_inst)] = .{ - .llvm_name = "prefer-w-inst", - .description = "Prefer instructions with W suffix", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.relax)] = .{ - .llvm_name = "relax", - .description = "Enable Linker relaxation", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.scq)] = .{ .llvm_name = "scq", .description = "Support sc.q instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.ual)] = .{ + result[@backingInt(Feature.unaligned_access)] = .{ .llvm_name = "ual", .description = "Allow memory accesses to be unaligned", .dependencies = featureSet(&[_]Feature{}), @@ -161,7 +131,7 @@ pub const all_features = blk: { pub const cpu = struct { pub const generic_la32: CpuModel = .{ .name = "generic_la32", - .llvm_name = "generic-la32", + .llvm_name = null, .features = featureSet(&[_]Feature{ .@"32bit", }), @@ -173,12 +143,20 @@ pub const cpu = struct { .@"64bit", }), }; + pub const la132: CpuModel = .{ + .name = "la132", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .@"32s", + }), + }; pub const la32rv1_0: CpuModel = .{ .name = "la32rv1_0", .llvm_name = null, .features = featureSet(&[_]Feature{ .@"32bit", - .ual, + .unaligned_access, }), }; pub const la32v1_0: CpuModel = .{ @@ -188,7 +166,7 @@ pub const cpu = struct { .@"32bit", .@"32s", .d, - .ual, + .unaligned_access, }), }; pub const la464: CpuModel = .{ @@ -199,7 +177,7 @@ pub const cpu = struct { .lasx, .lbt, .lvz, - .ual, + .unaligned_access, }), }; pub const la64v1_0: CpuModel = .{ @@ -208,7 +186,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .lsx, - .ual, + .unaligned_access, }), }; pub const la64v1_1: CpuModel = .{ @@ -223,7 +201,7 @@ pub const cpu = struct { .ld_seq_sa, .lsx, .scq, - .ual, + .unaligned_access, }), }; pub const la664: CpuModel = .{ @@ -240,7 +218,7 @@ pub const cpu = struct { .ld_seq_sa, .lvz, .scq, - .ual, + .unaligned_access, }), }; }; diff --git a/lib/std/Target/m68k.zig b/lib/std/Target/m68k.zig index 759f966b51..2833336d1b 100644 --- a/lib/std/Target/m68k.zig +++ b/lib/std/Target/m68k.zig @@ -13,21 +13,6 @@ pub const Feature = enum { isa_68060, isa_68881, isa_68882, - reserve_a0, - reserve_a1, - reserve_a2, - reserve_a3, - reserve_a4, - reserve_a5, - reserve_a6, - reserve_d0, - reserve_d1, - reserve_d2, - reserve_d3, - reserve_d4, - reserve_d5, - reserve_d6, - reserve_d7, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -92,81 +77,6 @@ pub const all_features = blk: { .isa_68881, }), }; - result[@backingInt(Feature.reserve_a0)] = .{ - .llvm_name = "reserve-a0", - .description = "Reserve A0 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_a1)] = .{ - .llvm_name = "reserve-a1", - .description = "Reserve A1 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_a2)] = .{ - .llvm_name = "reserve-a2", - .description = "Reserve A2 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_a3)] = .{ - .llvm_name = "reserve-a3", - .description = "Reserve A3 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_a4)] = .{ - .llvm_name = "reserve-a4", - .description = "Reserve A4 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_a5)] = .{ - .llvm_name = "reserve-a5", - .description = "Reserve A5 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_a6)] = .{ - .llvm_name = "reserve-a6", - .description = "Reserve A6 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_d0)] = .{ - .llvm_name = "reserve-d0", - .description = "Reserve D0 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_d1)] = .{ - .llvm_name = "reserve-d1", - .description = "Reserve D1 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_d2)] = .{ - .llvm_name = "reserve-d2", - .description = "Reserve D2 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_d3)] = .{ - .llvm_name = "reserve-d3", - .description = "Reserve D3 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_d4)] = .{ - .llvm_name = "reserve-d4", - .description = "Reserve D4 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_d5)] = .{ - .llvm_name = "reserve-d5", - .description = "Reserve D5 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_d6)] = .{ - .llvm_name = "reserve-d6", - .description = "Reserve D6 register", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_d7)] = .{ - .llvm_name = "reserve-d7", - .description = "Reserve D7 register", - .dependencies = featureSet(&[_]Feature{}), - }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { elem.index = i; @@ -176,50 +86,45 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{ - .isa_68000, - }), - }; - pub const M68000: CpuModel = .{ - .name = "M68000", + pub const m68000: CpuModel = .{ + .name = "m68000", .llvm_name = "M68000", .features = featureSet(&[_]Feature{ .isa_68000, }), }; - pub const M68010: CpuModel = .{ - .name = "M68010", + pub const m68010: CpuModel = .{ + .name = "m68010", .llvm_name = "M68010", .features = featureSet(&[_]Feature{ .isa_68010, }), }; - pub const M68020: CpuModel = .{ - .name = "M68020", + pub const m68020: CpuModel = .{ + .name = "m68020", .llvm_name = "M68020", .features = featureSet(&[_]Feature{ .isa_68020, + .isa_68881, }), }; - pub const M68030: CpuModel = .{ - .name = "M68030", + pub const m68030: CpuModel = .{ + .name = "m68030", .llvm_name = "M68030", .features = featureSet(&[_]Feature{ .isa_68030, + .isa_68881, }), }; - pub const M68040: CpuModel = .{ - .name = "M68040", + pub const m68040: CpuModel = .{ + .name = "m68040", .llvm_name = "M68040", .features = featureSet(&[_]Feature{ .isa_68040, }), }; - pub const M68060: CpuModel = .{ - .name = "M68060", + pub const m68060: CpuModel = .{ + .name = "m68060", .llvm_name = "M68060", .features = featureSet(&[_]Feature{ .isa_68060, diff --git a/lib/std/Target/m88k.zig b/lib/std/Target/m88k.zig new file mode 100644 index 0000000000..04f596d899 --- /dev/null +++ b/lib/std/Target/m88k.zig @@ -0,0 +1,83 @@ +//! This file is auto-generated by tools/update_cpu_features.zig. + +const std = @import("../std.zig"); +const CpuFeature = std.Target.Cpu.Feature; +const CpuModel = std.Target.Cpu.Model; + +pub const Feature = enum { + isa_88110, + sfu1, + sfu2, + xmem_imm, + xrf, +}; + +pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; +pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; +pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; +pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; + +pub const all_features = blk: { + const len = @typeInfo(Feature).@"enum".field_names.len; + std.debug.assert(len <= CpuFeature.Set.needed_bit_count); + var result: [len]CpuFeature = undefined; + result[@backingInt(Feature.isa_88110)] = .{ + .llvm_name = null, + .description = "Enable MC88110 additions to the base instruction set", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.sfu1)] = .{ + .llvm_name = null, + .description = "Enable floating-point unit", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.sfu2)] = .{ + .llvm_name = null, + .description = "Enable graphics unit", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.xmem_imm)] = .{ + .llvm_name = null, + .description = "Enable xmem with 16-bit immediate offset", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.xrf)] = .{ + .llvm_name = null, + .description = "Enable extended register file", + .dependencies = featureSet(&[_]Feature{ + .sfu1, + }), + }; + const ti = @typeInfo(Feature); + for (&result, 0..) |*elem, i| { + elem.index = i; + elem.name = ti.@"enum".field_names[i]; + } + break :blk result; +}; + +pub const cpu = struct { + pub const m88000: CpuModel = .{ + .name = "m88000", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .sfu1, + }), + }; + pub const m88100: CpuModel = .{ + .name = "m88100", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .sfu1, + .xmem_imm, + }), + }; + pub const m88110: CpuModel = .{ + .name = "m88110", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .sfu2, + .xrf, + }), + }; +}; diff --git a/lib/std/Target/microblaze.zig b/lib/std/Target/microblaze.zig new file mode 100644 index 0000000000..1a0a6844f7 --- /dev/null +++ b/lib/std/Target/microblaze.zig @@ -0,0 +1,301 @@ +//! This file is auto-generated by tools/update_cpu_features.zig. + +const std = @import("../std.zig"); +const CpuFeature = std.Target.Cpu.Feature; +const CpuModel = std.Target.Cpu.Model; + +pub const Feature = enum { + barrel, + div, + fpu, + fpu2, + msr, + mul, + mul64, + pcmp, + pipe3, + pipe8, + reorder, + v10_0, + v7_20, + v8_10, + v8_30, +}; + +pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; +pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; +pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; +pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; + +pub const all_features = blk: { + const len = @typeInfo(Feature).@"enum".field_names.len; + std.debug.assert(len <= CpuFeature.Set.needed_bit_count); + var result: [len]CpuFeature = undefined; + result[@backingInt(Feature.barrel)] = .{ + .llvm_name = null, + .description = "Enable barrel shift instructions (C_USE_BARREL)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.div)] = .{ + .llvm_name = null, + .description = "Enable hardware divide instructions (C_USE_DIV)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fpu)] = .{ + .llvm_name = null, + .description = "Enable single-precision floating point instructions (C_USE_FPU >= 1)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fpu2)] = .{ + .llvm_name = null, + .description = "Enable floating point conversion and square root instructions (C_USE_FPU = 2)", + .dependencies = featureSet(&[_]Feature{ + .fpu, + }), + }; + result[@backingInt(Feature.msr)] = .{ + .llvm_name = null, + .description = "Enable msrset and msrclr instructions (C_USE_MSR_INSTR)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.mul)] = .{ + .llvm_name = null, + .description = "Enable 32-bit multiply instructions (C_USE_HW_MUL >= 1)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.mul64)] = .{ + .llvm_name = null, + .description = "Enable multiply high instructions (C_USE_HW_MUL = 2)", + .dependencies = featureSet(&[_]Feature{ + .mul, + }), + }; + result[@backingInt(Feature.pcmp)] = .{ + .llvm_name = null, + .description = "Enable pattern compare instructions, and clz with v8.10 (C_USE_PCMP_INSTR)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.pipe3)] = .{ + .llvm_name = null, + .description = "Tune for the 3-stage pipeline (C_AREA_OPTIMIZED = 1)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.pipe8)] = .{ + .llvm_name = null, + .description = "Tune for the 8-stage pipeline (C_AREA_OPTIMIZED = 2)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reorder)] = .{ + .llvm_name = null, + .description = "Enable byte-reversed load/store instructions, and swapb and swaph with v8.30 (C_USE_REORDER_INSTR)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.v10_0)] = .{ + .llvm_name = null, + .description = "Enable MicroBlaze v10.0 instructions (bsefi and bsifi with barrel)", + .dependencies = featureSet(&[_]Feature{ + .v8_30, + }), + }; + result[@backingInt(Feature.v7_20)] = .{ + .llvm_name = null, + .description = "Enable MicroBlaze v7.20 instructions (lwx, swx)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.v8_10)] = .{ + .llvm_name = null, + .description = "Enable MicroBlaze v8.10 instructions (mbar)", + .dependencies = featureSet(&[_]Feature{ + .v7_20, + }), + }; + result[@backingInt(Feature.v8_30)] = .{ + .llvm_name = null, + .description = "Enable MicroBlaze v8.30 instructions (swapb and swaph with reorder)", + .dependencies = featureSet(&[_]Feature{ + .v8_10, + }), + }; + const ti = @typeInfo(Feature); + for (&result, 0..) |*elem, i| { + elem.index = i; + elem.name = ti.@"enum".field_names[i]; + } + break :blk result; +}; + +pub const cpu = struct { + pub const v10_0: CpuModel = .{ + .name = "v10_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v10_0, + }), + }; + pub const v11_0: CpuModel = .{ + .name = "v11_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v10_0, + }), + }; + pub const v2_00: CpuModel = .{ + .name = "v2_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .pipe3, + }), + }; + pub const v2_10: CpuModel = .{ + .name = "v2_10", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .pipe3, + }), + }; + pub const v3_00: CpuModel = .{ + .name = "v3_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .pipe3, + }), + }; + pub const v4_00: CpuModel = .{ + .name = "v4_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .pipe3, + }), + }; + pub const v5_00: CpuModel = .{ + .name = "v5_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .msr, + .pcmp, + }), + }; + pub const v6_00: CpuModel = .{ + .name = "v6_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const v7_00: CpuModel = .{ + .name = "v7_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const v7_10: CpuModel = .{ + .name = "v7_10", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const v7_20: CpuModel = .{ + .name = "v7_20", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v7_20, + }), + }; + pub const v7_30: CpuModel = .{ + .name = "v7_30", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v7_20, + }), + }; + pub const v8_00: CpuModel = .{ + .name = "v8_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .reorder, + .v7_20, + }), + }; + pub const v8_10: CpuModel = .{ + .name = "v8_10", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .reorder, + .v8_10, + }), + }; + pub const v8_20: CpuModel = .{ + .name = "v8_20", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .reorder, + .v8_10, + }), + }; + pub const v8_30: CpuModel = .{ + .name = "v8_30", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v8_40: CpuModel = .{ + .name = "v8_40", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v8_50: CpuModel = .{ + .name = "v8_50", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_0: CpuModel = .{ + .name = "v9_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_1: CpuModel = .{ + .name = "v9_1", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_2: CpuModel = .{ + .name = "v9_2", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_3: CpuModel = .{ + .name = "v9_3", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_4: CpuModel = .{ + .name = "v9_4", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_5: CpuModel = .{ + .name = "v9_5", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_6: CpuModel = .{ + .name = "v9_6", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; +}; diff --git a/lib/std/Target/mips.zig b/lib/std/Target/mips.zig index ad19d451ab..3d9b32a28c 100644 --- a/lib/std/Target/mips.zig +++ b/lib/std/Target/mips.zig @@ -14,16 +14,8 @@ pub const Feature = enum { dspr3, eva, fix_r5900, - fp64, - fpxx, ginv, - gp64, - i6400, - i6500, - long_calls, - micromips, mips1, - mips16, mips2, mips3, mips32, @@ -47,23 +39,12 @@ pub const Feature = enum { msa, mt, nan2008, - noabicalls, + no_unaligned_access, nomadd4, - nooddspreg, - notraps, - p5600, - ptr64, r5900, single_float, - soft_float, - strict_align, - sym32, - use_compact_branches, - use_indirect_jump_hazard, - use_tcc_in_div, vfpu, virt, - xgot, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -128,75 +109,27 @@ pub const all_features = blk: { .description = "Enable R5900 short loop erratum fix", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.fp64)] = .{ - .llvm_name = "fp64", - .description = "Support 64-bit FP registers", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.fpxx)] = .{ - .llvm_name = "fpxx", - .description = "Support for FPXX", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.ginv)] = .{ .llvm_name = "ginv", .description = "Mips Global Invalidate ASE", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.gp64)] = .{ - .llvm_name = "gp64", - .description = "General Purpose Registers are 64-bit wide", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.i6400)] = .{ - .llvm_name = "i6400", - .description = "MIPS I6400 Processor", - .dependencies = featureSet(&[_]Feature{ - .mips64r6, - .msa, - }), - }; - result[@backingInt(Feature.i6500)] = .{ - .llvm_name = "i6500", - .description = "MIPS I6500 Processor", - .dependencies = featureSet(&[_]Feature{ - .mips64r6, - .msa, - }), - }; - result[@backingInt(Feature.long_calls)] = .{ - .llvm_name = "long-calls", - .description = "Disable use of the jal instruction", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.micromips)] = .{ - .llvm_name = "micromips", - .description = "microMips mode", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.mips1)] = .{ .llvm_name = "mips1", - .description = "Mips I ISA Support [highly experimental]", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.mips16)] = .{ - .llvm_name = "mips16", - .description = "Mips16 mode", + .description = "Mips I ISA Support", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.mips2)] = .{ .llvm_name = "mips2", - .description = "Mips II ISA Support [highly experimental]", + .description = "Mips II ISA Support", .dependencies = featureSet(&[_]Feature{ .mips1, }), }; result[@backingInt(Feature.mips3)] = .{ .llvm_name = "mips3", - .description = "MIPS III ISA Support [highly experimental]", + .description = "MIPS III ISA Support", .dependencies = featureSet(&[_]Feature{ - .fp64, - .gp64, .mips2, .mips3_32, .mips3_32r2, @@ -240,7 +173,6 @@ pub const all_features = blk: { .description = "Mips32r6 ISA Support [experimental]", .dependencies = featureSet(&[_]Feature{ .abs2008, - .fp64, .mips32r5, .nan2008, }), @@ -347,9 +279,9 @@ pub const all_features = blk: { .description = "IEEE 754-2008 NaN encoding", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.noabicalls)] = .{ - .llvm_name = "noabicalls", - .description = "Disable SVR4-style position-independent code", + result[@backingInt(Feature.no_unaligned_access)] = .{ + .llvm_name = "strict-align", + .description = "Disable unaligned load store for r6", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.nomadd4)] = .{ @@ -357,28 +289,6 @@ pub const all_features = blk: { .description = "Disable 4-operand madd.fmt and related instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.nooddspreg)] = .{ - .llvm_name = "nooddspreg", - .description = "Disable odd numbered single-precision registers", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.notraps)] = .{ - .llvm_name = null, - .description = "Disable trap instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.p5600)] = .{ - .llvm_name = "p5600", - .description = "The P5600 Processor", - .dependencies = featureSet(&[_]Feature{ - .mips32r5, - }), - }; - result[@backingInt(Feature.ptr64)] = .{ - .llvm_name = "ptr64", - .description = "Pointers are 64-bit wide", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.r5900)] = .{ .llvm_name = "r5900", .description = "R5900 (PS2 Emotion Engine) Support", @@ -393,36 +303,6 @@ pub const all_features = blk: { .description = "Only supports single precision float", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.soft_float)] = .{ - .llvm_name = "soft-float", - .description = "Does not support floating point instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.strict_align)] = .{ - .llvm_name = "strict-align", - .description = "Disable unaligned load store for r6", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.sym32)] = .{ - .llvm_name = "sym32", - .description = "Symbols are 32 bit on Mips64", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.use_compact_branches)] = .{ - .llvm_name = "use-compact-branches", - .description = "Use compact branch instructions for MIPS32R6/MIPS64R6", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.use_indirect_jump_hazard)] = .{ - .llvm_name = "use-indirect-jump-hazard", - .description = "Use indirect jump guards to prevent certain speculation based attacks", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.use_tcc_in_div)] = .{ - .llvm_name = "use-tcc-in-div", - .description = "Force the assembler to use trapping", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.vfpu)] = .{ .llvm_name = "vfpu", .description = "Enable vector FPU instructions", @@ -433,11 +313,6 @@ pub const all_features = blk: { .description = "Mips Virtualization ASE", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.xgot)] = .{ - .llvm_name = "xgot", - .description = "Assume 32-bit GOT", - .dependencies = featureSet(&[_]Feature{}), - }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { elem.index = i; @@ -449,32 +324,27 @@ pub const all_features = blk: { pub const cpu = struct { pub const allegrex: CpuModel = .{ .name = "allegrex", - .llvm_name = null, + .llvm_name = "mips2", .features = featureSet(&[_]Feature{ .mips2, - .notraps, .single_float, - }), - }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{ - .mips32, + .vfpu, }), }; pub const @"i6400": CpuModel = .{ .name = "i6400", .llvm_name = "i6400", .features = featureSet(&[_]Feature{ - .i6400, + .mips64r6, + .msa, }), }; pub const @"i6500": CpuModel = .{ .name = "i6500", .llvm_name = "i6500", .features = featureSet(&[_]Feature{ - .i6500, + .mips64r6, + .msa, }), }; pub const mips1: CpuModel = .{ @@ -540,13 +410,6 @@ pub const cpu = struct { .mips4, }), }; - pub const mips5: CpuModel = .{ - .name = "mips5", - .llvm_name = "mips5", - .features = featureSet(&[_]Feature{ - .mips5, - }), - }; pub const mips64: CpuModel = .{ .name = "mips64", .llvm_name = "mips64", @@ -600,16 +463,14 @@ pub const cpu = struct { .name = "p5600", .llvm_name = "p5600", .features = featureSet(&[_]Feature{ - .p5600, + .mips32r5, }), }; pub const r3000a: CpuModel = .{ .name = "r3000a", - .llvm_name = null, + .llvm_name = "mips1", .features = featureSet(&[_]Feature{ .mips1, - .notraps, - .soft_float, }), }; pub const r5900: CpuModel = .{ diff --git a/lib/std/Target/msp430.zig b/lib/std/Target/msp430.zig index d2999c13c8..4e0474a14f 100644 --- a/lib/std/Target/msp430.zig +++ b/lib/std/Target/msp430.zig @@ -33,7 +33,9 @@ pub const all_features = blk: { result[@backingInt(Feature.hwmult32)] = .{ .llvm_name = "hwmult32", .description = "Enable 32-bit hardware multiplier", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .hwmult16, + }), }; result[@backingInt(Feature.hwmultf5)] = .{ .llvm_name = "hwmultf5", @@ -49,11 +51,6 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{}), - }; pub const msp430: CpuModel = .{ .name = "msp430", .llvm_name = "msp430", diff --git a/lib/std/Target/or1k.zig b/lib/std/Target/or1k.zig new file mode 100644 index 0000000000..230fb815ef --- /dev/null +++ b/lib/std/Target/or1k.zig @@ -0,0 +1,253 @@ +//! This file is auto-generated by tools/update_cpu_features.zig. + +const std = @import("../std.zig"); +const CpuFeature = std.Target.Cpu.Feature; +const CpuModel = std.Target.Cpu.Model; + +pub const Feature = enum { + adrp, + atomic, + cmov, + csync, + div, + ext, + ff1, + fl1, + mac, + madd_d, + madd_s, + msync, + mul, + muld, + no_addc, + no_sr_cy, + no_sr_ov, + no_sra, + orfpx32, + orfpx64a32, + psync, + ror, + sfimm, + sfun_s, + stod_dtos, +}; + +pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; +pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; +pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; +pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; + +pub const all_features = blk: { + const len = @typeInfo(Feature).@"enum".field_names.len; + std.debug.assert(len <= CpuFeature.Set.needed_bit_count); + var result: [len]CpuFeature = undefined; + result[@backingInt(Feature.adrp)] = .{ + .llvm_name = null, + .description = "Enable PC-relative page address instruction (l.adrp)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.atomic)] = .{ + .llvm_name = null, + .description = "Enable load-linked/store-conditional instructions (l.lwa, l.swa)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.cmov)] = .{ + .llvm_name = null, + .description = "Enable conditional move instruction (l.cmov)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.csync)] = .{ + .llvm_name = null, + .description = "Enable context synchronization instruction (l.csync)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.div)] = .{ + .llvm_name = null, + .description = "Enable hardware divide instructions (l.div, l.divu)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.ext)] = .{ + .llvm_name = null, + .description = "Enable sign/zero extension instructions (l.extbs, l.extbz, l.exths, l.exthz, l.extws, l.extwz)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.ff1)] = .{ + .llvm_name = null, + .description = "Enable find first 1 instruction (l.ff1)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fl1)] = .{ + .llvm_name = null, + .description = "Enable find last 1 instruction (l.fl1)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.mac)] = .{ + .llvm_name = null, + .description = "Enable multiply-accumulate instructions (l.mac, l.maci, l.macrc, l.macu, l.msb, l.msbu)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.madd_d)] = .{ + .llvm_name = null, + .description = "Enable double-precision floating point multiply-add instruction (lf.madd.d)", + .dependencies = featureSet(&[_]Feature{ + .orfpx64a32, + }), + }; + result[@backingInt(Feature.madd_s)] = .{ + .llvm_name = null, + .description = "Enable single-precision floating point multiply-add instruction (lf.madd.s)", + .dependencies = featureSet(&[_]Feature{ + .orfpx32, + }), + }; + result[@backingInt(Feature.msync)] = .{ + .llvm_name = null, + .description = "Enable memory synchronization instruction (l.msync)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.mul)] = .{ + .llvm_name = null, + .description = "Enable hardware multiply instructions (l.mul, l.muli, l.mulu)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.muld)] = .{ + .llvm_name = null, + .description = "Enable widening multiply instructions (l.muld, l.muldu)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.no_addc)] = .{ + .llvm_name = null, + .description = "Disable add with carry instructions (l.addc, l.addic)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.no_sr_cy)] = .{ + .llvm_name = null, + .description = "Disable carry flag (SR[CY]) updates", + .dependencies = featureSet(&[_]Feature{ + .no_addc, + }), + }; + result[@backingInt(Feature.no_sr_ov)] = .{ + .llvm_name = null, + .description = "Disable overflow flag (SR[OV]) updates", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.no_sra)] = .{ + .llvm_name = null, + .description = "Disable arithmetic shift right instructions (l.sra, l.srai)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.orfpx32)] = .{ + .llvm_name = null, + .description = "Enable single-precision floating point instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.orfpx64a32)] = .{ + .llvm_name = null, + .description = "Enable double-precision floating point instructions on register pairs", + .dependencies = featureSet(&[_]Feature{ + .sfun_s, + }), + }; + result[@backingInt(Feature.psync)] = .{ + .llvm_name = null, + .description = "Enable pipeline synchronization instruction (l.psync)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.ror)] = .{ + .llvm_name = null, + .description = "Enable rotate right instructions (l.ror, l.rori)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.sfimm)] = .{ + .llvm_name = null, + .description = "Enable set flag with immediate instructions (l.sfeqi, l.sfnei, l.sfgtsi, l.sfgtui, l.sfgesi, l.sfgeui, l.sfltsi, l.sfltui, l.sflesi, l.sfleui)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.sfun_s)] = .{ + .llvm_name = null, + .description = "Enable unordered single-precision floating point comparison instructions (lf.sfueq.s, lf.sfune.s, lf.sfugt.s, lf.sfuge.s, lf.sfult.s, lf.sfule.s, lf.sfun.s)", + .dependencies = featureSet(&[_]Feature{ + .orfpx32, + }), + }; + result[@backingInt(Feature.stod_dtos)] = .{ + .llvm_name = null, + .description = "Enable floating point precision conversion instructions (lf.stod.d, lf.dtos.d)", + .dependencies = featureSet(&[_]Feature{ + .orfpx64a32, + }), + }; + const ti = @typeInfo(Feature); + for (&result, 0..) |*elem, i| { + elem.index = i; + elem.name = ti.@"enum".field_names[i]; + } + break :blk result; +}; + +pub const cpu = struct { + pub const ar100: CpuModel = .{ + .name = "ar100", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .csync, + .ff1, + .msync, + .psync, + .sfimm, + }), + }; + pub const marocchino: CpuModel = .{ + .name = "marocchino", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .atomic, + .cmov, + .div, + .ext, + .ff1, + .fl1, + .msync, + .mul, + .orfpx64a32, + .ror, + .sfimm, + }), + }; + pub const mor1kx: CpuModel = .{ + .name = "mor1kx", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .atomic, + .cmov, + .div, + .ff1, + .fl1, + .msync, + .mul, + .sfimm, + }), + }; + pub const or1200: CpuModel = .{ + .name = "or1200", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .cmov, + .csync, + .div, + .ext, + .ff1, + .fl1, + .msync, + .mul, + .psync, + .sfimm, + }), + }; + pub const orbis32: CpuModel = .{ + .name = "orbis32", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; +}; diff --git a/lib/std/Target/powerpc.zig b/lib/std/Target/powerpc.zig index c66e0156e4..089f7fad25 100644 --- a/lib/std/Target/powerpc.zig +++ b/lib/std/Target/powerpc.zig @@ -6,20 +6,15 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { @"64bit", - @"64bit_support", - @"64bitregs", - allow_unaligned_fp_access, altivec, booke, bpermd, cmpb, - crbits, crypto, direct_move, - e500, efpu2, extdiv, - fast_MFLR, + fast_mflr, fcpsgn, float128, fpcvt, @@ -43,12 +38,8 @@ pub const Feature = enum { fuse_wideimm, fuse_zeromove, fusion, - future_vector, - hard_float, htm, icbt, - invariant_function_descriptors, - isa_future_instructions, isa_v206_instructions, isa_v207_instructions, isa_v30_instructions, @@ -56,7 +47,6 @@ pub const Feature = enum { isel, ldbrx, lfiwax, - longcall, mfocrf, mma, msync, @@ -69,22 +59,15 @@ pub const Feature = enum { power8_vector, power9_altivec, power9_vector, - ppc4xx, - ppc6xx, - ppc_postra_sched, - ppc_prera_sched, predictable_select_expensive, prefix_instrs, - privileged, quadword_atomics, recipprec, - rop_protect, - secure_plt, slow_popcntd, spe, stfiwx, two_const_nr, - use_ptrgl_helper, + unaligned_fp_access, vectors_use_two_units, vsx, }; @@ -99,27 +82,10 @@ pub const all_features = blk: { std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; result[@backingInt(Feature.@"64bit")] = .{ - .llvm_name = "64bit", - .description = "Enable 64-bit mode", - .dependencies = featureSet(&[_]Feature{ - .@"64bit_support", - }), - }; - result[@backingInt(Feature.@"64bit_support")] = .{ .llvm_name = "64bit-support", .description = "Supports 64-bit instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.@"64bitregs")] = .{ - .llvm_name = "64bitregs", - .description = "Enable 64-bit registers usage for ppc32 [beta]", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.allow_unaligned_fp_access)] = .{ - .llvm_name = "allow-unaligned-fp-access", - .description = "CPU does not trap on unaligned FP access", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.altivec)] = .{ .llvm_name = "altivec", .description = "Enable Altivec instructions", @@ -144,11 +110,6 @@ pub const all_features = blk: { .description = "Enable the cmpb instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.crbits)] = .{ - .llvm_name = "crbits", - .description = "Use condition-register bits individually", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.crypto)] = .{ .llvm_name = "crypto", .description = "Enable POWER8 Crypto instructions", @@ -163,11 +124,6 @@ pub const all_features = blk: { .vsx, }), }; - result[@backingInt(Feature.e500)] = .{ - .llvm_name = "e500", - .description = "Enable E500/E500mc instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.efpu2)] = .{ .llvm_name = "efpu2", .description = "Enable Embedded Floating-Point APU 2 instructions", @@ -180,7 +136,7 @@ pub const all_features = blk: { .description = "Enable extended divide instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.fast_MFLR)] = .{ + result[@backingInt(Feature.fast_mflr)] = .{ .llvm_name = "fast-MFLR", .description = "MFLR is a fast instruction", .dependencies = featureSet(&[_]Feature{}), @@ -216,9 +172,7 @@ pub const all_features = blk: { result[@backingInt(Feature.fpu)] = .{ .llvm_name = "fpu", .description = "Enable classic FPU instructions", - .dependencies = featureSet(&[_]Feature{ - .hard_float, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.fre)] = .{ .llvm_name = "fre", @@ -344,19 +298,6 @@ pub const all_features = blk: { .description = "Target supports instruction fusion", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.future_vector)] = .{ - .llvm_name = "future-vector", - .description = "Enable Future vector instructions", - .dependencies = featureSet(&[_]Feature{ - .isa_future_instructions, - .power10_vector, - }), - }; - result[@backingInt(Feature.hard_float)] = .{ - .llvm_name = "hard-float", - .description = "Enable floating-point instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.htm)] = .{ .llvm_name = "htm", .description = "Enable Hardware Transactional Memory instructions", @@ -367,18 +308,6 @@ pub const all_features = blk: { .description = "Enable icbt instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.invariant_function_descriptors)] = .{ - .llvm_name = "invariant-function-descriptors", - .description = "Assume function descriptors are invariant", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.isa_future_instructions)] = .{ - .llvm_name = "isa-future-instructions", - .description = "Enable instructions for Future ISA.", - .dependencies = featureSet(&[_]Feature{ - .isa_v31_instructions, - }), - }; result[@backingInt(Feature.isa_v206_instructions)] = .{ .llvm_name = "isa-v206-instructions", .description = "Enable instructions in ISA 2.06.", @@ -420,11 +349,6 @@ pub const all_features = blk: { .fpu, }), }; - result[@backingInt(Feature.longcall)] = .{ - .llvm_name = "longcall", - .description = "Always use indirect calls", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.mfocrf)] = .{ .llvm_name = "mfocrf", .description = "Enable the MFOCRF instruction", @@ -510,26 +434,6 @@ pub const all_features = blk: { .power9_altivec, }), }; - result[@backingInt(Feature.ppc4xx)] = .{ - .llvm_name = "ppc4xx", - .description = "Enable PPC 4xx instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ppc6xx)] = .{ - .llvm_name = "ppc6xx", - .description = "Enable PPC 6xx instructions", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ppc_postra_sched)] = .{ - .llvm_name = "ppc-postra-sched", - .description = "Use PowerPC post-RA scheduling strategy", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.ppc_prera_sched)] = .{ - .llvm_name = "ppc-prera-sched", - .description = "Use PowerPC pre-RA scheduling strategy", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.predictable_select_expensive)] = .{ .llvm_name = "predictable-select-expensive", .description = "Prefer likely predicted branches over selects", @@ -542,11 +446,6 @@ pub const all_features = blk: { .isa_v31_instructions, }), }; - result[@backingInt(Feature.privileged)] = .{ - .llvm_name = "privileged", - .description = "Add privileged instructions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.quadword_atomics)] = .{ .llvm_name = "quadword-atomics", .description = "Enable lqarx and stqcx.", @@ -557,16 +456,6 @@ pub const all_features = blk: { .description = "Assume higher precision reciprocal estimates", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.rop_protect)] = .{ - .llvm_name = "rop-protect", - .description = "Add ROP protect", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.secure_plt)] = .{ - .llvm_name = "secure-plt", - .description = "Enable secure plt mode", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.slow_popcntd)] = .{ .llvm_name = "slow-popcntd", .description = "Has slow popcnt[dw] instructions", @@ -575,9 +464,7 @@ pub const all_features = blk: { result[@backingInt(Feature.spe)] = .{ .llvm_name = "spe", .description = "Enable SPE instructions", - .dependencies = featureSet(&[_]Feature{ - .hard_float, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.stfiwx)] = .{ .llvm_name = "stfiwx", @@ -591,9 +478,9 @@ pub const all_features = blk: { .description = "Requires two constant Newton-Raphson computation", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.use_ptrgl_helper)] = .{ - .llvm_name = "use-ptrgl-helper", - .description = "Use ._ptrgl for indirect calls", + result[@backingInt(Feature.unaligned_fp_access)] = .{ + .llvm_name = "allow-unaligned-fp-access", + .description = "CPU does not trap on unaligned FP access", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.vectors_use_two_units)] = .{ @@ -729,7 +616,7 @@ pub const cpu = struct { .name = "970", .llvm_name = "970", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .fres, .frsqrte, @@ -742,7 +629,7 @@ pub const cpu = struct { .name = "a2", .llvm_name = "a2", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .booke, .cmpb, .fcpsgn, @@ -765,9 +652,9 @@ pub const cpu = struct { }; pub const cell: CpuModel = .{ .name = "cell", - .llvm_name = null, + .llvm_name = "970", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .fres, .frsqrte, @@ -794,20 +681,11 @@ pub const cpu = struct { .stfiwx, }), }; - pub const e500v2: CpuModel = .{ - .name = "e500v2", - .llvm_name = null, - .features = featureSet(&[_]Feature{ - .efpu2, - .isel, - .msync, - }), - }; pub const e5500: CpuModel = .{ .name = "e5500", .llvm_name = "e5500", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .booke, .isel, .mfocrf, @@ -816,61 +694,20 @@ pub const cpu = struct { }; pub const e6500: CpuModel = .{ .name = "e6500", - .llvm_name = null, + .llvm_name = "e5500", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .booke, - .isel, - .mfocrf, - .stfiwx, - }), - }; - pub const future: CpuModel = .{ - .name = "future", - .llvm_name = "future", - .features = featureSet(&[_]Feature{ - .@"64bit_support", - .allow_unaligned_fp_access, .bpermd, .cmpb, - .crbits, - .crypto, - .direct_move, - .extdiv, - .fast_MFLR, - .fcpsgn, - .fpcvt, - .fprnd, - .fre, .fres, .frsqrte, - .frsqrtes, - .fsqrt, - .fuse_add_logical, - .fuse_arith_add, - .fuse_logical, - .fuse_logical_add, - .fuse_sha3, - .fuse_store, - .future_vector, - .icbt, - .isa_v206_instructions, .isel, - .ldbrx, - .lfiwax, .mfocrf, - .mma, .partword_atomics, - .pcrelative_memops, .popcntd, - .ppc_postra_sched, - .ppc_prera_sched, - .predictable_select_expensive, - .quadword_atomics, - .recipprec, .stfiwx, - .two_const_nr, }), }; pub const g3: CpuModel = .{ @@ -903,7 +740,7 @@ pub const cpu = struct { .name = "g5", .llvm_name = "g5", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .fres, .frsqrte, @@ -912,25 +749,16 @@ pub const cpu = struct { .stfiwx, }), }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{ - .hard_float, - }), - }; - pub const ppc: CpuModel = .{ - .name = "ppc", - .llvm_name = "ppc", - .features = featureSet(&[_]Feature{ - .hard_float, - }), + pub const ppc32: CpuModel = .{ + .name = "ppc32", + .llvm_name = "ppc32", + .features = featureSet(&[_]Feature{}), }; pub const ppc64: CpuModel = .{ .name = "ppc64", .llvm_name = "ppc64", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .fres, .frsqrte, @@ -943,11 +771,9 @@ pub const cpu = struct { .name = "ppc64le", .llvm_name = "ppc64le", .features = featureSet(&[_]Feature{ - .@"64bit_support", - .allow_unaligned_fp_access, + .@"64bit", .bpermd, .cmpb, - .crbits, .crypto, .direct_move, .extdiv, @@ -977,21 +803,20 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, }), }; pub const pwr10: CpuModel = .{ .name = "pwr10", .llvm_name = "pwr10", .features = featureSet(&[_]Feature{ - .@"64bit_support", - .allow_unaligned_fp_access, + .@"64bit", .bpermd, .cmpb, - .crbits, .crypto, .direct_move, .extdiv, - .fast_MFLR, + .fast_mflr, .fcpsgn, .fpcvt, .fprnd, @@ -1017,28 +842,25 @@ pub const cpu = struct { .pcrelative_memops, .popcntd, .power10_vector, - .ppc_postra_sched, - .ppc_prera_sched, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, }), }; pub const pwr11: CpuModel = .{ .name = "pwr11", .llvm_name = "pwr11", .features = featureSet(&[_]Feature{ - .@"64bit_support", - .allow_unaligned_fp_access, + .@"64bit", .bpermd, .cmpb, - .crbits, .crypto, .direct_move, .extdiv, - .fast_MFLR, + .fast_mflr, .fcpsgn, .fpcvt, .fprnd, @@ -1064,20 +886,19 @@ pub const cpu = struct { .pcrelative_memops, .popcntd, .power10_vector, - .ppc_postra_sched, - .ppc_prera_sched, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, }), }; pub const pwr3: CpuModel = .{ .name = "pwr3", .llvm_name = "pwr3", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .fres, .frsqrte, @@ -1089,7 +910,7 @@ pub const cpu = struct { .name = "pwr4", .llvm_name = "pwr4", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .fres, .frsqrte, @@ -1102,7 +923,7 @@ pub const cpu = struct { .name = "pwr5", .llvm_name = "pwr5", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .fre, .fres, @@ -1117,7 +938,7 @@ pub const cpu = struct { .name = "pwr5x", .llvm_name = "pwr5x", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .fprnd, .fre, @@ -1133,7 +954,7 @@ pub const cpu = struct { .name = "pwr6", .llvm_name = "pwr6", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .cmpb, .fcpsgn, @@ -1153,7 +974,7 @@ pub const cpu = struct { .name = "pwr6x", .llvm_name = "pwr6x", .features = featureSet(&[_]Feature{ - .@"64bit_support", + .@"64bit", .altivec, .cmpb, .fcpsgn, @@ -1173,8 +994,7 @@ pub const cpu = struct { .name = "pwr7", .llvm_name = "pwr7", .features = featureSet(&[_]Feature{ - .@"64bit_support", - .allow_unaligned_fp_access, + .@"64bit", .bpermd, .cmpb, .extdiv, @@ -1195,6 +1015,7 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, .vsx, }), }; @@ -1202,11 +1023,9 @@ pub const cpu = struct { .name = "pwr8", .llvm_name = "pwr8", .features = featureSet(&[_]Feature{ - .@"64bit_support", - .allow_unaligned_fp_access, + .@"64bit", .bpermd, .cmpb, - .crbits, .crypto, .direct_move, .extdiv, @@ -1236,17 +1055,16 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, }), }; pub const pwr9: CpuModel = .{ .name = "pwr9", .llvm_name = "pwr9", .features = featureSet(&[_]Feature{ - .@"64bit_support", - .allow_unaligned_fp_access, + .@"64bit", .bpermd, .cmpb, - .crbits, .crypto, .direct_move, .extdiv, @@ -1268,13 +1086,12 @@ pub const cpu = struct { .partword_atomics, .popcntd, .power9_vector, - .ppc_postra_sched, - .ppc_prera_sched, .predictable_select_expensive, .quadword_atomics, .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, .vectors_use_two_units, }), }; diff --git a/lib/std/Target/riscv.zig b/lib/std/Target/riscv.zig index 3f9f11b9e9..fab072d371 100644 --- a/lib/std/Target/riscv.zig +++ b/lib/std/Target/riscv.zig @@ -8,55 +8,13 @@ pub const Feature = enum { @"32bit", @"64bit", a, - andes45, b, c, conditional_cmv_fusion, d, - disable_latency_sched_heuristic, - disable_misched_load_clustering, - disable_misched_store_clustering, - disable_postmisched_load_clustering, - disable_postmisched_store_clustering, dlen_factor_2, e, - enable_select_opt, - enable_vsetvli_sched_heuristic, - exact_asm, - experimental, - experimental_p, - experimental_rvm23u32, - experimental_smpmpmt, - experimental_svukte, - experimental_xqccmt, - experimental_xsfmclic, - experimental_xsfsclic, - experimental_y, - experimental_zibi, - experimental_zicfilp, - experimental_zicfiss, - experimental_zvabd, - experimental_zvbc32e, - experimental_zvdot4a8i, - experimental_zvfbdota32f, - experimental_zvfbfa, - experimental_zvfofp8min, - experimental_zvfqwbdota8f, - experimental_zvfqwdota8f, - experimental_zvfwbdota16bf, - experimental_zvfwdota16bf, - experimental_zvkgs, - experimental_zvqwbdota16i, - experimental_zvqwbdota8i, - experimental_zvqwdota16i, - experimental_zvqwdota8i, - experimental_zvvfmm, - experimental_zvvmm, - experimental_zvvmtls, - experimental_zvvmttls, - experimental_zvzip, f, - forced_atomics, fusion_add_load, fusion_add_mem, fusion_addi_load, @@ -80,10 +38,7 @@ pub const Feature = enum { i, log_vrgather, m, - mips_p8700, - no_default_unroll, no_sink_splat_operands, - no_trailing_seq_cst_fence, optimized_nf2_segment_load_store, optimized_nf3_segment_load_store, optimized_nf4_segment_load_store, @@ -98,49 +53,6 @@ pub const Feature = enum { prefer_vsetvli_over_read_vlenb, prefer_w_inst, q, - relax, - reserve_x1, - reserve_x10, - reserve_x11, - reserve_x12, - reserve_x13, - reserve_x14, - reserve_x15, - reserve_x16, - reserve_x17, - reserve_x18, - reserve_x19, - reserve_x2, - reserve_x20, - reserve_x21, - reserve_x22, - reserve_x23, - reserve_x24, - reserve_x25, - reserve_x26, - reserve_x27, - reserve_x28, - reserve_x29, - reserve_x3, - reserve_x30, - reserve_x31, - reserve_x4, - reserve_x5, - reserve_x6, - reserve_x7, - reserve_x8, - reserve_x9, - rva20s64, - rva20u64, - rva22s64, - rva22u64, - rva23s64, - rva23u64, - rvb23s64, - rvb23u64, - rvi20u32, - rvi20u64, - save_restore, sdext, sdtrig, sha, @@ -194,12 +106,9 @@ pub const Feature = enum { svpbmt, svrsw60t59b, svvptc, - tagged_globals, - unaligned_scalar_mem, - unaligned_vector_mem, - use_postra_scheduler, + unaligned_access, + unaligned_vector_access, v, - ventana_veyron, vl_dependent_latency, vxrm_pipeline_flush, xaifet, @@ -210,7 +119,6 @@ pub const Feature = enum { xandesvpackfph, xandesvsinth, xandesvsintload, - xcheriot, xcvalu, xcvbi, xcvbitmanip, @@ -413,11 +321,6 @@ pub const all_features = blk: { .zalrsc, }), }; - result[@backingInt(Feature.andes45)] = .{ - .llvm_name = "andes45", - .description = "Andes 45-Series processors", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.b)] = .{ .llvm_name = "b", .description = "'B' (the collection of the Zba, Zbb, Zbs extensions)", @@ -446,31 +349,6 @@ pub const all_features = blk: { .f, }), }; - result[@backingInt(Feature.disable_latency_sched_heuristic)] = .{ - .llvm_name = "disable-latency-sched-heuristic", - .description = "Disable latency scheduling heuristic", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.disable_misched_load_clustering)] = .{ - .llvm_name = "disable-misched-load-clustering", - .description = "Disable load clustering in the machine scheduler", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.disable_misched_store_clustering)] = .{ - .llvm_name = "disable-misched-store-clustering", - .description = "Disable store clustering in the machine scheduler", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.disable_postmisched_load_clustering)] = .{ - .llvm_name = "disable-postmisched-load-clustering", - .description = "Disable PostRA load clustering in the machine scheduler", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.disable_postmisched_store_clustering)] = .{ - .llvm_name = "disable-postmisched-store-clustering", - .description = "Disable PostRA store clustering in the machine scheduler", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.dlen_factor_2)] = .{ .llvm_name = "dlen-factor-2", .description = "Vector unit DLEN(data path width) is half of VLEN", @@ -481,245 +359,6 @@ pub const all_features = blk: { .description = "'E' (Embedded Instruction Set with 16 GPRs)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.enable_select_opt)] = .{ - .llvm_name = "enable-select-opt", - .description = "Enable the select optimize pass for select loop heuristics", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.enable_vsetvli_sched_heuristic)] = .{ - .llvm_name = "enable-vsetvli-sched-heuristic", - .description = "Enable vsetvli-based scheduling heuristic", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.exact_asm)] = .{ - .llvm_name = "exact-asm", - .description = "Enable Exact Assembly (Disables Compression and Relaxation)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental)] = .{ - .llvm_name = "experimental", - .description = "Experimental intrinsics", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_p)] = .{ - .llvm_name = "experimental-p", - .description = "'P' ('Base P' (Packed SIMD))", - .dependencies = featureSet(&[_]Feature{ - .zba, - .zbb, - .zicsr, - .zmmul, - }), - }; - result[@backingInt(Feature.experimental_rvm23u32)] = .{ - .llvm_name = "experimental-rvm23u32", - .description = "RISC-V experimental-rvm23u32 profile", - .dependencies = featureSet(&[_]Feature{ - .@"32bit", - .b, - .i, - .m, - .zce, - .zcmop, - .zicbop, - .zicond, - .zihintntl, - .zihintpause, - .zimop, - }), - }; - result[@backingInt(Feature.experimental_smpmpmt)] = .{ - .llvm_name = "experimental-smpmpmt", - .description = "'Smpmpmt' (PMP-based Memory Types Extension)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_svukte)] = .{ - .llvm_name = "experimental-svukte", - .description = "'Svukte' (Address-Independent Latency of User-Mode Faults to Supervisor Addresses)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_xqccmt)] = .{ - .llvm_name = "experimental-xqccmt", - .description = "'Xqccmt' (Qualcomm 16-bit Table Jump)", - .dependencies = featureSet(&[_]Feature{ - .zca, - .zicsr, - }), - }; - result[@backingInt(Feature.experimental_xsfmclic)] = .{ - .llvm_name = "experimental-xsfmclic", - .description = "'XSfmclic' (SiFive CLIC Machine-mode CSRs)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_xsfsclic)] = .{ - .llvm_name = "experimental-xsfsclic", - .description = "'XSfsclic' (SiFive CLIC Supervisor-mode CSRs)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_y)] = .{ - .llvm_name = "experimental-y", - .description = "'Y' ('Base Y' (CHERI))", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_zibi)] = .{ - .llvm_name = "experimental-zibi", - .description = "'Zibi' (Branch with Immediate)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_zicfilp)] = .{ - .llvm_name = "experimental-zicfilp", - .description = "'Zicfilp' (Landing pad)", - .dependencies = featureSet(&[_]Feature{ - .zicsr, - }), - }; - result[@backingInt(Feature.experimental_zicfiss)] = .{ - .llvm_name = "experimental-zicfiss", - .description = "'Zicfiss' (Shadow stack)", - .dependencies = featureSet(&[_]Feature{ - .zicsr, - .zimop, - }), - }; - result[@backingInt(Feature.experimental_zvabd)] = .{ - .llvm_name = "experimental-zvabd", - .description = "'Zvabd' (Vector Absolute Difference)", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.experimental_zvbc32e)] = .{ - .llvm_name = "experimental-zvbc32e", - .description = "'Zvbc32e' (Vector Carryless Multiplication with 32-bits elements)", - .dependencies = featureSet(&[_]Feature{ - .zve32x, - }), - }; - result[@backingInt(Feature.experimental_zvdot4a8i)] = .{ - .llvm_name = "experimental-zvdot4a8i", - .description = "'Zvdot4a8i' (Vector 4-element Dot Product of packed 8-bit Integers)", - .dependencies = featureSet(&[_]Feature{ - .zve32x, - }), - }; - result[@backingInt(Feature.experimental_zvfbdota32f)] = .{ - .llvm_name = "experimental-zvfbdota32f", - .description = "'Zvfbdota32f' (FP32 batched dot-product extension)", - .dependencies = featureSet(&[_]Feature{ - .zve32f, - }), - }; - result[@backingInt(Feature.experimental_zvfbfa)] = .{ - .llvm_name = "experimental-zvfbfa", - .description = "'Zvfbfa' (Additional BF16 vector compute support)", - .dependencies = featureSet(&[_]Feature{ - .zfbfmin, - .zve32f, - }), - }; - result[@backingInt(Feature.experimental_zvfofp8min)] = .{ - .llvm_name = "experimental-zvfofp8min", - .description = "'Zvfofp8min' (Vector OFP8 Converts)", - .dependencies = featureSet(&[_]Feature{ - .zve32f, - }), - }; - result[@backingInt(Feature.experimental_zvfqwbdota8f)] = .{ - .llvm_name = "experimental-zvfqwbdota8f", - .description = "'Zvfqwbdota8f' (OCP FP8 batched dot-product extension)", - .dependencies = featureSet(&[_]Feature{ - .zve32f, - }), - }; - result[@backingInt(Feature.experimental_zvfqwdota8f)] = .{ - .llvm_name = "experimental-zvfqwdota8f", - .description = "'Zvfqwdota8f' (OCP FP8 Dot-Product)", - .dependencies = featureSet(&[_]Feature{ - .zve32f, - }), - }; - result[@backingInt(Feature.experimental_zvfwbdota16bf)] = .{ - .llvm_name = "experimental-zvfwbdota16bf", - .description = "'Zvfwbdota16bf' (BF16 batched dot-product extension)", - .dependencies = featureSet(&[_]Feature{ - .zve32f, - }), - }; - result[@backingInt(Feature.experimental_zvfwdota16bf)] = .{ - .llvm_name = "experimental-zvfwdota16bf", - .description = "'Zvfwdota16bf' (BF16 Dot-Product)", - .dependencies = featureSet(&[_]Feature{ - .zve32f, - }), - }; - result[@backingInt(Feature.experimental_zvkgs)] = .{ - .llvm_name = "experimental-zvkgs", - .description = "'Zvkgs' (Vector-Scalar GCM instructions for Cryptography)", - .dependencies = featureSet(&[_]Feature{ - .zvkg, - }), - }; - result[@backingInt(Feature.experimental_zvqwbdota16i)] = .{ - .llvm_name = "experimental-zvqwbdota16i", - .description = "'Zvqwbdota16i' (16-bit integer batched dot-product extension)", - .dependencies = featureSet(&[_]Feature{ - .zve64x, - }), - }; - result[@backingInt(Feature.experimental_zvqwbdota8i)] = .{ - .llvm_name = "experimental-zvqwbdota8i", - .description = "'Zvqwbdota8i' (8-bit integer batched dot-product extension)", - .dependencies = featureSet(&[_]Feature{ - .zve32x, - }), - }; - result[@backingInt(Feature.experimental_zvqwdota16i)] = .{ - .llvm_name = "experimental-zvqwdota16i", - .description = "'Zvqwdota16i' (16-bit Integer Dot-Product)", - .dependencies = featureSet(&[_]Feature{ - .zve64x, - }), - }; - result[@backingInt(Feature.experimental_zvqwdota8i)] = .{ - .llvm_name = "experimental-zvqwdota8i", - .description = "'Zvqwdota8i' (8-bit Integer Dot-Product)", - .dependencies = featureSet(&[_]Feature{ - .zve32x, - }), - }; - result[@backingInt(Feature.experimental_zvvfmm)] = .{ - .llvm_name = "experimental-zvvfmm", - .description = "'Zvvfmm' (Floating-Point Matrix Multiply-Accumulate)", - .dependencies = featureSet(&[_]Feature{ - .zve32f, - }), - }; - result[@backingInt(Feature.experimental_zvvmm)] = .{ - .llvm_name = "experimental-zvvmm", - .description = "'Zvvmm' (Integer Matrix Multiply-Accumulate)", - .dependencies = featureSet(&[_]Feature{ - .zve32x, - }), - }; - result[@backingInt(Feature.experimental_zvvmtls)] = .{ - .llvm_name = "experimental-zvvmtls", - .description = "'Zvvmtls' (Matrix Tile Load/Store)", - .dependencies = featureSet(&[_]Feature{ - .zve32x, - }), - }; - result[@backingInt(Feature.experimental_zvvmttls)] = .{ - .llvm_name = "experimental-zvvmttls", - .description = "'Zvvmttls' (Transposing Matrix Tile Load/Store)", - .dependencies = featureSet(&[_]Feature{ - .zve32x, - }), - }; - result[@backingInt(Feature.experimental_zvzip)] = .{ - .llvm_name = "experimental-zvzip", - .description = "'Zvzip' (Vector Reordering Structured Data)", - .dependencies = featureSet(&[_]Feature{ - .zve32x, - }), - }; result[@backingInt(Feature.f)] = .{ .llvm_name = "f", .description = "'F' (Single-Precision Floating-Point)", @@ -727,11 +366,6 @@ pub const all_features = blk: { .zicsr, }), }; - result[@backingInt(Feature.forced_atomics)] = .{ - .llvm_name = "forced-atomics", - .description = "Assume that lock-free native-width atomics are available", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.fusion_add_load)] = .{ .llvm_name = "fusion-add-load", .description = "Enable ADD(.UW) + load macrofusion", @@ -849,26 +483,11 @@ pub const all_features = blk: { .zmmul, }), }; - result[@backingInt(Feature.mips_p8700)] = .{ - .llvm_name = "mips-p8700", - .description = "MIPS p8700 processor", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.no_default_unroll)] = .{ - .llvm_name = "no-default-unroll", - .description = "Disable default unroll preference", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.no_sink_splat_operands)] = .{ .llvm_name = "no-sink-splat-operands", .description = "Disable sink splat operands to enable .vx, .vf,.wx, and .wf instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.no_trailing_seq_cst_fence)] = .{ - .llvm_name = "no-trailing-seq-cst-fence", - .description = "Disable trailing fence for seq-cst store", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.optimized_nf2_segment_load_store)] = .{ .llvm_name = "optimized-nf2-segment-load-store", .description = "vlseg2eN.v and vsseg2eN.v are implemented as a wide memory op and shuffle", @@ -941,462 +560,6 @@ pub const all_features = blk: { .d, }), }; - result[@backingInt(Feature.relax)] = .{ - .llvm_name = "relax", - .description = "Enable Linker relaxation", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x1)] = .{ - .llvm_name = "reserve-x1", - .description = "Reserve X1", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x10)] = .{ - .llvm_name = "reserve-x10", - .description = "Reserve X10", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x11)] = .{ - .llvm_name = "reserve-x11", - .description = "Reserve X11", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x12)] = .{ - .llvm_name = "reserve-x12", - .description = "Reserve X12", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x13)] = .{ - .llvm_name = "reserve-x13", - .description = "Reserve X13", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x14)] = .{ - .llvm_name = "reserve-x14", - .description = "Reserve X14", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x15)] = .{ - .llvm_name = "reserve-x15", - .description = "Reserve X15", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x16)] = .{ - .llvm_name = "reserve-x16", - .description = "Reserve X16", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x17)] = .{ - .llvm_name = "reserve-x17", - .description = "Reserve X17", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x18)] = .{ - .llvm_name = "reserve-x18", - .description = "Reserve X18", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x19)] = .{ - .llvm_name = "reserve-x19", - .description = "Reserve X19", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x2)] = .{ - .llvm_name = "reserve-x2", - .description = "Reserve X2", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x20)] = .{ - .llvm_name = "reserve-x20", - .description = "Reserve X20", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x21)] = .{ - .llvm_name = "reserve-x21", - .description = "Reserve X21", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x22)] = .{ - .llvm_name = "reserve-x22", - .description = "Reserve X22", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x23)] = .{ - .llvm_name = "reserve-x23", - .description = "Reserve X23", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x24)] = .{ - .llvm_name = "reserve-x24", - .description = "Reserve X24", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x25)] = .{ - .llvm_name = "reserve-x25", - .description = "Reserve X25", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x26)] = .{ - .llvm_name = "reserve-x26", - .description = "Reserve X26", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x27)] = .{ - .llvm_name = "reserve-x27", - .description = "Reserve X27", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x28)] = .{ - .llvm_name = "reserve-x28", - .description = "Reserve X28", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x29)] = .{ - .llvm_name = "reserve-x29", - .description = "Reserve X29", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x3)] = .{ - .llvm_name = "reserve-x3", - .description = "Reserve X3", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x30)] = .{ - .llvm_name = "reserve-x30", - .description = "Reserve X30", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x31)] = .{ - .llvm_name = "reserve-x31", - .description = "Reserve X31", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x4)] = .{ - .llvm_name = "reserve-x4", - .description = "Reserve X4", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x5)] = .{ - .llvm_name = "reserve-x5", - .description = "Reserve X5", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x6)] = .{ - .llvm_name = "reserve-x6", - .description = "Reserve X6", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x7)] = .{ - .llvm_name = "reserve-x7", - .description = "Reserve X7", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x8)] = .{ - .llvm_name = "reserve-x8", - .description = "Reserve X8", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_x9)] = .{ - .llvm_name = "reserve-x9", - .description = "Reserve X9", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.rva20s64)] = .{ - .llvm_name = "rva20s64", - .description = "RISC-V rva20s64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .a, - .c, - .d, - .i, - .m, - .ssccptr, - .sstvala, - .sstvecd, - .svade, - .svbare, - .za128rs, - .ziccamoa, - .ziccif, - .zicclsm, - .ziccrse, - .zicntr, - .zifencei, - }), - }; - result[@backingInt(Feature.rva20u64)] = .{ - .llvm_name = "rva20u64", - .description = "RISC-V rva20u64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .a, - .c, - .d, - .i, - .m, - .za128rs, - .ziccamoa, - .ziccif, - .zicclsm, - .ziccrse, - .zicntr, - }), - }; - result[@backingInt(Feature.rva22s64)] = .{ - .llvm_name = "rva22s64", - .description = "RISC-V rva22s64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .a, - .b, - .c, - .d, - .i, - .m, - .ssccptr, - .sscounterenw, - .sstvala, - .sstvecd, - .svade, - .svbare, - .svinval, - .svpbmt, - .za64rs, - .zfhmin, - .zic64b, - .zicbom, - .zicbop, - .zicboz, - .ziccamoa, - .ziccif, - .zicclsm, - .ziccrse, - .zicntr, - .zifencei, - .zihintpause, - .zihpm, - .zkt, - }), - }; - result[@backingInt(Feature.rva22u64)] = .{ - .llvm_name = "rva22u64", - .description = "RISC-V rva22u64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .a, - .b, - .c, - .d, - .i, - .m, - .za64rs, - .zfhmin, - .zic64b, - .zicbom, - .zicbop, - .zicboz, - .ziccamoa, - .ziccif, - .zicclsm, - .ziccrse, - .zicntr, - .zihintpause, - .zihpm, - .zkt, - }), - }; - result[@backingInt(Feature.rva23s64)] = .{ - .llvm_name = "rva23s64", - .description = "RISC-V rva23s64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .a, - .b, - .c, - .i, - .m, - .sha, - .ssccptr, - .sscofpmf, - .sscounterenw, - .ssnpm, - .sstc, - .sstvala, - .sstvecd, - .ssu64xl, - .supm, - .svade, - .svbare, - .svinval, - .svnapot, - .svpbmt, - .v, - .za64rs, - .zawrs, - .zcb, - .zcmop, - .zfa, - .zfhmin, - .zic64b, - .zicbom, - .zicbop, - .zicboz, - .ziccamoa, - .ziccif, - .zicclsm, - .ziccrse, - .zicntr, - .zicond, - .zifencei, - .zihintntl, - .zihintpause, - .zihpm, - .zimop, - .zkt, - .zvbb, - .zvfhmin, - .zvkt, - }), - }; - result[@backingInt(Feature.rva23u64)] = .{ - .llvm_name = "rva23u64", - .description = "RISC-V rva23u64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .a, - .b, - .c, - .i, - .m, - .supm, - .v, - .za64rs, - .zawrs, - .zcb, - .zcmop, - .zfa, - .zfhmin, - .zic64b, - .zicbom, - .zicbop, - .zicboz, - .ziccamoa, - .ziccif, - .zicclsm, - .ziccrse, - .zicntr, - .zicond, - .zihintntl, - .zihintpause, - .zihpm, - .zimop, - .zkt, - .zvbb, - .zvfhmin, - .zvkt, - }), - }; - result[@backingInt(Feature.rvb23s64)] = .{ - .llvm_name = "rvb23s64", - .description = "RISC-V rvb23s64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .a, - .b, - .c, - .d, - .i, - .m, - .ssccptr, - .sscofpmf, - .sscounterenw, - .sstc, - .sstvala, - .sstvecd, - .ssu64xl, - .svade, - .svbare, - .svinval, - .svnapot, - .svpbmt, - .za64rs, - .zawrs, - .zcb, - .zcmop, - .zfa, - .zic64b, - .zicbom, - .zicbop, - .zicboz, - .ziccamoa, - .ziccif, - .zicclsm, - .ziccrse, - .zicntr, - .zicond, - .zifencei, - .zihintntl, - .zihintpause, - .zihpm, - .zimop, - .zkt, - }), - }; - result[@backingInt(Feature.rvb23u64)] = .{ - .llvm_name = "rvb23u64", - .description = "RISC-V rvb23u64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .a, - .b, - .c, - .d, - .i, - .m, - .za64rs, - .zawrs, - .zcb, - .zcmop, - .zfa, - .zic64b, - .zicbom, - .zicbop, - .zicboz, - .ziccamoa, - .ziccif, - .zicclsm, - .ziccrse, - .zicntr, - .zicond, - .zihintntl, - .zihintpause, - .zihpm, - .zimop, - .zkt, - }), - }; - result[@backingInt(Feature.rvi20u32)] = .{ - .llvm_name = "rvi20u32", - .description = "RISC-V rvi20u32 profile", - .dependencies = featureSet(&[_]Feature{ - .@"32bit", - .i, - }), - }; - result[@backingInt(Feature.rvi20u64)] = .{ - .llvm_name = "rvi20u64", - .description = "RISC-V rvi20u64 profile", - .dependencies = featureSet(&[_]Feature{ - .@"64bit", - .i, - }), - }; - result[@backingInt(Feature.save_restore)] = .{ - .llvm_name = "save-restore", - .description = "Enable save/restore", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.sdext)] = .{ .llvm_name = "sdext", .description = "'Sdext' (External debugger)", @@ -1687,26 +850,16 @@ pub const all_features = blk: { .description = "'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.tagged_globals)] = .{ - .llvm_name = "tagged-globals", - .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.unaligned_scalar_mem)] = .{ + result[@backingInt(Feature.unaligned_access)] = .{ .llvm_name = "unaligned-scalar-mem", .description = "Has reasonably performant unaligned scalar loads and stores", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.unaligned_vector_mem)] = .{ + result[@backingInt(Feature.unaligned_vector_access)] = .{ .llvm_name = "unaligned-vector-mem", .description = "Has reasonably performant unaligned vector loads and stores", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.use_postra_scheduler)] = .{ - .llvm_name = "use-postra-scheduler", - .description = "Schedule again after register allocation", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.v)] = .{ .llvm_name = "v", .description = "'V' (Vector Extension for Application Processors)", @@ -1715,11 +868,6 @@ pub const all_features = blk: { .zvl128b, }), }; - result[@backingInt(Feature.ventana_veyron)] = .{ - .llvm_name = "ventana-veyron", - .description = "Ventana Veyron-Series processors", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.vl_dependent_latency)] = .{ .llvm_name = "vl-dependent-latency", .description = "Latency of vector instructions is dependent on the dynamic value of vl", @@ -1784,15 +932,6 @@ pub const all_features = blk: { .zve32x, }), }; - result[@backingInt(Feature.xcheriot)] = .{ - .llvm_name = "xcheriot", - .description = "'XCheriot' (CHERIoT extension)", - .dependencies = featureSet(&[_]Feature{ - .e, - .m, - .zca, - }), - }; result[@backingInt(Feature.xcvalu)] = .{ .llvm_name = "xcvalu", .description = "'XCValu' (CORE-V ALU Operations)", @@ -2936,10 +2075,7 @@ pub const cpu = struct { .name = "andes_45_series", .llvm_name = "andes-45-series", .features = featureSet(&[_]Feature{ - .andes45, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, }), }; pub const andes_a25: CpuModel = .{ @@ -2962,14 +2098,11 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"32bit", .a, - .andes45, .c, .d, .i, .m, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, .xandesperf, .zifencei, }), @@ -2994,14 +2127,11 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .a, - .andes45, .c, .d, .i, .m, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, .xandesperf, .zifencei, }), @@ -3012,13 +2142,10 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .a, - .andes45, .c, .i, .m, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, .v, .xandesperf, .zifencei, @@ -3030,14 +2157,11 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"32bit", .a, - .andes45, .c, .d, .i, .m, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, .xandesperf, .zifencei, }), @@ -3048,42 +2172,15 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .a, - .andes45, .c, .d, .i, .m, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, .xandesperf, .zifencei, }), }; - pub const baseline_rv32: CpuModel = .{ - .name = "baseline_rv32", - .llvm_name = null, - .features = featureSet(&[_]Feature{ - .@"32bit", - .a, - .c, - .d, - .i, - .m, - }), - }; - pub const baseline_rv64: CpuModel = .{ - .name = "baseline_rv64", - .llvm_name = null, - .features = featureSet(&[_]Feature{ - .@"64bit", - .a, - .c, - .d, - .i, - .m, - }), - }; pub const et_soc1: CpuModel = .{ .name = "et_soc1", .llvm_name = "et-soc1", @@ -3094,36 +2191,6 @@ pub const cpu = struct { .xaifet, }), }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{}), - }; - pub const generic_ooo: CpuModel = .{ - .name = "generic_ooo", - .llvm_name = "generic-ooo", - .features = featureSet(&[_]Feature{}), - }; - pub const generic_rv32: CpuModel = .{ - .name = "generic_rv32", - .llvm_name = "generic-rv32", - .features = featureSet(&[_]Feature{ - .@"32bit", - .enable_select_opt, - .i, - .optimized_nf2_segment_load_store, - }), - }; - pub const generic_rv64: CpuModel = .{ - .name = "generic_rv64", - .llvm_name = "generic-rv64", - .features = featureSet(&[_]Feature{ - .@"64bit", - .enable_select_opt, - .i, - .optimized_nf2_segment_load_store, - }), - }; pub const mips_p8700: CpuModel = .{ .name = "mips_p8700", .llvm_name = "mips-p8700", @@ -3134,7 +2201,6 @@ pub const cpu = struct { .d, .i, .m, - .mips_p8700, .xmipscbop, .xmipscmov, .xmipsexectl, @@ -3188,13 +2254,501 @@ pub const cpu = struct { .zifencei, }), }; + pub const rv32e: CpuModel = .{ + .name = "rv32e", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .e, + }), + }; + pub const rv32ec: CpuModel = .{ + .name = "rv32ec", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .c, + .e, + }), + }; + pub const rv32emc: CpuModel = .{ + .name = "rv32emc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .c, + .e, + .m, + }), + }; + pub const rv32gc: CpuModel = .{ + .name = "rv32gc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .a, + .c, + .i, + .m, + .zcd, + .zcf, + .zifencei, + }), + }; + pub const rv32i: CpuModel = .{ + .name = "rv32i", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .i, + }), + }; + pub const rv32im: CpuModel = .{ + .name = "rv32im", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .i, + .m, + }), + }; + pub const rv32ima: CpuModel = .{ + .name = "rv32ima", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .a, + .i, + .m, + }), + }; + pub const rv32imac: CpuModel = .{ + .name = "rv32imac", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .a, + .c, + .i, + .m, + }), + }; + pub const rv32imafc: CpuModel = .{ + .name = "rv32imafc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .a, + .c, + .i, + .m, + .zcf, + }), + }; + pub const rv32imafdc: CpuModel = .{ + .name = "rv32imafdc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .a, + .c, + .i, + .m, + .zcd, + .zcf, + }), + }; + pub const rv32imc: CpuModel = .{ + .name = "rv32imc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .c, + .i, + .m, + }), + }; + pub const rv64gc: CpuModel = .{ + .name = "rv64gc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .i, + .m, + .zcd, + .zifencei, + }), + }; + pub const rv64i: CpuModel = .{ + .name = "rv64i", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .i, + }), + }; + pub const rv64im: CpuModel = .{ + .name = "rv64im", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .i, + .m, + }), + }; + pub const rv64ima: CpuModel = .{ + .name = "rv64ima", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .i, + .m, + }), + }; + pub const rv64imac: CpuModel = .{ + .name = "rv64imac", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .i, + .m, + }), + }; + pub const rv64imafc: CpuModel = .{ + .name = "rv64imafc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .f, + .i, + .m, + }), + }; + pub const rv64imafdc: CpuModel = .{ + .name = "rv64imafdc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .i, + .m, + .zcd, + }), + }; + pub const rv64imc: CpuModel = .{ + .name = "rv64imc", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .c, + .i, + .m, + }), + }; + pub const rva20s64: CpuModel = .{ + .name = "rva20s64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .i, + .m, + .ssccptr, + .sstvala, + .sstvecd, + .svade, + .svbare, + .za128rs, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zifencei, + }), + }; + pub const rva20u64: CpuModel = .{ + .name = "rva20u64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .c, + .d, + .i, + .m, + .za128rs, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + }), + }; + pub const rva22s64: CpuModel = .{ + .name = "rva22s64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .d, + .i, + .m, + .ssccptr, + .sscounterenw, + .sstvala, + .sstvecd, + .svade, + .svbare, + .svinval, + .svpbmt, + .za64rs, + .zfhmin, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zifencei, + .zihintpause, + .zihpm, + .zkt, + }), + }; + pub const rva22u64: CpuModel = .{ + .name = "rva22u64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .d, + .i, + .m, + .za64rs, + .zfhmin, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zihintpause, + .zihpm, + .zkt, + }), + }; + pub const rva23s64: CpuModel = .{ + .name = "rva23s64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .i, + .m, + .sha, + .ssccptr, + .sscofpmf, + .sscounterenw, + .ssnpm, + .sstc, + .sstvala, + .sstvecd, + .ssu64xl, + .supm, + .svade, + .svbare, + .svinval, + .svnapot, + .svpbmt, + .v, + .za64rs, + .zawrs, + .zcb, + .zcmop, + .zfa, + .zfhmin, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + .zvbb, + .zvfhmin, + .zvkt, + }), + }; + pub const rva23u64: CpuModel = .{ + .name = "rva23u64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .i, + .m, + .supm, + .v, + .za64rs, + .zawrs, + .zcb, + .zcmop, + .zfa, + .zfhmin, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + .zvbb, + .zvfhmin, + .zvkt, + }), + }; + pub const rvb23s64: CpuModel = .{ + .name = "rvb23s64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .d, + .i, + .m, + .ssccptr, + .sscofpmf, + .sscounterenw, + .sstc, + .sstvala, + .sstvecd, + .ssu64xl, + .svade, + .svbare, + .svinval, + .svnapot, + .svpbmt, + .za64rs, + .zawrs, + .zcb, + .zcmop, + .zfa, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zifencei, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + }), + }; + pub const rvb23u64: CpuModel = .{ + .name = "rvb23u64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .a, + .b, + .c, + .d, + .i, + .m, + .za64rs, + .zawrs, + .zcb, + .zcmop, + .zfa, + .zic64b, + .zicbom, + .zicbop, + .zicboz, + .ziccamoa, + .ziccif, + .zicclsm, + .ziccrse, + .zicntr, + .zicond, + .zihintntl, + .zihintpause, + .zihpm, + .zimop, + .zkt, + }), + }; + pub const rvi20u32: CpuModel = .{ + .name = "rvi20u32", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"32bit", + .i, + }), + }; + pub const rvi20u64: CpuModel = .{ + .name = "rvi20u64", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .@"64bit", + .i, + }), + }; pub const sifive_7_series: CpuModel = .{ .name = "sifive_7_series", .llvm_name = "sifive-7-series", .features = featureSet(&[_]Feature{ - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, }), }; pub const sifive_e20: CpuModel = .{ @@ -3271,9 +2825,7 @@ pub const cpu = struct { .f, .i, .m, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, .zifencei, }), }; @@ -3291,10 +2843,8 @@ pub const cpu = struct { .fusion_lui_addi, .i, .m, - .no_default_unroll, - .unaligned_scalar_mem, - .unaligned_vector_mem, - .use_postra_scheduler, + .unaligned_access, + .unaligned_vector_access, .za64rs, .zfhmin, .zic64b, @@ -3325,11 +2875,9 @@ pub const cpu = struct { .fusion_lui_addi, .i, .m, - .no_default_unroll, .no_sink_splat_operands, - .unaligned_scalar_mem, - .unaligned_vector_mem, - .use_postra_scheduler, + .unaligned_access, + .unaligned_vector_access, .v, .vxrm_pipeline_flush, .xsifivecdiscarddlone, @@ -3365,13 +2913,10 @@ pub const cpu = struct { .c, .conditional_cmv_fusion, .d, - .enable_select_opt, .fusion_auipc_addi, .fusion_lui_addi, .i, .m, - .no_default_unroll, - .use_postra_scheduler, .zba, .zbb, .zifencei, @@ -3390,11 +2935,9 @@ pub const cpu = struct { .fusion_lui_addi, .i, .m, - .no_default_unroll, .no_sink_splat_operands, - .unaligned_scalar_mem, - .unaligned_vector_mem, - .use_postra_scheduler, + .unaligned_access, + .unaligned_vector_access, .v, .vxrm_pipeline_flush, .za64rs, @@ -3432,12 +2975,10 @@ pub const cpu = struct { .fusion_lui_addi, .i, .m, - .no_default_unroll, .no_sink_splat_operands, .supm, - .unaligned_scalar_mem, - .unaligned_vector_mem, - .use_postra_scheduler, + .unaligned_access, + .unaligned_vector_access, .v, .vxrm_pipeline_flush, .za64rs, @@ -3522,9 +3063,7 @@ pub const cpu = struct { .d, .i, .m, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, .zifencei, .zihintpause, }), @@ -3552,9 +3091,7 @@ pub const cpu = struct { .d, .i, .m, - .no_default_unroll, .short_forward_branch_ialu, - .use_postra_scheduler, .zifencei, }), }; @@ -3567,16 +3104,11 @@ pub const cpu = struct { .b, .c, .dlen_factor_2, - .experimental_zicfilp, - .experimental_zvdot4a8i, - .experimental_zvfbfa, .i, .m, - .no_default_unroll, .optimized_nf2_segment_load_store, .optimized_zero_stride_load, .short_forward_branch_ialu, - .use_postra_scheduler, .vl_dependent_latency, .xsfcease, .zawrs, @@ -3611,16 +3143,11 @@ pub const cpu = struct { .b, .c, .dlen_factor_2, - .experimental_zicfilp, - .experimental_zvdot4a8i, - .experimental_zvfbfa, .i, .m, - .no_default_unroll, .optimized_nf2_segment_load_store, .optimized_zero_stride_load, .short_forward_branch_ialu, - .use_postra_scheduler, .v, .vl_dependent_latency, .xsfcease, @@ -3665,11 +3192,9 @@ pub const cpu = struct { .dlen_factor_2, .i, .m, - .no_default_unroll, .optimized_nf2_segment_load_store, .optimized_zero_stride_load, .short_forward_branch_ialu, - .use_postra_scheduler, .v, .vl_dependent_latency, .zba, @@ -3689,16 +3214,12 @@ pub const cpu = struct { .b, .c, .dlen_factor_2, - .experimental_zicfilp, - .experimental_zicfiss, .i, .m, - .no_default_unroll, .optimized_nf2_segment_load_store, .optimized_zero_stride_load, .short_forward_branch_ialu, .single_element_vec_fp64, - .use_postra_scheduler, .v, .vl_dependent_latency, .xsifivecdiscarddlone, @@ -3722,6 +3243,7 @@ pub const cpu = struct { .zihintntl, .zihintpause, .zihpm, + .zimop, .zkr, .zkt, .zvbb, @@ -3763,7 +3285,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, + .unaligned_access, .v, .vxrm_pipeline_flush, .xsmtvdotii, @@ -3816,7 +3338,6 @@ pub const cpu = struct { .fusion_shift_bit_extract, .i, .m, - .no_default_unroll, .optimized_nf2_segment_load_store, .optimized_nf3_segment_load_store, .optimized_nf4_segment_load_store, @@ -3839,7 +3360,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, + .unaligned_access, .v, .vxrm_pipeline_flush, .xsmtvdot, @@ -3884,7 +3405,6 @@ pub const cpu = struct { .b, .c, .dlen_factor_2, - .enable_select_opt, .i, .m, .optimized_nf2_segment_load_store, @@ -3902,7 +3422,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, + .unaligned_access, .v, .vxrm_pipeline_flush, .xsmtvdot, @@ -3935,7 +3455,6 @@ pub const cpu = struct { .@"32bit", .c, .i, - .no_default_unroll, .zicsr, .zifencei, }), @@ -3948,7 +3467,6 @@ pub const cpu = struct { .c, .i, .m, - .no_default_unroll, .zicsr, .zifencei, }), @@ -3961,8 +3479,6 @@ pub const cpu = struct { .c, .i, .m, - .no_default_unroll, - .use_postra_scheduler, .zicsr, .zifencei, }), @@ -3976,8 +3492,6 @@ pub const cpu = struct { .c, .i, .m, - .no_default_unroll, - .use_postra_scheduler, .zicsr, .zifencei, }), @@ -3991,8 +3505,6 @@ pub const cpu = struct { .d, .i, .m, - .no_default_unroll, - .use_postra_scheduler, .zifencei, }), }; @@ -4006,8 +3518,6 @@ pub const cpu = struct { .d, .i, .m, - .no_default_unroll, - .use_postra_scheduler, .zifencei, }), }; @@ -4021,8 +3531,6 @@ pub const cpu = struct { .d, .i, .m, - .no_default_unroll, - .use_postra_scheduler, .zifencei, }), }; @@ -4036,8 +3544,6 @@ pub const cpu = struct { .d, .i, .m, - .no_default_unroll, - .use_postra_scheduler, .zifencei, }), }; @@ -4050,8 +3556,6 @@ pub const cpu = struct { .c, .i, .m, - .no_default_unroll, - .use_postra_scheduler, .v, .zba, .zbb, @@ -4072,7 +3576,6 @@ pub const cpu = struct { .i, .log_vrgather, .m, - .no_default_unroll, .optimized_nf2_segment_load_store, .optimized_nf3_segment_load_store, .optimized_nf4_segment_load_store, @@ -4103,9 +3606,8 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, - .unaligned_vector_mem, - .use_postra_scheduler, + .unaligned_access, + .unaligned_vector_access, .v, .za64rs, .zawrs, @@ -4146,9 +3648,6 @@ pub const cpu = struct { .a, .c, .d, - .disable_misched_load_clustering, - .disable_postmisched_load_clustering, - .disable_postmisched_store_clustering, .fusion_add_load, .fusion_auipc_addi, .fusion_auipc_load, @@ -4159,7 +3658,6 @@ pub const cpu = struct { .fusion_zextw, .i, .m, - .ventana_veyron, .xventanacondops, .zba, .zbb, @@ -4187,7 +3685,6 @@ pub const cpu = struct { .fusion_zextw, .i, .m, - .no_default_unroll, .sha, .smaia, .smcsrind, @@ -4260,7 +3757,6 @@ pub const cpu = struct { .fusion_zextw, .i, .m, - .no_default_unroll, .svinval, .zba, .zbb, @@ -4296,8 +3792,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, - .use_postra_scheduler, + .unaligned_access, .vxrm_pipeline_flush, .xtheadba, .xtheadbb, @@ -4358,8 +3853,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, - .use_postra_scheduler, + .unaligned_access, .vxrm_pipeline_flush, .xtheadba, .xtheadbb, diff --git a/lib/std/Target/s390x.zig b/lib/std/Target/s390x.zig index 5607f0362e..3a637c9f1b 100644 --- a/lib/std/Target/s390x.zig +++ b/lib/std/Target/s390x.zig @@ -5,55 +5,52 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { - backchain, - bear_enhancement, - concurrent_functions, - deflate_conversion, - dfp_packed_conversion, - dfp_zoned_conversion, - distinct_ops, - enhanced_dat_2, - enhanced_sort, - execution_hint, - fast_serialization, - fp_extension, - guarded_storage, - high_word, - insert_reference_bits_multiple, - interlocked_access1, - load_and_trap, - load_and_zero_rightmost_byte, - load_store_on_cond, - load_store_on_cond_2, - message_security_assist_extension12, - message_security_assist_extension3, - message_security_assist_extension4, - message_security_assist_extension5, - message_security_assist_extension7, - message_security_assist_extension8, - message_security_assist_extension9, - miscellaneous_extensions, - miscellaneous_extensions_2, - miscellaneous_extensions_3, - miscellaneous_extensions_4, - nnp_assist, - population_count, - processor_activity_instrumentation, - processor_assist, - reset_dat_protection, - reset_reference_bits_multiple, - soft_float, - test_pending_external_interruption, - transactional_execution, - unaligned_symbols, - vector, - vector_enhancements_1, - vector_enhancements_2, - vector_enhancements_3, - vector_packed_decimal, - vector_packed_decimal_enhancement, - vector_packed_decimal_enhancement_2, - vector_packed_decimal_enhancement_3, + beareh, + ccf, + deflate, + dfppc, + dfpzc, + distops, + edat2, + esort, + exhint, + fbcrs, + fpe, + gs, + hiword, + iacc, + irbm, + lat, + loc, + loc2, + lzr, + minste, + minste2, + minste3, + minste4, + msa12, + msa3, + msa4, + msa5, + msa7, + msa8, + msa9, + nnpa, + pai, + popcnt, + ppa, + rdp, + rrbm, + te, + tpei, + vx, + vxeh, + vxeh2, + vxeh3, + vxpd, + vxpdeh, + vxpdeh2, + vxpdeh3, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -65,250 +62,270 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; - result[@backingInt(Feature.backchain)] = .{ - .llvm_name = "backchain", - .description = "Store the address of the caller's frame into the callee's stack frame", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.bear_enhancement)] = .{ + result[@backingInt(Feature.beareh)] = .{ .llvm_name = "bear-enhancement", .description = "Assume that the BEAR-enhancement facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.concurrent_functions)] = .{ + result[@backingInt(Feature.ccf)] = .{ .llvm_name = "concurrent-functions", .description = "Assume that the concurrent-functions facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.deflate_conversion)] = .{ + result[@backingInt(Feature.deflate)] = .{ .llvm_name = "deflate-conversion", .description = "Assume that the deflate-conversion facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.dfp_packed_conversion)] = .{ + result[@backingInt(Feature.dfppc)] = .{ .llvm_name = "dfp-packed-conversion", .description = "Assume that the DFP packed-conversion facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.dfp_zoned_conversion)] = .{ + result[@backingInt(Feature.dfpzc)] = .{ .llvm_name = "dfp-zoned-conversion", .description = "Assume that the DFP zoned-conversion facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.distinct_ops)] = .{ + result[@backingInt(Feature.distops)] = .{ .llvm_name = "distinct-ops", .description = "Assume that the distinct-operands facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.enhanced_dat_2)] = .{ + result[@backingInt(Feature.edat2)] = .{ .llvm_name = "enhanced-dat-2", .description = "Assume that the enhanced-DAT facility 2 is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.enhanced_sort)] = .{ + result[@backingInt(Feature.esort)] = .{ .llvm_name = "enhanced-sort", .description = "Assume that the enhanced-sort facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.execution_hint)] = .{ + result[@backingInt(Feature.exhint)] = .{ .llvm_name = "execution-hint", .description = "Assume that the execution-hint facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.fast_serialization)] = .{ + result[@backingInt(Feature.fbcrs)] = .{ .llvm_name = "fast-serialization", .description = "Assume that the fast-serialization facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.fp_extension)] = .{ + result[@backingInt(Feature.fpe)] = .{ .llvm_name = "fp-extension", .description = "Assume that the floating-point extension facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.guarded_storage)] = .{ + result[@backingInt(Feature.gs)] = .{ .llvm_name = "guarded-storage", .description = "Assume that the guarded-storage facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.high_word)] = .{ + result[@backingInt(Feature.hiword)] = .{ .llvm_name = "high-word", .description = "Assume that the high-word facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.insert_reference_bits_multiple)] = .{ - .llvm_name = "insert-reference-bits-multiple", - .description = "Assume that the insert-reference-bits-multiple facility is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.interlocked_access1)] = .{ + result[@backingInt(Feature.iacc)] = .{ .llvm_name = "interlocked-access1", .description = "Assume that interlocked-access facility 1 is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.load_and_trap)] = .{ + result[@backingInt(Feature.irbm)] = .{ + .llvm_name = "insert-reference-bits-multiple", + .description = "Assume that the insert-reference-bits-multiple facility is installed", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.lat)] = .{ .llvm_name = "load-and-trap", .description = "Assume that the load-and-trap facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.load_and_zero_rightmost_byte)] = .{ - .llvm_name = "load-and-zero-rightmost-byte", - .description = "Assume that the load-and-zero-rightmost-byte facility is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.load_store_on_cond)] = .{ + result[@backingInt(Feature.loc)] = .{ .llvm_name = "load-store-on-cond", .description = "Assume that the load/store-on-condition facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.load_store_on_cond_2)] = .{ + result[@backingInt(Feature.loc2)] = .{ .llvm_name = "load-store-on-cond-2", .description = "Assume that the load/store-on-condition facility 2 is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.message_security_assist_extension12)] = .{ - .llvm_name = "message-security-assist-extension12", - .description = "Assume that the message-security-assist extension facility 12 is installed", + result[@backingInt(Feature.lzr)] = .{ + .llvm_name = "load-and-zero-rightmost-byte", + .description = "Assume that the load-and-zero-rightmost-byte facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.message_security_assist_extension3)] = .{ - .llvm_name = "message-security-assist-extension3", - .description = "Assume that the message-security-assist extension facility 3 is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.message_security_assist_extension4)] = .{ - .llvm_name = "message-security-assist-extension4", - .description = "Assume that the message-security-assist extension facility 4 is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.message_security_assist_extension5)] = .{ - .llvm_name = "message-security-assist-extension5", - .description = "Assume that the message-security-assist extension facility 5 is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.message_security_assist_extension7)] = .{ - .llvm_name = "message-security-assist-extension7", - .description = "Assume that the message-security-assist extension facility 7 is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.message_security_assist_extension8)] = .{ - .llvm_name = "message-security-assist-extension8", - .description = "Assume that the message-security-assist extension facility 8 is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.message_security_assist_extension9)] = .{ - .llvm_name = "message-security-assist-extension9", - .description = "Assume that the message-security-assist extension facility 9 is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.miscellaneous_extensions)] = .{ + result[@backingInt(Feature.minste)] = .{ .llvm_name = "miscellaneous-extensions", .description = "Assume that the miscellaneous-extensions facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.miscellaneous_extensions_2)] = .{ + result[@backingInt(Feature.minste2)] = .{ .llvm_name = "miscellaneous-extensions-2", .description = "Assume that the miscellaneous-extensions facility 2 is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.miscellaneous_extensions_3)] = .{ + result[@backingInt(Feature.minste3)] = .{ .llvm_name = "miscellaneous-extensions-3", .description = "Assume that the miscellaneous-extensions facility 3 is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .distops, + .fbcrs, + .hiword, + .iacc, + .loc, + .popcnt, + }), }; - result[@backingInt(Feature.miscellaneous_extensions_4)] = .{ + result[@backingInt(Feature.minste4)] = .{ .llvm_name = "miscellaneous-extensions-4", .description = "Assume that the miscellaneous-extensions facility 4 is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.nnp_assist)] = .{ + result[@backingInt(Feature.msa12)] = .{ + .llvm_name = "message-security-assist-extension12", + .description = "Assume that the message-security-assist extension facility 12 is installed", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.msa3)] = .{ + .llvm_name = "message-security-assist-extension3", + .description = "Assume that the message-security-assist extension facility 3 is installed", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.msa4)] = .{ + .llvm_name = "message-security-assist-extension4", + .description = "Assume that the message-security-assist extension facility 4 is installed", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.msa5)] = .{ + .llvm_name = "message-security-assist-extension5", + .description = "Assume that the message-security-assist extension facility 5 is installed", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.msa7)] = .{ + .llvm_name = "message-security-assist-extension7", + .description = "Assume that the message-security-assist extension facility 7 is installed", + .dependencies = featureSet(&[_]Feature{ + .msa5, + }), + }; + result[@backingInt(Feature.msa8)] = .{ + .llvm_name = "message-security-assist-extension8", + .description = "Assume that the message-security-assist extension facility 8 is installed", + .dependencies = featureSet(&[_]Feature{ + .msa3, + }), + }; + result[@backingInt(Feature.msa9)] = .{ + .llvm_name = "message-security-assist-extension9", + .description = "Assume that the message-security-assist extension facility 9 is installed", + .dependencies = featureSet(&[_]Feature{ + .msa3, + .msa4, + }), + }; + result[@backingInt(Feature.nnpa)] = .{ .llvm_name = "nnp-assist", .description = "Assume that the NNP-assist facility is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .vx, + }), }; - result[@backingInt(Feature.population_count)] = .{ - .llvm_name = "population-count", - .description = "Assume that the population-count facility is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.processor_activity_instrumentation)] = .{ + result[@backingInt(Feature.pai)] = .{ .llvm_name = "processor-activity-instrumentation", .description = "Assume that the processor-activity-instrumentation facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.processor_assist)] = .{ + result[@backingInt(Feature.popcnt)] = .{ + .llvm_name = "population-count", + .description = "Assume that the population-count facility is installed", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.ppa)] = .{ .llvm_name = "processor-assist", .description = "Assume that the processor-assist facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.reset_dat_protection)] = .{ + result[@backingInt(Feature.rdp)] = .{ .llvm_name = "reset-dat-protection", .description = "Assume that the reset-DAT-protection facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.reset_reference_bits_multiple)] = .{ + result[@backingInt(Feature.rrbm)] = .{ .llvm_name = "reset-reference-bits-multiple", .description = "Assume that the reset-reference-bits-multiple facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.soft_float)] = .{ - .llvm_name = "soft-float", - .description = "Use software emulation for floating point", - .dependencies = featureSet(&[_]Feature{}), + result[@backingInt(Feature.te)] = .{ + .llvm_name = "transactional-execution", + .description = "Assume that the transactional-execution facility is installed", + .dependencies = featureSet(&[_]Feature{ + .exhint, + .lat, + .minste, + .ppa, + }), }; - result[@backingInt(Feature.test_pending_external_interruption)] = .{ + result[@backingInt(Feature.tpei)] = .{ .llvm_name = "test-pending-external-interruption", .description = "Assume that the test-pending-external-interruption facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.transactional_execution)] = .{ - .llvm_name = "transactional-execution", - .description = "Assume that the transactional-execution facility is installed", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.unaligned_symbols)] = .{ - .llvm_name = "unaligned-symbols", - .description = "Don't apply the ABI minimum alignment to external symbols.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.vector)] = .{ + result[@backingInt(Feature.vx)] = .{ .llvm_name = "vector", .description = "Assume that the vectory facility is installed", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.vector_enhancements_1)] = .{ + result[@backingInt(Feature.vxeh)] = .{ .llvm_name = "vector-enhancements-1", .description = "Assume that the vector enhancements facility 1 is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .vx, + }), }; - result[@backingInt(Feature.vector_enhancements_2)] = .{ + result[@backingInt(Feature.vxeh2)] = .{ .llvm_name = "vector-enhancements-2", .description = "Assume that the vector enhancements facility 2 is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .vxeh, + }), }; - result[@backingInt(Feature.vector_enhancements_3)] = .{ + result[@backingInt(Feature.vxeh3)] = .{ .llvm_name = "vector-enhancements-3", .description = "Assume that the vector enhancements facility 3 is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .vxeh2, + }), }; - result[@backingInt(Feature.vector_packed_decimal)] = .{ + result[@backingInt(Feature.vxpd)] = .{ .llvm_name = "vector-packed-decimal", .description = "Assume that the vector packed decimal facility is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .vx, + }), }; - result[@backingInt(Feature.vector_packed_decimal_enhancement)] = .{ + result[@backingInt(Feature.vxpdeh)] = .{ .llvm_name = "vector-packed-decimal-enhancement", .description = "Assume that the vector packed decimal enhancement facility is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .vxpd, + }), }; - result[@backingInt(Feature.vector_packed_decimal_enhancement_2)] = .{ + result[@backingInt(Feature.vxpdeh2)] = .{ .llvm_name = "vector-packed-decimal-enhancement-2", .description = "Assume that the vector packed decimal enhancement facility 2 is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .vxpdeh, + }), }; - result[@backingInt(Feature.vector_packed_decimal_enhancement_3)] = .{ + result[@backingInt(Feature.vxpdeh3)] = .{ .llvm_name = "vector-packed-decimal-enhancement-3", .description = "Assume that the vector packed decimal enhancement facility 3 is installed", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .vxpdeh2, + }), }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { @@ -323,228 +340,161 @@ pub const cpu = struct { .name = "arch10", .llvm_name = "arch10", .features = featureSet(&[_]Feature{ - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .execution_hint, - .fast_serialization, - .fp_extension, - .high_word, - .interlocked_access1, - .load_and_trap, - .load_store_on_cond, - .message_security_assist_extension3, - .message_security_assist_extension4, - .miscellaneous_extensions, - .population_count, - .processor_assist, - .reset_reference_bits_multiple, - .transactional_execution, + .dfpzc, + .distops, + .edat2, + .fbcrs, + .fpe, + .hiword, + .iacc, + .loc, + .msa3, + .msa4, + .popcnt, + .rrbm, + .te, }), }; pub const arch11: CpuModel = .{ .name = "arch11", .llvm_name = "arch11", .features = featureSet(&[_]Feature{ - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .execution_hint, - .fast_serialization, - .fp_extension, - .high_word, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .miscellaneous_extensions, - .population_count, - .processor_assist, - .reset_reference_bits_multiple, - .transactional_execution, - .vector, + .dfppc, + .dfpzc, + .distops, + .edat2, + .fbcrs, + .fpe, + .hiword, + .iacc, + .loc, + .loc2, + .lzr, + .msa3, + .msa4, + .msa5, + .popcnt, + .rrbm, + .te, + .vx, }), }; pub const arch12: CpuModel = .{ .name = "arch12", .llvm_name = "arch12", .features = featureSet(&[_]Feature{ - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .execution_hint, - .fast_serialization, - .fp_extension, - .guarded_storage, - .high_word, - .insert_reference_bits_multiple, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .message_security_assist_extension7, - .message_security_assist_extension8, - .miscellaneous_extensions, - .miscellaneous_extensions_2, - .population_count, - .processor_assist, - .reset_reference_bits_multiple, - .test_pending_external_interruption, - .transactional_execution, - .vector, - .vector_enhancements_1, - .vector_packed_decimal, + .dfppc, + .dfpzc, + .distops, + .edat2, + .fbcrs, + .fpe, + .gs, + .hiword, + .iacc, + .irbm, + .loc, + .loc2, + .lzr, + .minste2, + .msa4, + .msa7, + .msa8, + .popcnt, + .rrbm, + .te, + .tpei, + .vxeh, + .vxpd, }), }; pub const arch13: CpuModel = .{ .name = "arch13", .llvm_name = "arch13", .features = featureSet(&[_]Feature{ - .deflate_conversion, - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .enhanced_sort, - .execution_hint, - .fast_serialization, - .fp_extension, - .guarded_storage, - .high_word, - .insert_reference_bits_multiple, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .message_security_assist_extension7, - .message_security_assist_extension8, - .message_security_assist_extension9, - .miscellaneous_extensions, - .miscellaneous_extensions_2, - .miscellaneous_extensions_3, - .population_count, - .processor_assist, - .reset_reference_bits_multiple, - .test_pending_external_interruption, - .transactional_execution, - .vector, - .vector_enhancements_1, - .vector_enhancements_2, - .vector_packed_decimal, - .vector_packed_decimal_enhancement, + .deflate, + .dfppc, + .dfpzc, + .edat2, + .esort, + .fpe, + .gs, + .irbm, + .loc2, + .lzr, + .minste2, + .minste3, + .msa7, + .msa8, + .msa9, + .rrbm, + .te, + .tpei, + .vxeh2, + .vxpdeh, }), }; pub const arch14: CpuModel = .{ .name = "arch14", .llvm_name = "arch14", .features = featureSet(&[_]Feature{ - .bear_enhancement, - .deflate_conversion, - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .enhanced_sort, - .execution_hint, - .fast_serialization, - .fp_extension, - .guarded_storage, - .high_word, - .insert_reference_bits_multiple, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .message_security_assist_extension7, - .message_security_assist_extension8, - .message_security_assist_extension9, - .miscellaneous_extensions, - .miscellaneous_extensions_2, - .miscellaneous_extensions_3, - .nnp_assist, - .population_count, - .processor_activity_instrumentation, - .processor_assist, - .reset_dat_protection, - .reset_reference_bits_multiple, - .test_pending_external_interruption, - .transactional_execution, - .vector, - .vector_enhancements_1, - .vector_enhancements_2, - .vector_packed_decimal, - .vector_packed_decimal_enhancement, - .vector_packed_decimal_enhancement_2, + .beareh, + .deflate, + .dfppc, + .dfpzc, + .edat2, + .esort, + .fpe, + .gs, + .irbm, + .loc2, + .lzr, + .minste2, + .minste3, + .msa7, + .msa8, + .msa9, + .nnpa, + .pai, + .rdp, + .rrbm, + .te, + .tpei, + .vxeh2, + .vxpdeh2, }), }; pub const arch15: CpuModel = .{ .name = "arch15", .llvm_name = "arch15", .features = featureSet(&[_]Feature{ - .bear_enhancement, - .concurrent_functions, - .deflate_conversion, - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .enhanced_sort, - .execution_hint, - .fast_serialization, - .fp_extension, - .guarded_storage, - .high_word, - .insert_reference_bits_multiple, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension12, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .message_security_assist_extension7, - .message_security_assist_extension8, - .message_security_assist_extension9, - .miscellaneous_extensions, - .miscellaneous_extensions_2, - .miscellaneous_extensions_3, - .miscellaneous_extensions_4, - .nnp_assist, - .population_count, - .processor_activity_instrumentation, - .processor_assist, - .reset_dat_protection, - .reset_reference_bits_multiple, - .test_pending_external_interruption, - .transactional_execution, - .vector, - .vector_enhancements_1, - .vector_enhancements_2, - .vector_enhancements_3, - .vector_packed_decimal, - .vector_packed_decimal_enhancement, - .vector_packed_decimal_enhancement_2, - .vector_packed_decimal_enhancement_3, + .beareh, + .ccf, + .deflate, + .dfppc, + .dfpzc, + .edat2, + .esort, + .fpe, + .gs, + .irbm, + .loc2, + .lzr, + .minste2, + .minste3, + .minste4, + .msa12, + .msa7, + .msa8, + .msa9, + .nnpa, + .pai, + .rdp, + .rrbm, + .te, + .tpei, + .vxeh3, + .vxpdeh3, }), }; pub const arch8: CpuModel = .{ @@ -556,23 +506,18 @@ pub const cpu = struct { .name = "arch9", .llvm_name = "arch9", .features = featureSet(&[_]Feature{ - .distinct_ops, - .fast_serialization, - .fp_extension, - .high_word, - .interlocked_access1, - .load_store_on_cond, - .message_security_assist_extension3, - .message_security_assist_extension4, - .population_count, - .reset_reference_bits_multiple, + .distops, + .fbcrs, + .fpe, + .hiword, + .iacc, + .loc, + .msa3, + .msa4, + .popcnt, + .rrbm, }), }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{}), - }; pub const z10: CpuModel = .{ .name = "z10", .llvm_name = "z10", @@ -582,244 +527,177 @@ pub const cpu = struct { .name = "z13", .llvm_name = "z13", .features = featureSet(&[_]Feature{ - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .execution_hint, - .fast_serialization, - .fp_extension, - .high_word, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .miscellaneous_extensions, - .population_count, - .processor_assist, - .reset_reference_bits_multiple, - .transactional_execution, - .vector, + .dfppc, + .dfpzc, + .distops, + .edat2, + .fbcrs, + .fpe, + .hiword, + .iacc, + .loc, + .loc2, + .lzr, + .msa3, + .msa4, + .msa5, + .popcnt, + .rrbm, + .te, + .vx, }), }; pub const z14: CpuModel = .{ .name = "z14", .llvm_name = "z14", .features = featureSet(&[_]Feature{ - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .execution_hint, - .fast_serialization, - .fp_extension, - .guarded_storage, - .high_word, - .insert_reference_bits_multiple, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .message_security_assist_extension7, - .message_security_assist_extension8, - .miscellaneous_extensions, - .miscellaneous_extensions_2, - .population_count, - .processor_assist, - .reset_reference_bits_multiple, - .test_pending_external_interruption, - .transactional_execution, - .vector, - .vector_enhancements_1, - .vector_packed_decimal, + .dfppc, + .dfpzc, + .distops, + .edat2, + .fbcrs, + .fpe, + .gs, + .hiword, + .iacc, + .irbm, + .loc, + .loc2, + .lzr, + .minste2, + .msa4, + .msa7, + .msa8, + .popcnt, + .rrbm, + .te, + .tpei, + .vxeh, + .vxpd, }), }; pub const z15: CpuModel = .{ .name = "z15", .llvm_name = "z15", .features = featureSet(&[_]Feature{ - .deflate_conversion, - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .enhanced_sort, - .execution_hint, - .fast_serialization, - .fp_extension, - .guarded_storage, - .high_word, - .insert_reference_bits_multiple, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .message_security_assist_extension7, - .message_security_assist_extension8, - .message_security_assist_extension9, - .miscellaneous_extensions, - .miscellaneous_extensions_2, - .miscellaneous_extensions_3, - .population_count, - .processor_assist, - .reset_reference_bits_multiple, - .test_pending_external_interruption, - .transactional_execution, - .vector, - .vector_enhancements_1, - .vector_enhancements_2, - .vector_packed_decimal, - .vector_packed_decimal_enhancement, + .deflate, + .dfppc, + .dfpzc, + .edat2, + .esort, + .fpe, + .gs, + .irbm, + .loc2, + .lzr, + .minste2, + .minste3, + .msa7, + .msa8, + .msa9, + .rrbm, + .te, + .tpei, + .vxeh2, + .vxpdeh, }), }; pub const z16: CpuModel = .{ .name = "z16", .llvm_name = "z16", .features = featureSet(&[_]Feature{ - .bear_enhancement, - .deflate_conversion, - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .enhanced_sort, - .execution_hint, - .fast_serialization, - .fp_extension, - .guarded_storage, - .high_word, - .insert_reference_bits_multiple, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .message_security_assist_extension7, - .message_security_assist_extension8, - .message_security_assist_extension9, - .miscellaneous_extensions, - .miscellaneous_extensions_2, - .miscellaneous_extensions_3, - .nnp_assist, - .population_count, - .processor_activity_instrumentation, - .processor_assist, - .reset_dat_protection, - .reset_reference_bits_multiple, - .test_pending_external_interruption, - .transactional_execution, - .vector, - .vector_enhancements_1, - .vector_enhancements_2, - .vector_packed_decimal, - .vector_packed_decimal_enhancement, - .vector_packed_decimal_enhancement_2, + .beareh, + .deflate, + .dfppc, + .dfpzc, + .edat2, + .esort, + .fpe, + .gs, + .irbm, + .loc2, + .lzr, + .minste2, + .minste3, + .msa7, + .msa8, + .msa9, + .nnpa, + .pai, + .rdp, + .rrbm, + .te, + .tpei, + .vxeh2, + .vxpdeh2, }), }; pub const z17: CpuModel = .{ .name = "z17", .llvm_name = "z17", .features = featureSet(&[_]Feature{ - .bear_enhancement, - .concurrent_functions, - .deflate_conversion, - .dfp_packed_conversion, - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .enhanced_sort, - .execution_hint, - .fast_serialization, - .fp_extension, - .guarded_storage, - .high_word, - .insert_reference_bits_multiple, - .interlocked_access1, - .load_and_trap, - .load_and_zero_rightmost_byte, - .load_store_on_cond, - .load_store_on_cond_2, - .message_security_assist_extension12, - .message_security_assist_extension3, - .message_security_assist_extension4, - .message_security_assist_extension5, - .message_security_assist_extension7, - .message_security_assist_extension8, - .message_security_assist_extension9, - .miscellaneous_extensions, - .miscellaneous_extensions_2, - .miscellaneous_extensions_3, - .miscellaneous_extensions_4, - .nnp_assist, - .population_count, - .processor_activity_instrumentation, - .processor_assist, - .reset_dat_protection, - .reset_reference_bits_multiple, - .test_pending_external_interruption, - .transactional_execution, - .vector, - .vector_enhancements_1, - .vector_enhancements_2, - .vector_enhancements_3, - .vector_packed_decimal, - .vector_packed_decimal_enhancement, - .vector_packed_decimal_enhancement_2, - .vector_packed_decimal_enhancement_3, + .beareh, + .ccf, + .deflate, + .dfppc, + .dfpzc, + .edat2, + .esort, + .fpe, + .gs, + .irbm, + .loc2, + .lzr, + .minste2, + .minste3, + .minste4, + .msa12, + .msa7, + .msa8, + .msa9, + .nnpa, + .pai, + .rdp, + .rrbm, + .te, + .tpei, + .vxeh3, + .vxpdeh3, }), }; pub const z196: CpuModel = .{ .name = "z196", .llvm_name = "z196", .features = featureSet(&[_]Feature{ - .distinct_ops, - .fast_serialization, - .fp_extension, - .high_word, - .interlocked_access1, - .load_store_on_cond, - .message_security_assist_extension3, - .message_security_assist_extension4, - .population_count, - .reset_reference_bits_multiple, + .distops, + .fbcrs, + .fpe, + .hiword, + .iacc, + .loc, + .msa3, + .msa4, + .popcnt, + .rrbm, }), }; pub const zEC12: CpuModel = .{ .name = "zEC12", .llvm_name = "zEC12", .features = featureSet(&[_]Feature{ - .dfp_zoned_conversion, - .distinct_ops, - .enhanced_dat_2, - .execution_hint, - .fast_serialization, - .fp_extension, - .high_word, - .interlocked_access1, - .load_and_trap, - .load_store_on_cond, - .message_security_assist_extension3, - .message_security_assist_extension4, - .miscellaneous_extensions, - .population_count, - .processor_assist, - .reset_reference_bits_multiple, - .transactional_execution, + .dfpzc, + .distops, + .edat2, + .fbcrs, + .fpe, + .hiword, + .iacc, + .loc, + .msa3, + .msa4, + .popcnt, + .rrbm, + .te, }), }; }; diff --git a/lib/std/Target/sh.zig b/lib/std/Target/sh.zig new file mode 100644 index 0000000000..a542acb58c --- /dev/null +++ b/lib/std/Target/sh.zig @@ -0,0 +1,236 @@ +//! This file is auto-generated by tools/update_cpu_features.zig. + +const std = @import("../std.zig"); +const CpuFeature = std.Target.Cpu.Feature; +const CpuModel = std.Target.Cpu.Model; + +pub const Feature = enum { + cas, + dsp, + dynshift, + fpu, + fsca, + fsrra, + mmu, + sh2, + sh2a, + sh3, + sh4, + sh4a, +}; + +pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; +pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; +pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; +pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; + +pub const all_features = blk: { + const len = @typeInfo(Feature).@"enum".field_names.len; + std.debug.assert(len <= CpuFeature.Set.needed_bit_count); + var result: [len]CpuFeature = undefined; + result[@backingInt(Feature.cas)] = .{ + .llvm_name = null, + .description = "Enable cas.l instruction", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.dsp)] = .{ + .llvm_name = null, + .description = "Enable DSP extension", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.dynshift)] = .{ + .llvm_name = null, + .description = "Enable dynamic shift instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fpu)] = .{ + .llvm_name = null, + .description = "Enable floating point unit", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fsca)] = .{ + .llvm_name = null, + .description = "Enable fsca instruction", + .dependencies = featureSet(&[_]Feature{ + .fpu, + }), + }; + result[@backingInt(Feature.fsrra)] = .{ + .llvm_name = null, + .description = "Enable fsrra instruction", + .dependencies = featureSet(&[_]Feature{ + .fpu, + }), + }; + result[@backingInt(Feature.mmu)] = .{ + .llvm_name = null, + .description = "Enable memory management unit", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.sh2)] = .{ + .llvm_name = null, + .description = "Enable SH-2 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.sh2a)] = .{ + .llvm_name = null, + .description = "Enable SH-2A instructions", + .dependencies = featureSet(&[_]Feature{ + .dynshift, + .sh2, + }), + }; + result[@backingInt(Feature.sh3)] = .{ + .llvm_name = null, + .description = "Enable SH-3 instructions", + .dependencies = featureSet(&[_]Feature{ + .dynshift, + .sh2, + }), + }; + result[@backingInt(Feature.sh4)] = .{ + .llvm_name = null, + .description = "Enable SH-4 instructions", + .dependencies = featureSet(&[_]Feature{ + .sh3, + }), + }; + result[@backingInt(Feature.sh4a)] = .{ + .llvm_name = null, + .description = "Enable SH-4A instructions", + .dependencies = featureSet(&[_]Feature{ + .sh4, + }), + }; + const ti = @typeInfo(Feature); + for (&result, 0..) |*elem, i| { + elem.index = i; + elem.name = ti.@"enum".field_names[i]; + } + break :blk result; +}; + +pub const cpu = struct { + pub const j2: CpuModel = .{ + .name = "j2", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .cas, + .dynshift, + .sh2, + }), + }; + pub const sh1: CpuModel = .{ + .name = "sh1", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const sh2: CpuModel = .{ + .name = "sh2", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .sh2, + }), + }; + pub const sh2_dsp: CpuModel = .{ + .name = "sh2_dsp", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .dsp, + .sh2, + }), + }; + pub const sh2a: CpuModel = .{ + .name = "sh2a", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .fpu, + .sh2a, + }), + }; + pub const sh2a_nofpu: CpuModel = .{ + .name = "sh2a_nofpu", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .sh2a, + }), + }; + pub const sh2e: CpuModel = .{ + .name = "sh2e", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .fpu, + .sh2, + }), + }; + pub const sh3: CpuModel = .{ + .name = "sh3", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .mmu, + .sh3, + }), + }; + pub const sh3_dsp: CpuModel = .{ + .name = "sh3_dsp", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .dsp, + .mmu, + .sh3, + }), + }; + pub const sh3e: CpuModel = .{ + .name = "sh3e", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .fpu, + .mmu, + .sh3, + }), + }; + pub const sh4: CpuModel = .{ + .name = "sh4", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .fpu, + .mmu, + .sh4, + }), + }; + pub const sh4_nofpu: CpuModel = .{ + .name = "sh4_nofpu", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .mmu, + .sh4, + }), + }; + pub const sh4a: CpuModel = .{ + .name = "sh4a", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .fsca, + .fsrra, + .mmu, + .sh4a, + }), + }; + pub const sh4a_nofpu: CpuModel = .{ + .name = "sh4a_nofpu", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .mmu, + .sh4a, + }), + }; + pub const sh4al_dsp: CpuModel = .{ + .name = "sh4al_dsp", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .dsp, + .mmu, + .sh4a, + }), + }; +}; diff --git a/lib/std/Target/sparc.zig b/lib/std/Target/sparc.zig index 4b303a133d..c62f3321cf 100644 --- a/lib/std/Target/sparc.zig +++ b/lib/std/Target/sparc.zig @@ -5,10 +5,8 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { - @"64bit", crypto, deprecated_v8, - detectroundchange, fix_tn0009, fix_tn0010, fix_tn0011, @@ -19,7 +17,6 @@ pub const Feature = enum { hasleoncasa, hasumacsmac, insertnopload, - leon, leoncyclecounter, leonpwrpsr, no_fmuls, @@ -27,39 +24,10 @@ pub const Feature = enum { no_predictor, osa2011, popc, - reserve_g1, - reserve_g2, - reserve_g3, - reserve_g4, - reserve_g5, - reserve_g6, - reserve_g7, - reserve_i0, - reserve_i1, - reserve_i2, - reserve_i3, - reserve_i4, - reserve_i5, - reserve_l0, - reserve_l1, - reserve_l2, - reserve_l3, - reserve_l4, - reserve_l5, - reserve_l6, - reserve_l7, - reserve_o0, - reserve_o1, - reserve_o2, - reserve_o3, - reserve_o4, - reserve_o5, slow_rdpc, - soft_float, soft_mul_div, ua2005, ua2007, - v8plus, v9, vis, vis2, @@ -75,13 +43,6 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; - result[@backingInt(Feature.@"64bit")] = .{ - .llvm_name = "64bit", - .description = "Enable 64-bit mode", - .dependencies = featureSet(&[_]Feature{ - .v9, - }), - }; result[@backingInt(Feature.crypto)] = .{ .llvm_name = "crypto", .description = "Enable cryptographic extensions", @@ -94,11 +55,6 @@ pub const all_features = blk: { .description = "Enable deprecated V8 instructions in V9 mode", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.detectroundchange)] = .{ - .llvm_name = "detectroundchange", - .description = "LEON3 erratum detection: Detects any rounding mode change request: use only the round-to-nearest rounding mode", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.fix_tn0009)] = .{ .llvm_name = "fix-tn0009", .description = "Enable workaround for errata described in GRLIB-TN-0009", @@ -149,11 +105,6 @@ pub const all_features = blk: { .description = "LEON3 erratum fix: Insert a NOP instruction after every single-cycle load instruction when the next instruction is another load/store instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.leon)] = .{ - .llvm_name = "leon", - .description = "Enable LEON extensions", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.leoncyclecounter)] = .{ .llvm_name = "leoncyclecounter", .description = "Use the Leon cycle counter register", @@ -193,141 +144,6 @@ pub const all_features = blk: { .description = "Use the popc (population count) instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.reserve_g1)] = .{ - .llvm_name = "reserve-g1", - .description = "Reserve G1, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_g2)] = .{ - .llvm_name = "reserve-g2", - .description = "Reserve G2, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_g3)] = .{ - .llvm_name = "reserve-g3", - .description = "Reserve G3, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_g4)] = .{ - .llvm_name = "reserve-g4", - .description = "Reserve G4, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_g5)] = .{ - .llvm_name = "reserve-g5", - .description = "Reserve G5, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_g6)] = .{ - .llvm_name = "reserve-g6", - .description = "Reserve G6, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_g7)] = .{ - .llvm_name = "reserve-g7", - .description = "Reserve G7, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_i0)] = .{ - .llvm_name = "reserve-i0", - .description = "Reserve I0, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_i1)] = .{ - .llvm_name = "reserve-i1", - .description = "Reserve I1, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_i2)] = .{ - .llvm_name = "reserve-i2", - .description = "Reserve I2, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_i3)] = .{ - .llvm_name = "reserve-i3", - .description = "Reserve I3, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_i4)] = .{ - .llvm_name = "reserve-i4", - .description = "Reserve I4, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_i5)] = .{ - .llvm_name = "reserve-i5", - .description = "Reserve I5, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_l0)] = .{ - .llvm_name = "reserve-l0", - .description = "Reserve L0, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_l1)] = .{ - .llvm_name = "reserve-l1", - .description = "Reserve L1, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_l2)] = .{ - .llvm_name = "reserve-l2", - .description = "Reserve L2, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_l3)] = .{ - .llvm_name = "reserve-l3", - .description = "Reserve L3, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_l4)] = .{ - .llvm_name = "reserve-l4", - .description = "Reserve L4, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_l5)] = .{ - .llvm_name = "reserve-l5", - .description = "Reserve L5, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_l6)] = .{ - .llvm_name = "reserve-l6", - .description = "Reserve L6, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_l7)] = .{ - .llvm_name = "reserve-l7", - .description = "Reserve L7, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_o0)] = .{ - .llvm_name = "reserve-o0", - .description = "Reserve O0, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_o1)] = .{ - .llvm_name = "reserve-o1", - .description = "Reserve O1, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_o2)] = .{ - .llvm_name = "reserve-o2", - .description = "Reserve O2, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_o3)] = .{ - .llvm_name = "reserve-o3", - .description = "Reserve O3, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_o4)] = .{ - .llvm_name = "reserve-o4", - .description = "Reserve O4, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_o5)] = .{ - .llvm_name = "reserve-o5", - .description = "Reserve O5, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.slow_rdpc)] = .{ .llvm_name = "slow-rdpc", .description = "rd %pc, %XX is slow", @@ -335,11 +151,6 @@ pub const all_features = blk: { .v9, }), }; - result[@backingInt(Feature.soft_float)] = .{ - .llvm_name = "soft-float", - .description = "Use software emulation for floating point", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.soft_mul_div)] = .{ .llvm_name = "soft-mul-div", .description = "Use software emulation for integer multiply and divide", @@ -361,11 +172,6 @@ pub const all_features = blk: { .vis2, }), }; - result[@backingInt(Feature.v8plus)] = .{ - .llvm_name = "v8plus", - .description = "Enable V8+ mode, allowing use of 64-bit V9 instructions in 32-bit code", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.v9)] = .{ .llvm_name = "v9", .description = "Enable SPARC-V9 instructions", @@ -406,7 +212,6 @@ pub const cpu = struct { .llvm_name = "at697e", .features = featureSet(&[_]Feature{ .insertnopload, - .leon, }), }; pub const at697f: CpuModel = .{ @@ -414,7 +219,6 @@ pub const cpu = struct { .llvm_name = "at697f", .features = featureSet(&[_]Feature{ .insertnopload, - .leon, }), }; pub const f934: CpuModel = .{ @@ -422,17 +226,11 @@ pub const cpu = struct { .llvm_name = "f934", .features = featureSet(&[_]Feature{}), }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{}), - }; pub const gr712rc: CpuModel = .{ .name = "gr712rc", .llvm_name = "gr712rc", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const gr740: CpuModel = .{ @@ -441,7 +239,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .hasleoncasa, .hasumacsmac, - .leon, .leoncyclecounter, .leonpwrpsr, }), @@ -454,9 +251,7 @@ pub const cpu = struct { pub const leon2: CpuModel = .{ .name = "leon2", .llvm_name = "leon2", - .features = featureSet(&[_]Feature{ - .leon, - }), + .features = featureSet(&[_]Feature{}), }; pub const leon3: CpuModel = .{ .name = "leon3", @@ -464,7 +259,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .hasleoncasa, .hasumacsmac, - .leon, }), }; pub const leon4: CpuModel = .{ @@ -473,7 +267,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .hasleoncasa, .hasumacsmac, - .leon, }), }; pub const ma2080: CpuModel = .{ @@ -481,7 +274,6 @@ pub const cpu = struct { .llvm_name = "ma2080", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2085: CpuModel = .{ @@ -489,7 +281,6 @@ pub const cpu = struct { .llvm_name = "ma2085", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2100: CpuModel = .{ @@ -497,7 +288,6 @@ pub const cpu = struct { .llvm_name = "ma2100", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2150: CpuModel = .{ @@ -505,7 +295,6 @@ pub const cpu = struct { .llvm_name = "ma2150", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2155: CpuModel = .{ @@ -513,7 +302,6 @@ pub const cpu = struct { .llvm_name = "ma2155", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2450: CpuModel = .{ @@ -521,7 +309,6 @@ pub const cpu = struct { .llvm_name = "ma2450", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2455: CpuModel = .{ @@ -529,7 +316,6 @@ pub const cpu = struct { .llvm_name = "ma2455", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2480: CpuModel = .{ @@ -537,7 +323,6 @@ pub const cpu = struct { .llvm_name = "ma2480", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2485: CpuModel = .{ @@ -545,7 +330,6 @@ pub const cpu = struct { .llvm_name = "ma2485", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2x5x: CpuModel = .{ @@ -553,7 +337,6 @@ pub const cpu = struct { .llvm_name = "ma2x5x", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const ma2x8x: CpuModel = .{ @@ -561,7 +344,6 @@ pub const cpu = struct { .llvm_name = "ma2x8x", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const myriad2: CpuModel = .{ @@ -569,7 +351,6 @@ pub const cpu = struct { .llvm_name = "myriad2", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const myriad2_1: CpuModel = .{ @@ -577,7 +358,6 @@ pub const cpu = struct { .llvm_name = "myriad2.1", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const myriad2_2: CpuModel = .{ @@ -585,7 +365,6 @@ pub const cpu = struct { .llvm_name = "myriad2.2", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const myriad2_3: CpuModel = .{ @@ -593,7 +372,6 @@ pub const cpu = struct { .llvm_name = "myriad2.3", .features = featureSet(&[_]Feature{ .hasleoncasa, - .leon, }), }; pub const niagara: CpuModel = .{ @@ -688,7 +466,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .fixallfdivsqrt, .insertnopload, - .leon, .no_fmuls, .no_fsmuld, }), diff --git a/lib/std/Target/spirv.zig b/lib/std/Target/spirv.zig index 29f40003e9..2e36c21a32 100644 --- a/lib/std/Target/spirv.zig +++ b/lib/std/Target/spirv.zig @@ -19,11 +19,16 @@ pub const Feature = enum { b_float16dot_product_khr, b_float16type_khr, bit_instructions, + bitcast_extract_ext, clip_distance, compute_derivative_group_linear_khr, compute_derivative_group_quads_khr, constant_data_khr, + cooperative_matrix_conversions_ext, + cooperative_matrix_get_coordinate_ext, cooperative_matrix_khr, + cooperative_matrix_per_element_operations_ext, + cooperative_matrix_reductions_ext, cull_distance, demote_to_helper_invocation, denorm_flush_to_zero, @@ -40,9 +45,12 @@ pub const Feature = enum { expect_assume_khr, float16, float16buffer, + float4ext, float64, + float6ext, float8cooperative_matrix_ext, float8ext, + float8unsigned_e8m0ext, float_controls2, fmakhr, fragment_barycentric_khr, @@ -68,6 +76,7 @@ pub const Feature = enum { group_non_uniform_vote, group_uniform_arithmetic_khr, groups, + image1d, image_basic, image_buffer, image_cube_array, @@ -88,30 +97,31 @@ pub const Feature = enum { interpolation_function, literal_sampler, long_vector_ext, - matrix, mesh_shading_ext, min_lod, multi_view, multi_viewport, + mx_int8ext, named_barrier, opt_none_ext, pipe_storage, pipes, - poison_freeze_khr, quad_control_khr, ray_cull_mask_khr, ray_query_khr, ray_query_position_fetch_khr, - ray_query_provisional_khr, ray_tracing_khr, - ray_tracing_opacity_micromap_ext, + ray_tracing_opacity_micromap_execution_mode_khr, + ray_tracing_opacity_micromap_khr, ray_tracing_position_fetch_khr, - ray_tracing_provisional_khr, ray_traversal_primitive_culling_khr, replicated_composites_ext, + rounding_mode_rte, + rounding_mode_rtz, runtime_descriptor_array, sample_mask_post_depth_coverage, sample_rate_shading, + sampled1d, sampled_buffer, sampled_cube_array, sampled_image_array_dynamic_indexing, @@ -126,7 +136,9 @@ pub const Feature = enum { shader_viewport_index_layer_ext, signed_zero_inf_nan_preserve, sparse_residency, + split_barrier_ext, SPV_EXT_arithmetic_fence, + SPV_EXT_cooperative_matrix_maintenance1, SPV_EXT_demote_to_helper_invocation, SPV_EXT_descriptor_heap, SPV_EXT_descriptor_indexing, @@ -136,9 +148,9 @@ pub const Feature = enum { SPV_EXT_fragment_shader_interlock, SPV_EXT_long_vector, SPV_EXT_mesh_shader, + SPV_EXT_ocp_microscaling_types, SPV_EXT_opacity_micromap, SPV_EXT_optnone, - SPV_EXT_physical_storage_buffer, SPV_EXT_replicated_composites, SPV_EXT_shader_64bit_indexing, SPV_EXT_shader_atomic_float16_add, @@ -150,6 +162,7 @@ pub const Feature = enum { SPV_EXT_shader_subgroup_partitioned, SPV_EXT_shader_tile_image, SPV_EXT_shader_viewport_index_layer, + SPV_EXT_split_barrier, SPV_KHR_16bit_storage, SPV_KHR_8bit_storage, SPV_KHR_abort, @@ -167,7 +180,7 @@ pub const Feature = enum { SPV_KHR_fragment_shading_rate, SPV_KHR_integer_dot_product, SPV_KHR_multiview, - SPV_KHR_poison_freeze, + SPV_KHR_opacity_micromap, SPV_KHR_post_depth_coverage, SPV_KHR_quad_control, SPV_KHR_ray_cull_mask, @@ -218,7 +231,6 @@ pub const Feature = enum { uniform_texel_buffer_array_dynamic_indexing, uniform_texel_buffer_array_non_uniform_indexing, untyped_pointers_khr, - v1_0, v1_1, v1_2, v1_3, @@ -250,7 +262,6 @@ pub const all_features = blk: { .description = "Enable abort_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_abort, - .v1_0, }), }; result[@backingInt(Feature.arithmetic_fence_ext)] = .{ @@ -258,7 +269,6 @@ pub const all_features = blk: { .description = "Enable arithmetic_fence_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_arithmetic_fence, - .v1_0, }), }; result[@backingInt(Feature.atomic_float16add_ext)] = .{ @@ -266,7 +276,6 @@ pub const all_features = blk: { .description = "Enable atomic_float16add_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_atomic_float16_add, - .v1_0, }), }; result[@backingInt(Feature.atomic_float16min_max_ext)] = .{ @@ -274,7 +283,6 @@ pub const all_features = blk: { .description = "Enable atomic_float16min_max_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_atomic_float_min_max, - .v1_0, }), }; result[@backingInt(Feature.atomic_float32add_ext)] = .{ @@ -282,7 +290,6 @@ pub const all_features = blk: { .description = "Enable atomic_float32add_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_atomic_float_add, - .v1_0, }), }; result[@backingInt(Feature.atomic_float32min_max_ext)] = .{ @@ -290,7 +297,6 @@ pub const all_features = blk: { .description = "Enable atomic_float32min_max_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_atomic_float_min_max, - .v1_0, }), }; result[@backingInt(Feature.atomic_float64add_ext)] = .{ @@ -298,7 +304,6 @@ pub const all_features = blk: { .description = "Enable atomic_float64add_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_atomic_float_add, - .v1_0, }), }; result[@backingInt(Feature.atomic_float64min_max_ext)] = .{ @@ -306,38 +311,34 @@ pub const all_features = blk: { .description = "Enable atomic_float64min_max_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_atomic_float_min_max, - .v1_0, }), }; result[@backingInt(Feature.atomic_storage)] = .{ .llvm_name = null, .description = "Enable atomic_storage capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.atomic_storage_ops)] = .{ .llvm_name = null, .description = "Enable atomic_storage_ops capability", .dependencies = featureSet(&[_]Feature{ + .atomic_storage, .SPV_KHR_shader_atomic_counter_ops, - .v1_0, }), }; result[@backingInt(Feature.b_float16cooperative_matrix_khr)] = .{ .llvm_name = null, .description = "Enable b_float16cooperative_matrix_khr capability", .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_bfloat16, - .v1_0, + .b_float16type_khr, + .cooperative_matrix_khr, }), }; result[@backingInt(Feature.b_float16dot_product_khr)] = .{ .llvm_name = null, .description = "Enable b_float16dot_product_khr capability", .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_bfloat16, - .v1_0, + .b_float16type_khr, }), }; result[@backingInt(Feature.b_float16type_khr)] = .{ @@ -345,7 +346,6 @@ pub const all_features = blk: { .description = "Enable b_float16type_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_bfloat16, - .v1_0, }), }; result[@backingInt(Feature.bit_instructions)] = .{ @@ -353,22 +353,25 @@ pub const all_features = blk: { .description = "Enable bit_instructions capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_bit_instructions, - .v1_0, + }), + }; + result[@backingInt(Feature.bitcast_extract_ext)] = .{ + .llvm_name = null, + .description = "Enable bitcast_extract_ext capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_EXT_ocp_microscaling_types, }), }; result[@backingInt(Feature.clip_distance)] = .{ .llvm_name = null, .description = "Enable clip_distance capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.compute_derivative_group_linear_khr)] = .{ .llvm_name = null, .description = "Enable compute_derivative_group_linear_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_compute_shader_derivatives, - .v1_0, }), }; result[@backingInt(Feature.compute_derivative_group_quads_khr)] = .{ @@ -376,7 +379,6 @@ pub const all_features = blk: { .description = "Enable compute_derivative_group_quads_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_compute_shader_derivatives, - .v1_0, }), }; result[@backingInt(Feature.constant_data_khr)] = .{ @@ -384,7 +386,20 @@ pub const all_features = blk: { .description = "Enable constant_data_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_constant_data, - .v1_0, + }), + }; + result[@backingInt(Feature.cooperative_matrix_conversions_ext)] = .{ + .llvm_name = null, + .description = "Enable cooperative_matrix_conversions_ext capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_EXT_cooperative_matrix_maintenance1, + }), + }; + result[@backingInt(Feature.cooperative_matrix_get_coordinate_ext)] = .{ + .llvm_name = null, + .description = "Enable cooperative_matrix_get_coordinate_ext capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_EXT_cooperative_matrix_maintenance1, }), }; result[@backingInt(Feature.cooperative_matrix_khr)] = .{ @@ -392,15 +407,26 @@ pub const all_features = blk: { .description = "Enable cooperative_matrix_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_cooperative_matrix, - .v1_0, + }), + }; + result[@backingInt(Feature.cooperative_matrix_per_element_operations_ext)] = .{ + .llvm_name = null, + .description = "Enable cooperative_matrix_per_element_operations_ext capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_EXT_cooperative_matrix_maintenance1, + }), + }; + result[@backingInt(Feature.cooperative_matrix_reductions_ext)] = .{ + .llvm_name = null, + .description = "Enable cooperative_matrix_reductions_ext capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_EXT_cooperative_matrix_maintenance1, }), }; result[@backingInt(Feature.cull_distance)] = .{ .llvm_name = null, .description = "Enable cull_distance capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.demote_to_helper_invocation)] = .{ .llvm_name = null, @@ -429,24 +455,20 @@ pub const all_features = blk: { result[@backingInt(Feature.derivative_control)] = .{ .llvm_name = null, .description = "Enable derivative_control capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.descriptor_heap_ext)] = .{ .llvm_name = null, .description = "Enable descriptor_heap_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_descriptor_heap, - .v1_0, + .untyped_pointers_khr, }), }; result[@backingInt(Feature.device_enqueue)] = .{ .llvm_name = null, .description = "Enable device_enqueue capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.device_group)] = .{ .llvm_name = null, @@ -468,6 +490,7 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable dot_product_input4x8bit capability", .dependencies = featureSet(&[_]Feature{ + .int8, .SPV_KHR_integer_dot_product, .v1_6, }), @@ -501,36 +524,43 @@ pub const all_features = blk: { .description = "Enable expect_assume_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_expect_assume, - .v1_0, }), }; result[@backingInt(Feature.float16)] = .{ .llvm_name = null, .description = "Enable float16 capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.float16buffer)] = .{ .llvm_name = null, .description = "Enable float16buffer capability", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.float4ext)] = .{ + .llvm_name = null, + .description = "Enable float4ext capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .SPV_EXT_ocp_microscaling_types, }), }; result[@backingInt(Feature.float64)] = .{ .llvm_name = null, .description = "Enable float64 capability", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.float6ext)] = .{ + .llvm_name = null, + .description = "Enable float6ext capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .SPV_EXT_ocp_microscaling_types, }), }; result[@backingInt(Feature.float8cooperative_matrix_ext)] = .{ .llvm_name = null, .description = "Enable float8cooperative_matrix_ext capability", .dependencies = featureSet(&[_]Feature{ - .SPV_EXT_float8, - .v1_0, + .cooperative_matrix_khr, + .float8ext, }), }; result[@backingInt(Feature.float8ext)] = .{ @@ -538,7 +568,13 @@ pub const all_features = blk: { .description = "Enable float8ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_float8, - .v1_0, + }), + }; + result[@backingInt(Feature.float8unsigned_e8m0ext)] = .{ + .llvm_name = null, + .description = "Enable float8unsigned_e8m0ext capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_EXT_ocp_microscaling_types, }), }; result[@backingInt(Feature.float_controls2)] = .{ @@ -546,7 +582,6 @@ pub const all_features = blk: { .description = "Enable float_controls2 capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_float_controls2, - .v1_0, }), }; result[@backingInt(Feature.fmakhr)] = .{ @@ -554,7 +589,6 @@ pub const all_features = blk: { .description = "Enable fmakhr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_fma, - .v1_0, }), }; result[@backingInt(Feature.fragment_barycentric_khr)] = .{ @@ -562,7 +596,6 @@ pub const all_features = blk: { .description = "Enable fragment_barycentric_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_fragment_shader_barycentric, - .v1_0, }), }; result[@backingInt(Feature.fragment_density_ext)] = .{ @@ -570,7 +603,6 @@ pub const all_features = blk: { .description = "Enable fragment_density_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_fragment_invocation_density, - .v1_0, }), }; result[@backingInt(Feature.fragment_fully_covered_ext)] = .{ @@ -578,7 +610,6 @@ pub const all_features = blk: { .description = "Enable fragment_fully_covered_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_fragment_fully_covered, - .v1_0, }), }; result[@backingInt(Feature.fragment_shader_pixel_interlock_ext)] = .{ @@ -586,7 +617,6 @@ pub const all_features = blk: { .description = "Enable fragment_shader_pixel_interlock_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_fragment_shader_interlock, - .v1_0, }), }; result[@backingInt(Feature.fragment_shader_sample_interlock_ext)] = .{ @@ -594,7 +624,6 @@ pub const all_features = blk: { .description = "Enable fragment_shader_sample_interlock_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_fragment_shader_interlock, - .v1_0, }), }; result[@backingInt(Feature.fragment_shader_shading_rate_interlock_ext)] = .{ @@ -602,7 +631,6 @@ pub const all_features = blk: { .description = "Enable fragment_shader_shading_rate_interlock_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_fragment_shader_interlock, - .v1_0, }), }; result[@backingInt(Feature.fragment_shading_rate_khr)] = .{ @@ -610,35 +638,30 @@ pub const all_features = blk: { .description = "Enable fragment_shading_rate_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_fragment_shading_rate, - .v1_0, }), }; result[@backingInt(Feature.generic_pointer)] = .{ .llvm_name = null, .description = "Enable generic_pointer capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.geometry)] = .{ .llvm_name = null, .description = "Enable geometry capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.geometry_point_size)] = .{ .llvm_name = null, .description = "Enable geometry_point_size capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .geometry, }), }; result[@backingInt(Feature.geometry_streams)] = .{ .llvm_name = null, .description = "Enable geometry_streams capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .geometry, }), }; result[@backingInt(Feature.group_non_uniform)] = .{ @@ -652,21 +675,21 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable group_non_uniform_arithmetic capability", .dependencies = featureSet(&[_]Feature{ - .v1_3, + .group_non_uniform, }), }; result[@backingInt(Feature.group_non_uniform_ballot)] = .{ .llvm_name = null, .description = "Enable group_non_uniform_ballot capability", .dependencies = featureSet(&[_]Feature{ - .v1_3, + .group_non_uniform, }), }; result[@backingInt(Feature.group_non_uniform_clustered)] = .{ .llvm_name = null, .description = "Enable group_non_uniform_clustered capability", .dependencies = featureSet(&[_]Feature{ - .v1_3, + .group_non_uniform, }), }; result[@backingInt(Feature.group_non_uniform_partitioned_ext)] = .{ @@ -674,43 +697,42 @@ pub const all_features = blk: { .description = "Enable group_non_uniform_partitioned_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_subgroup_partitioned, - .v1_0, }), }; result[@backingInt(Feature.group_non_uniform_quad)] = .{ .llvm_name = null, .description = "Enable group_non_uniform_quad capability", .dependencies = featureSet(&[_]Feature{ - .v1_3, + .group_non_uniform, }), }; result[@backingInt(Feature.group_non_uniform_rotate_khr)] = .{ .llvm_name = null, .description = "Enable group_non_uniform_rotate_khr capability", .dependencies = featureSet(&[_]Feature{ + .group_non_uniform, .SPV_KHR_subgroup_rotate, - .v1_0, }), }; result[@backingInt(Feature.group_non_uniform_shuffle)] = .{ .llvm_name = null, .description = "Enable group_non_uniform_shuffle capability", .dependencies = featureSet(&[_]Feature{ - .v1_3, + .group_non_uniform, }), }; result[@backingInt(Feature.group_non_uniform_shuffle_relative)] = .{ .llvm_name = null, .description = "Enable group_non_uniform_shuffle_relative capability", .dependencies = featureSet(&[_]Feature{ - .v1_3, + .group_non_uniform, }), }; result[@backingInt(Feature.group_non_uniform_vote)] = .{ .llvm_name = null, .description = "Enable group_non_uniform_vote capability", .dependencies = featureSet(&[_]Feature{ - .v1_3, + .group_non_uniform, }), }; result[@backingInt(Feature.group_uniform_arithmetic_khr)] = .{ @@ -718,90 +740,85 @@ pub const all_features = blk: { .description = "Enable group_uniform_arithmetic_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_uniform_group_instructions, - .v1_0, }), }; result[@backingInt(Feature.groups)] = .{ .llvm_name = null, .description = "Enable groups capability", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.image1d)] = .{ + .llvm_name = null, + .description = "Enable image1d capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .sampled1d, }), }; result[@backingInt(Feature.image_basic)] = .{ .llvm_name = null, .description = "Enable image_basic capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.image_buffer)] = .{ .llvm_name = null, .description = "Enable image_buffer capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .sampled_buffer, }), }; result[@backingInt(Feature.image_cube_array)] = .{ .llvm_name = null, .description = "Enable image_cube_array capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .sampled_cube_array, }), }; result[@backingInt(Feature.image_gather_extended)] = .{ .llvm_name = null, .description = "Enable image_gather_extended capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.image_mipmap)] = .{ .llvm_name = null, .description = "Enable image_mipmap capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .image_basic, }), }; result[@backingInt(Feature.image_ms_array)] = .{ .llvm_name = null, .description = "Enable image_ms_array capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.image_query)] = .{ .llvm_name = null, .description = "Enable image_query capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.image_read_write)] = .{ .llvm_name = null, .description = "Enable image_read_write capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .image_basic, }), }; result[@backingInt(Feature.image_rect)] = .{ .llvm_name = null, .description = "Enable image_rect capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .sampled_rect, }), }; result[@backingInt(Feature.input_attachment)] = .{ .llvm_name = null, .description = "Enable input_attachment capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.input_attachment_array_dynamic_indexing)] = .{ .llvm_name = null, .description = "Enable input_attachment_array_dynamic_indexing capability", .dependencies = featureSet(&[_]Feature{ + .input_attachment, .SPV_EXT_descriptor_indexing, .v1_5, }), @@ -810,73 +827,55 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable input_attachment_array_non_uniform_indexing capability", .dependencies = featureSet(&[_]Feature{ - .SPV_EXT_descriptor_indexing, - .v1_5, + .input_attachment, + .shader_non_uniform, }), }; result[@backingInt(Feature.int16)] = .{ .llvm_name = null, .description = "Enable int16 capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.int64)] = .{ .llvm_name = null, .description = "Enable int64 capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.int64atomics)] = .{ .llvm_name = null, .description = "Enable int64atomics capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .int64, }), }; result[@backingInt(Feature.int64image_ext)] = .{ .llvm_name = null, .description = "Enable int64image_ext capability", .dependencies = featureSet(&[_]Feature{ + .int64, .SPV_EXT_shader_image_int64, - .v1_0, }), }; result[@backingInt(Feature.int8)] = .{ .llvm_name = null, .description = "Enable int8 capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.interpolation_function)] = .{ .llvm_name = null, .description = "Enable interpolation_function capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.literal_sampler)] = .{ .llvm_name = null, .description = "Enable literal_sampler capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.long_vector_ext)] = .{ .llvm_name = null, .description = "Enable long_vector_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_long_vector, - .v1_0, - }), - }; - result[@backingInt(Feature.matrix)] = .{ - .llvm_name = null, - .description = "Enable matrix capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, }), }; result[@backingInt(Feature.mesh_shading_ext)] = .{ @@ -884,15 +883,12 @@ pub const all_features = blk: { .description = "Enable mesh_shading_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_mesh_shader, - .v1_0, }), }; result[@backingInt(Feature.min_lod)] = .{ .llvm_name = null, .description = "Enable min_lod capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.multi_view)] = .{ .llvm_name = null, @@ -906,7 +902,14 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable multi_viewport capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .geometry, + }), + }; + result[@backingInt(Feature.mx_int8ext)] = .{ + .llvm_name = null, + .description = "Enable mx_int8ext capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_EXT_ocp_microscaling_types, }), }; result[@backingInt(Feature.named_barrier)] = .{ @@ -921,37 +924,26 @@ pub const all_features = blk: { .description = "Enable opt_none_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_optnone, - .v1_0, }), }; result[@backingInt(Feature.pipe_storage)] = .{ .llvm_name = null, .description = "Enable pipe_storage capability", .dependencies = featureSet(&[_]Feature{ + .pipes, .v1_1, }), }; result[@backingInt(Feature.pipes)] = .{ .llvm_name = null, .description = "Enable pipes capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), - }; - result[@backingInt(Feature.poison_freeze_khr)] = .{ - .llvm_name = null, - .description = "Enable poison_freeze_khr capability", - .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_poison_freeze, - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.quad_control_khr)] = .{ .llvm_name = null, .description = "Enable quad_control_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_quad_control, - .v1_0, }), }; result[@backingInt(Feature.ray_cull_mask_khr)] = .{ @@ -959,7 +951,6 @@ pub const all_features = blk: { .description = "Enable ray_cull_mask_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_ray_cull_mask, - .v1_0, }), }; result[@backingInt(Feature.ray_query_khr)] = .{ @@ -967,7 +958,6 @@ pub const all_features = blk: { .description = "Enable ray_query_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_ray_query, - .v1_0, }), }; result[@backingInt(Feature.ray_query_position_fetch_khr)] = .{ @@ -975,15 +965,6 @@ pub const all_features = blk: { .description = "Enable ray_query_position_fetch_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_ray_tracing_position_fetch, - .v1_0, - }), - }; - result[@backingInt(Feature.ray_query_provisional_khr)] = .{ - .llvm_name = null, - .description = "Enable ray_query_provisional_khr capability", - .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_ray_query, - .v1_0, }), }; result[@backingInt(Feature.ray_tracing_khr)] = .{ @@ -991,15 +972,21 @@ pub const all_features = blk: { .description = "Enable ray_tracing_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_ray_tracing, - .v1_0, }), }; - result[@backingInt(Feature.ray_tracing_opacity_micromap_ext)] = .{ + result[@backingInt(Feature.ray_tracing_opacity_micromap_execution_mode_khr)] = .{ .llvm_name = null, - .description = "Enable ray_tracing_opacity_micromap_ext capability", + .description = "Enable ray_tracing_opacity_micromap_execution_mode_khr capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_KHR_opacity_micromap, + }), + }; + result[@backingInt(Feature.ray_tracing_opacity_micromap_khr)] = .{ + .llvm_name = null, + .description = "Enable ray_tracing_opacity_micromap_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_opacity_micromap, - .v1_0, + .SPV_KHR_opacity_micromap, }), }; result[@backingInt(Feature.ray_tracing_position_fetch_khr)] = .{ @@ -1007,15 +994,6 @@ pub const all_features = blk: { .description = "Enable ray_tracing_position_fetch_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_ray_tracing_position_fetch, - .v1_0, - }), - }; - result[@backingInt(Feature.ray_tracing_provisional_khr)] = .{ - .llvm_name = null, - .description = "Enable ray_tracing_provisional_khr capability", - .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_ray_tracing, - .v1_0, }), }; result[@backingInt(Feature.ray_traversal_primitive_culling_khr)] = .{ @@ -1024,7 +1002,6 @@ pub const all_features = blk: { .dependencies = featureSet(&[_]Feature{ .SPV_KHR_ray_query, .SPV_KHR_ray_tracing, - .v1_0, }), }; result[@backingInt(Feature.replicated_composites_ext)] = .{ @@ -1032,7 +1009,22 @@ pub const all_features = blk: { .description = "Enable replicated_composites_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_replicated_composites, - .v1_0, + }), + }; + result[@backingInt(Feature.rounding_mode_rte)] = .{ + .llvm_name = null, + .description = "Enable rounding_mode_rte capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_KHR_float_controls, + .v1_4, + }), + }; + result[@backingInt(Feature.rounding_mode_rtz)] = .{ + .llvm_name = null, + .description = "Enable rounding_mode_rtz capability", + .dependencies = featureSet(&[_]Feature{ + .SPV_KHR_float_controls, + .v1_4, }), }; result[@backingInt(Feature.runtime_descriptor_array)] = .{ @@ -1048,58 +1040,50 @@ pub const all_features = blk: { .description = "Enable sample_mask_post_depth_coverage capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_post_depth_coverage, - .v1_0, }), }; result[@backingInt(Feature.sample_rate_shading)] = .{ .llvm_name = null, .description = "Enable sample_rate_shading capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.sampled1d)] = .{ + .llvm_name = null, + .description = "Enable sampled1d capability", + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.sampled_buffer)] = .{ .llvm_name = null, .description = "Enable sampled_buffer capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.sampled_cube_array)] = .{ .llvm_name = null, .description = "Enable sampled_cube_array capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.sampled_image_array_dynamic_indexing)] = .{ .llvm_name = null, .description = "Enable sampled_image_array_dynamic_indexing capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.sampled_image_array_non_uniform_indexing)] = .{ .llvm_name = null, .description = "Enable sampled_image_array_non_uniform_indexing capability", .dependencies = featureSet(&[_]Feature{ - .SPV_EXT_descriptor_indexing, - .v1_5, + .shader_non_uniform, }), }; result[@backingInt(Feature.sampled_rect)] = .{ .llvm_name = null, .description = "Enable sampled_rect capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.shader64bit_indexing_ext)] = .{ .llvm_name = null, .description = "Enable shader64bit_indexing_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_64bit_indexing, - .v1_0, }), }; result[@backingInt(Feature.shader_clock_khr)] = .{ @@ -1107,15 +1091,14 @@ pub const all_features = blk: { .description = "Enable shader_clock_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_shader_clock, - .v1_0, }), }; result[@backingInt(Feature.shader_invocation_reorder_ext)] = .{ .llvm_name = null, .description = "Enable shader_invocation_reorder_ext capability", .dependencies = featureSet(&[_]Feature{ + .ray_tracing_khr, .SPV_EXT_shader_invocation_reorder, - .v1_0, }), }; result[@backingInt(Feature.shader_layer)] = .{ @@ -1144,8 +1127,8 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable shader_viewport_index_layer_ext capability", .dependencies = featureSet(&[_]Feature{ + .multi_viewport, .SPV_EXT_shader_viewport_index_layer, - .v1_0, }), }; result[@backingInt(Feature.signed_zero_inf_nan_preserve)] = .{ @@ -1159,8 +1142,13 @@ pub const all_features = blk: { result[@backingInt(Feature.sparse_residency)] = .{ .llvm_name = null, .description = "Enable sparse_residency capability", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.split_barrier_ext)] = .{ + .llvm_name = null, + .description = "Enable split_barrier_ext capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .SPV_EXT_split_barrier, }), }; result[@backingInt(Feature.SPV_EXT_arithmetic_fence)] = .{ @@ -1168,6 +1156,11 @@ pub const all_features = blk: { .description = "Enable SPV_EXT_arithmetic_fence extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.SPV_EXT_cooperative_matrix_maintenance1)] = .{ + .llvm_name = null, + .description = "Enable SPV_EXT_cooperative_matrix_maintenance1 extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.SPV_EXT_demote_to_helper_invocation)] = .{ .llvm_name = null, .description = "Enable SPV_EXT_demote_to_helper_invocation extension", @@ -1213,6 +1206,11 @@ pub const all_features = blk: { .description = "Enable SPV_EXT_mesh_shader extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.SPV_EXT_ocp_microscaling_types)] = .{ + .llvm_name = null, + .description = "Enable SPV_EXT_ocp_microscaling_types extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.SPV_EXT_opacity_micromap)] = .{ .llvm_name = null, .description = "Enable SPV_EXT_opacity_micromap extension", @@ -1223,11 +1221,6 @@ pub const all_features = blk: { .description = "Enable SPV_EXT_optnone extension", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.SPV_EXT_physical_storage_buffer)] = .{ - .llvm_name = null, - .description = "Enable SPV_EXT_physical_storage_buffer extension", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.SPV_EXT_replicated_composites)] = .{ .llvm_name = null, .description = "Enable SPV_EXT_replicated_composites extension", @@ -1283,6 +1276,11 @@ pub const all_features = blk: { .description = "Enable SPV_EXT_shader_viewport_index_layer extension", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.SPV_EXT_split_barrier)] = .{ + .llvm_name = null, + .description = "Enable SPV_EXT_split_barrier extension", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.SPV_KHR_16bit_storage)] = .{ .llvm_name = null, .description = "Enable SPV_KHR_16bit_storage extension", @@ -1368,9 +1366,9 @@ pub const all_features = blk: { .description = "Enable SPV_KHR_multiview extension", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.SPV_KHR_poison_freeze)] = .{ + result[@backingInt(Feature.SPV_KHR_opacity_micromap)] = .{ .llvm_name = null, - .description = "Enable SPV_KHR_poison_freeze extension", + .description = "Enable SPV_KHR_opacity_micromap extension", .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.SPV_KHR_post_depth_coverage)] = .{ @@ -1463,7 +1461,6 @@ pub const all_features = blk: { .description = "Enable stencil_export_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_stencil_export, - .v1_0, }), }; result[@backingInt(Feature.storage_buffer16bit_access)] = .{ @@ -1485,60 +1482,46 @@ pub const all_features = blk: { result[@backingInt(Feature.storage_buffer_array_dynamic_indexing)] = .{ .llvm_name = null, .description = "Enable storage_buffer_array_dynamic_indexing capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.storage_buffer_array_non_uniform_indexing)] = .{ .llvm_name = null, .description = "Enable storage_buffer_array_non_uniform_indexing capability", .dependencies = featureSet(&[_]Feature{ - .SPV_EXT_descriptor_indexing, - .v1_5, + .shader_non_uniform, }), }; result[@backingInt(Feature.storage_image_array_dynamic_indexing)] = .{ .llvm_name = null, .description = "Enable storage_image_array_dynamic_indexing capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.storage_image_array_non_uniform_indexing)] = .{ .llvm_name = null, .description = "Enable storage_image_array_non_uniform_indexing capability", .dependencies = featureSet(&[_]Feature{ - .SPV_EXT_descriptor_indexing, - .v1_5, + .shader_non_uniform, }), }; result[@backingInt(Feature.storage_image_extended_formats)] = .{ .llvm_name = null, .description = "Enable storage_image_extended_formats capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.storage_image_multisample)] = .{ .llvm_name = null, .description = "Enable storage_image_multisample capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.storage_image_read_without_format)] = .{ .llvm_name = null, .description = "Enable storage_image_read_without_format capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.storage_image_write_without_format)] = .{ .llvm_name = null, .description = "Enable storage_image_write_without_format capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.storage_input_output16)] = .{ .llvm_name = null, @@ -1568,6 +1551,7 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable storage_texel_buffer_array_dynamic_indexing capability", .dependencies = featureSet(&[_]Feature{ + .image_buffer, .SPV_EXT_descriptor_indexing, .v1_5, }), @@ -1576,8 +1560,8 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable storage_texel_buffer_array_non_uniform_indexing capability", .dependencies = featureSet(&[_]Feature{ - .SPV_EXT_descriptor_indexing, - .v1_5, + .image_buffer, + .shader_non_uniform, }), }; result[@backingInt(Feature.subgroup_ballot_khr)] = .{ @@ -1585,13 +1569,13 @@ pub const all_features = blk: { .description = "Enable subgroup_ballot_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_shader_ballot, - .v1_0, }), }; result[@backingInt(Feature.subgroup_dispatch)] = .{ .llvm_name = null, .description = "Enable subgroup_dispatch capability", .dependencies = featureSet(&[_]Feature{ + .device_enqueue, .v1_1, }), }; @@ -1600,21 +1584,18 @@ pub const all_features = blk: { .description = "Enable subgroup_vote_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_subgroup_vote, - .v1_0, }), }; result[@backingInt(Feature.tessellation)] = .{ .llvm_name = null, .description = "Enable tessellation capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.tessellation_point_size)] = .{ .llvm_name = null, .description = "Enable tessellation_point_size capability", .dependencies = featureSet(&[_]Feature{ - .v1_0, + .tessellation, }), }; result[@backingInt(Feature.tile_image_color_read_access_ext)] = .{ @@ -1622,7 +1603,6 @@ pub const all_features = blk: { .description = "Enable tile_image_color_read_access_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_tile_image, - .v1_0, }), }; result[@backingInt(Feature.tile_image_depth_read_access_ext)] = .{ @@ -1630,7 +1610,6 @@ pub const all_features = blk: { .description = "Enable tile_image_depth_read_access_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_tile_image, - .v1_0, }), }; result[@backingInt(Feature.tile_image_stencil_read_access_ext)] = .{ @@ -1638,45 +1617,37 @@ pub const all_features = blk: { .description = "Enable tile_image_stencil_read_access_ext capability", .dependencies = featureSet(&[_]Feature{ .SPV_EXT_shader_tile_image, - .v1_0, }), }; result[@backingInt(Feature.transform_feedback)] = .{ .llvm_name = null, .description = "Enable transform_feedback capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.uniform_and_storage_buffer16bit_access)] = .{ .llvm_name = null, .description = "Enable uniform_and_storage_buffer16bit_access capability", .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_16bit_storage, - .v1_3, + .storage_buffer16bit_access, }), }; result[@backingInt(Feature.uniform_and_storage_buffer8bit_access)] = .{ .llvm_name = null, .description = "Enable uniform_and_storage_buffer8bit_access capability", .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_8bit_storage, - .v1_5, + .storage_buffer8bit_access, }), }; result[@backingInt(Feature.uniform_buffer_array_dynamic_indexing)] = .{ .llvm_name = null, .description = "Enable uniform_buffer_array_dynamic_indexing capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.uniform_buffer_array_non_uniform_indexing)] = .{ .llvm_name = null, .description = "Enable uniform_buffer_array_non_uniform_indexing capability", .dependencies = featureSet(&[_]Feature{ - .SPV_EXT_descriptor_indexing, - .v1_5, + .shader_non_uniform, }), }; result[@backingInt(Feature.uniform_decoration)] = .{ @@ -1690,6 +1661,7 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable uniform_texel_buffer_array_dynamic_indexing capability", .dependencies = featureSet(&[_]Feature{ + .sampled_buffer, .SPV_EXT_descriptor_indexing, .v1_5, }), @@ -1698,8 +1670,8 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable uniform_texel_buffer_array_non_uniform_indexing capability", .dependencies = featureSet(&[_]Feature{ - .SPV_EXT_descriptor_indexing, - .v1_5, + .sampled_buffer, + .shader_non_uniform, }), }; result[@backingInt(Feature.untyped_pointers_khr)] = .{ @@ -1707,20 +1679,12 @@ pub const all_features = blk: { .description = "Enable untyped_pointers_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_untyped_pointers, - .v1_0, }), }; - result[@backingInt(Feature.v1_0)] = .{ - .llvm_name = null, - .description = "Enable v1_0 extension", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.v1_1)] = .{ .llvm_name = null, .description = "Enable v1_1 extension", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.v1_2)] = .{ .llvm_name = null, @@ -1761,8 +1725,7 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable variable_pointers capability", .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_variable_pointers, - .v1_3, + .variable_pointers_storage_buffer, }), }; result[@backingInt(Feature.variable_pointers_storage_buffer)] = .{ @@ -1776,9 +1739,7 @@ pub const all_features = blk: { result[@backingInt(Feature.vector16)] = .{ .llvm_name = null, .description = "Enable vector16 capability", - .dependencies = featureSet(&[_]Feature{ - .v1_0, - }), + .dependencies = featureSet(&[_]Feature{}), }; result[@backingInt(Feature.vulkan_memory_model)] = .{ .llvm_name = null, @@ -1800,16 +1761,14 @@ pub const all_features = blk: { .llvm_name = null, .description = "Enable workgroup_memory_explicit_layout16bit_access_khr capability", .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_workgroup_memory_explicit_layout, - .v1_0, + .workgroup_memory_explicit_layout_khr, }), }; result[@backingInt(Feature.workgroup_memory_explicit_layout8bit_access_khr)] = .{ .llvm_name = null, .description = "Enable workgroup_memory_explicit_layout8bit_access_khr capability", .dependencies = featureSet(&[_]Feature{ - .SPV_KHR_workgroup_memory_explicit_layout, - .v1_0, + .workgroup_memory_explicit_layout_khr, }), }; result[@backingInt(Feature.workgroup_memory_explicit_layout_khr)] = .{ @@ -1817,7 +1776,6 @@ pub const all_features = blk: { .description = "Enable workgroup_memory_explicit_layout_khr capability", .dependencies = featureSet(&[_]Feature{ .SPV_KHR_workgroup_memory_explicit_layout, - .v1_0, }), }; const ti = @typeInfo(Feature); @@ -1829,18 +1787,91 @@ pub const all_features = blk: { }; pub const cpu = struct { - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", + pub const opencl_v2_1: CpuModel = .{ + .name = "opencl_v2_1", + .llvm_name = null, .features = featureSet(&[_]Feature{}), }; - pub const opencl_v2: CpuModel = .{ - .name = "opencl_v2", + pub const opencl_v2_2: CpuModel = .{ + .name = "opencl_v2_2", .llvm_name = null, .features = featureSet(&[_]Feature{ .v1_2, }), }; + pub const opencl_v3_1: CpuModel = .{ + .name = "opencl_v3_1", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_4, + }), + }; + pub const opengl_v4_6: CpuModel = .{ + .name = "opengl_v4_6", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_4, + }), + }; + pub const v1_0: CpuModel = .{ + .name = "v1_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const v1_1: CpuModel = .{ + .name = "v1_1", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_1, + }), + }; + pub const v1_2: CpuModel = .{ + .name = "v1_2", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_2, + }), + }; + pub const v1_3: CpuModel = .{ + .name = "v1_3", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_3, + }), + }; + pub const v1_4: CpuModel = .{ + .name = "v1_4", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_4, + }), + }; + pub const v1_5: CpuModel = .{ + .name = "v1_5", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_5, + }), + }; + pub const v1_6: CpuModel = .{ + .name = "v1_6", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_6, + }), + }; + pub const vulkan_v1_0: CpuModel = .{ + .name = "vulkan_v1_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const vulkan_v1_1: CpuModel = .{ + .name = "vulkan_v1_1", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_3, + }), + }; pub const vulkan_v1_2: CpuModel = .{ .name = "vulkan_v1_2", .llvm_name = null, @@ -1848,4 +1879,18 @@ pub const cpu = struct { .v1_5, }), }; + pub const vulkan_v1_3: CpuModel = .{ + .name = "vulkan_v1_3", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_6, + }), + }; + pub const vulkan_v1_4: CpuModel = .{ + .name = "vulkan_v1_4", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v1_6, + }), + }; }; diff --git a/lib/std/Target/wasm.zig b/lib/std/Target/wasm.zig index 609a1ef93e..2df60fea20 100644 --- a/lib/std/Target/wasm.zig +++ b/lib/std/Target/wasm.zig @@ -74,7 +74,9 @@ pub const all_features = blk: { result[@backingInt(Feature.fp16)] = .{ .llvm_name = "fp16", .description = "Enable FP16 instructions", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .simd128, + }), }; result[@backingInt(Feature.gc)] = .{ .llvm_name = "gc", @@ -121,7 +123,9 @@ pub const all_features = blk: { result[@backingInt(Feature.relaxed_atomics)] = .{ .llvm_name = "relaxed-atomics", .description = "Enable relaxed-atomics proposal", - .dependencies = featureSet(&[_]Feature{}), + .dependencies = featureSet(&[_]Feature{ + .atomics, + }), }; result[@backingInt(Feature.relaxed_simd)] = .{ .llvm_name = "relaxed-simd", @@ -200,10 +204,8 @@ pub const cpu = struct { .name = "wasm_v3_0", .llvm_name = null, .features = featureSet(&[_]Feature{ - .atomics, .exception_handling, .extended_const, - .fp16, .gc, .multimemory, .mutable_globals, diff --git a/lib/std/Target/x86.zig b/lib/std/Target/x86.zig index 418ae155b7..397ec782c4 100644 --- a/lib/std/Target/x86.zig +++ b/lib/std/Target/x86.zig @@ -102,19 +102,14 @@ pub const Feature = enum { fsrm, fxsr, gfni, - harden_sls_ijmp, - harden_sls_ret, hreset, idivl_to_divb, idivq_to_divl, - inline_asm_use_gpr32, invpcid, jmpabs, kl, lea_sp, lea_uses_ag, - lvi_cfi, - lvi_load_hardening, lwp, lzcnt, macrofusion, @@ -155,40 +150,10 @@ pub const Feature = enum { rdpru, rdrnd, rdseed, - reserve_edi, - reserve_r10, - reserve_r11, - reserve_r12, - reserve_r13, - reserve_r14, - reserve_r15, - reserve_r16, - reserve_r17, - reserve_r18, - reserve_r19, - reserve_r20, - reserve_r21, - reserve_r22, - reserve_r23, - reserve_r24, - reserve_r25, - reserve_r26, - reserve_r27, - reserve_r28, - reserve_r29, - reserve_r30, - reserve_r31, - reserve_r8, - reserve_r9, - retpoline, - retpoline_external_thunk, - retpoline_indirect_branches, - retpoline_indirect_calls, rtm, sahf, sbb_dep_breaking, serialize, - seses, sgx, sha, sha512, @@ -208,20 +173,18 @@ pub const Feature = enum { sm4, smap, smep, - soft_float, sse, sse2, sse3, sse4_1, sse4_2, sse4a, - sse_unaligned_mem, ssse3, - tagged_globals, tbm, tsxldtrk, tuning_fast_imm_vector_shift, uintr, + unaligned_sse_access, use_glm_div_sqrt_costs, use_slm_arith_costs, usermsr, @@ -231,7 +194,6 @@ pub const Feature = enum { waitpkg, wbnoinvd, widekl, - x32, x87, xop, xsave, @@ -830,16 +792,6 @@ pub const all_features = blk: { .sse2, }), }; - result[@backingInt(Feature.harden_sls_ijmp)] = .{ - .llvm_name = "harden-sls-ijmp", - .description = "Harden against straight line speculation across indirect JMP instructions.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.harden_sls_ret)] = .{ - .llvm_name = "harden-sls-ret", - .description = "Harden against straight line speculation across RET instructions.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.hreset)] = .{ .llvm_name = "hreset", .description = "Has hreset instruction", @@ -855,11 +807,6 @@ pub const all_features = blk: { .description = "Use 32-bit divide for positive values less than 2^32", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.inline_asm_use_gpr32)] = .{ - .llvm_name = "inline-asm-use-gpr32", - .description = "Enable use of GPR32 in inline assembly for APX", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.invpcid)] = .{ .llvm_name = "invpcid", .description = "Invalidate Process-Context Identifier", @@ -887,16 +834,6 @@ pub const all_features = blk: { .description = "LEA instruction needs inputs at AG stage", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.lvi_cfi)] = .{ - .llvm_name = "lvi-cfi", - .description = "Prevent indirect calls/branches from using a memory operand, and precede all indirect calls/branches from a register with an LFENCE instruction to serialize control flow. Also decompose RET instructions into a POP+LFENCE+JMP sequence.", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.lvi_load_hardening)] = .{ - .llvm_name = "lvi-load-hardening", - .description = "Insert LFENCE instructions to prevent data speculatively injected into loads from being used maliciously.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.lwp)] = .{ .llvm_name = "lwp", .description = "Enable LWP instructions", @@ -1099,156 +1036,6 @@ pub const all_features = blk: { .description = "Support RDSEED instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.reserve_edi)] = .{ - .llvm_name = "reserve-edi", - .description = "Reserve EDI, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r10)] = .{ - .llvm_name = "reserve-r10", - .description = "Reserve R10, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r11)] = .{ - .llvm_name = "reserve-r11", - .description = "Reserve R11, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r12)] = .{ - .llvm_name = "reserve-r12", - .description = "Reserve R12, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r13)] = .{ - .llvm_name = "reserve-r13", - .description = "Reserve R13, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r14)] = .{ - .llvm_name = "reserve-r14", - .description = "Reserve R14, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r15)] = .{ - .llvm_name = "reserve-r15", - .description = "Reserve R15, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r16)] = .{ - .llvm_name = "reserve-r16", - .description = "Reserve R16, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r17)] = .{ - .llvm_name = "reserve-r17", - .description = "Reserve R17, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r18)] = .{ - .llvm_name = "reserve-r18", - .description = "Reserve R18, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r19)] = .{ - .llvm_name = "reserve-r19", - .description = "Reserve R19, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r20)] = .{ - .llvm_name = "reserve-r20", - .description = "Reserve R20, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r21)] = .{ - .llvm_name = "reserve-r21", - .description = "Reserve R21, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r22)] = .{ - .llvm_name = "reserve-r22", - .description = "Reserve R22, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r23)] = .{ - .llvm_name = "reserve-r23", - .description = "Reserve R23, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r24)] = .{ - .llvm_name = "reserve-r24", - .description = "Reserve R24, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r25)] = .{ - .llvm_name = "reserve-r25", - .description = "Reserve R25, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r26)] = .{ - .llvm_name = "reserve-r26", - .description = "Reserve R26, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r27)] = .{ - .llvm_name = "reserve-r27", - .description = "Reserve R27, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r28)] = .{ - .llvm_name = "reserve-r28", - .description = "Reserve R28, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r29)] = .{ - .llvm_name = "reserve-r29", - .description = "Reserve R29, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r30)] = .{ - .llvm_name = "reserve-r30", - .description = "Reserve R30, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r31)] = .{ - .llvm_name = "reserve-r31", - .description = "Reserve R31, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r8)] = .{ - .llvm_name = "reserve-r8", - .description = "Reserve R8, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.reserve_r9)] = .{ - .llvm_name = "reserve-r9", - .description = "Reserve R9, making it unavailable as a GPR", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.retpoline)] = .{ - .llvm_name = "retpoline", - .description = "Remove speculation of indirect branches from the generated code, either by avoiding them entirely or lowering them with a speculation blocking construct", - .dependencies = featureSet(&[_]Feature{ - .retpoline_indirect_branches, - .retpoline_indirect_calls, - }), - }; - result[@backingInt(Feature.retpoline_external_thunk)] = .{ - .llvm_name = "retpoline-external-thunk", - .description = "When lowering an indirect call or branch using a `retpoline`, rely on the specified user provided thunk rather than emitting one ourselves. Only has effect when combined with some other retpoline feature", - .dependencies = featureSet(&[_]Feature{ - .retpoline_indirect_calls, - }), - }; - result[@backingInt(Feature.retpoline_indirect_branches)] = .{ - .llvm_name = "retpoline-indirect-branches", - .description = "Remove speculation of indirect branches from the generated code", - .dependencies = featureSet(&[_]Feature{}), - }; - result[@backingInt(Feature.retpoline_indirect_calls)] = .{ - .llvm_name = "retpoline-indirect-calls", - .description = "Remove speculation of indirect calls from the generated code", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.rtm)] = .{ .llvm_name = "rtm", .description = "Support RTM instructions", @@ -1269,13 +1056,6 @@ pub const all_features = blk: { .description = "Has serialize instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.seses)] = .{ - .llvm_name = "seses", - .description = "Prevent speculative execution side channel timing attacks by inserting a speculation barrier before memory reads, memory writes, and conditional branches. Implies LVI Control Flow integrity.", - .dependencies = featureSet(&[_]Feature{ - .lvi_cfi, - }), - }; result[@backingInt(Feature.sgx)] = .{ .llvm_name = "sgx", .description = "Enable Software Guard Extensions", @@ -1379,11 +1159,6 @@ pub const all_features = blk: { .description = "Enable Supervisor Mode Execution Prevention", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.soft_float)] = .{ - .llvm_name = "soft-float", - .description = "Use software floating point features", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.sse)] = .{ .llvm_name = "sse", .description = "Enable SSE instructions", @@ -1425,11 +1200,6 @@ pub const all_features = blk: { .sse3, }), }; - result[@backingInt(Feature.sse_unaligned_mem)] = .{ - .llvm_name = "sse-unaligned-mem", - .description = "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.ssse3)] = .{ .llvm_name = "ssse3", .description = "Enable SSSE3 instructions", @@ -1437,11 +1207,6 @@ pub const all_features = blk: { .sse3, }), }; - result[@backingInt(Feature.tagged_globals)] = .{ - .llvm_name = "tagged-globals", - .description = "Use an instruction sequence for taking the address of a global that allows a memory tag in the upper address bits.", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.tbm)] = .{ .llvm_name = "tbm", .description = "Enable TBM instructions", @@ -1462,6 +1227,11 @@ pub const all_features = blk: { .description = "Has UINTR Instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.unaligned_sse_access)] = .{ + .llvm_name = "sse-unaligned-mem", + .description = "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.use_glm_div_sqrt_costs)] = .{ .llvm_name = "use-glm-div-sqrt-costs", .description = "Use Goldmont specific floating point div/sqrt costs", @@ -1515,11 +1285,6 @@ pub const all_features = blk: { .kl, }), }; - result[@backingInt(Feature.x32)] = .{ - .llvm_name = "x32", - .description = "64-bit with ILP32 programming model (e.g. x32 ABI)", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.x87)] = .{ .llvm_name = "x87", .description = "Enable X87 float instructions", @@ -3068,21 +2833,6 @@ pub const cpu = struct { .xsaves, }), }; - pub const generic: CpuModel = .{ - .name = "generic", - .llvm_name = "generic", - .features = featureSet(&[_]Feature{ - .@"64bit", - .cx8, - .fast_15bytenop, - .fast_scalar_fsqrt, - .idivq_to_divl, - .macrofusion, - .slow_3ops_lea, - .vzeroupper, - .x87, - }), - }; pub const geode: CpuModel = .{ .name = "geode", .llvm_name = "geode", @@ -3890,7 +3640,6 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .cx8, .slow_unaligned_mem_16, - .soft_float, .vzeroupper, }), }; diff --git a/lib/std/Target/xcore.zig b/lib/std/Target/xcore.zig index b2580b5a7d..c4521caee7 100644 --- a/lib/std/Target/xcore.zig +++ b/lib/std/Target/xcore.zig @@ -57,7 +57,7 @@ pub const all_features = blk: { pub const cpu = struct { pub const xs1b: CpuModel = .{ .name = "xs1b", - .llvm_name = null, + .llvm_name = "xs1b-generic", .features = featureSet(&[_]Feature{}), }; pub const xs2a: CpuModel = .{ diff --git a/lib/std/Target/xtensa.zig b/lib/std/Target/xtensa.zig index 2a95e224cb..af0e160f19 100644 --- a/lib/std/Target/xtensa.zig +++ b/lib/std/Target/xtensa.zig @@ -16,7 +16,6 @@ pub const Feature = enum { esp32s2ops, exception, extendedl32r, - forced_atomics, fp, highpriinterrupts, highpriinterrupts_level3, @@ -109,11 +108,6 @@ pub const all_features = blk: { .description = "Enable Xtensa Extended L32R option", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.forced_atomics)] = .{ - .llvm_name = "forced-atomics", - .description = "Assume that lock-free native-width atomics are available", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.fp)] = .{ .llvm_name = "fp", .description = "Enable Xtensa Single FP instructions", @@ -345,8 +339,8 @@ pub const cpu = struct { .timers1, }), }; - pub const generic: CpuModel = .{ - .name = "generic", + pub const xtensa: CpuModel = .{ + .name = "xtensa", .llvm_name = "generic", .features = featureSet(&[_]Feature{}), }; diff --git a/lib/std/Target/z80.zig b/lib/std/Target/z80.zig new file mode 100644 index 0000000000..049065a51c --- /dev/null +++ b/lib/std/Target/z80.zig @@ -0,0 +1,221 @@ +//! This file is auto-generated by tools/update_cpu_features.zig. + +const std = @import("../std.zig"); +const CpuFeature = std.Target.Cpu.Feature; +const CpuModel = std.Target.Cpu.Model; + +pub const Feature = enum { + epu, + ez80, + infc, + no_inirx, + no_ld_i_hl, + r800, + reliable_ld_a_i, + sli, + xdcb, + xyhl, + z180, + z280, + z380, + z80n, +}; + +pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; +pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; +pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; +pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; + +pub const all_features = blk: { + const len = @typeInfo(Feature).@"enum".field_names.len; + std.debug.assert(len <= CpuFeature.Set.needed_bit_count); + var result: [len]CpuFeature = undefined; + result[@backingInt(Feature.epu)] = .{ + .llvm_name = null, + .description = "Enable Extended Processing Unit instructions", + .dependencies = featureSet(&[_]Feature{ + .z280, + }), + }; + result[@backingInt(Feature.ez80)] = .{ + .llvm_name = null, + .description = "Enable eZ80 instructions including ADL mode", + .dependencies = featureSet(&[_]Feature{ + .xyhl, + .z180, + }), + }; + result[@backingInt(Feature.infc)] = .{ + .llvm_name = null, + .description = "Enable flags-only port input instruction", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.no_inirx)] = .{ + .llvm_name = null, + .description = "Disable block I/O instructions that address the port with DE and count with BC", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.no_ld_i_hl)] = .{ + .llvm_name = null, + .description = "Disable 16-bit I register transfers", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.r800)] = .{ + .llvm_name = null, + .description = "Enable R800 instructions", + .dependencies = featureSet(&[_]Feature{ + .infc, + .xyhl, + }), + }; + result[@backingInt(Feature.reliable_ld_a_i)] = .{ + .llvm_name = null, + .description = "LD A,I and LD A,R reliably report the interrupt enable state", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.sli)] = .{ + .llvm_name = null, + .description = "Enable shift left inserting 1 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.xdcb)] = .{ + .llvm_name = null, + .description = "Enable indexed rotate, shift, RES, and SET instructions that also store to a register", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.xyhl)] = .{ + .llvm_name = null, + .description = "Enable index register halves (IXH, IXL, IYH, IYL)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.z180)] = .{ + .llvm_name = null, + .description = "Enable Z180 instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.z280)] = .{ + .llvm_name = null, + .description = "Enable Z280 instructions", + .dependencies = featureSet(&[_]Feature{ + .infc, + .xyhl, + }), + }; + result[@backingInt(Feature.z380)] = .{ + .llvm_name = null, + .description = "Enable Z380 instructions including long mode", + .dependencies = featureSet(&[_]Feature{ + .xyhl, + .z180, + }), + }; + result[@backingInt(Feature.z80n)] = .{ + .llvm_name = null, + .description = "Enable Z80N instructions", + .dependencies = featureSet(&[_]Feature{}), + }; + const ti = @typeInfo(Feature); + for (&result, 0..) |*elem, i| { + elem.index = i; + elem.name = ti.@"enum".field_names[i]; + } + break :blk result; +}; + +pub const cpu = struct { + pub const ez80: CpuModel = .{ + .name = "ez80", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .ez80, + .reliable_ld_a_i, + }), + }; + pub const ez80190: CpuModel = .{ + .name = "ez80190", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .ez80, + .no_inirx, + .no_ld_i_hl, + .reliable_ld_a_i, + }), + }; + pub const ez80f92: CpuModel = .{ + .name = "ez80f92", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .ez80, + .no_ld_i_hl, + .reliable_ld_a_i, + }), + }; + pub const r800: CpuModel = .{ + .name = "r800", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .r800, + }), + }; + pub const z180: CpuModel = .{ + .name = "z180", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .z180, + }), + }; + pub const z280: CpuModel = .{ + .name = "z280", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .reliable_ld_a_i, + .z280, + }), + }; + pub const z380: CpuModel = .{ + .name = "z380", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .reliable_ld_a_i, + .z380, + }), + }; + pub const z80: CpuModel = .{ + .name = "z80", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const z80n: CpuModel = .{ + .name = "z80n", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .infc, + .reliable_ld_a_i, + .sli, + .xdcb, + .xyhl, + .z80n, + }), + }; + pub const z8400: CpuModel = .{ + .name = "z8400", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .infc, + .sli, + .xdcb, + .xyhl, + }), + }; + pub const z84c00: CpuModel = .{ + .name = "z84c00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .infc, + .reliable_ld_a_i, + .sli, + .xdcb, + .xyhl, + }), + }; +}; diff --git a/lib/std/atomic.zig b/lib/std/atomic.zig index f3f39b90a9..2a3e0ee802 100644 --- a/lib/std/atomic.zig +++ b/lib/std/atomic.zig @@ -415,7 +415,7 @@ pub inline fn spinLoopHint() void { .sparc, .sparc64, - => if (comptime builtin.cpu.hasAny(.sparc, &.{ .v8plus, .v9 })) { + => if (comptime builtin.cpu.has(.sparc, .v9)) { asm volatile ("rd %%ccr, %%g0"); }, diff --git a/lib/std/hash/crc.zig b/lib/std/hash/crc.zig index 795f6a5f5e..cd6d494a65 100644 --- a/lib/std/hash/crc.zig +++ b/lib/std/hash/crc.zig @@ -786,7 +786,7 @@ pub const @"CRC-32/CKSUM" = Generic(u32, .{ .xor_output = 0xffffffff, }); -pub const @"CRC-32/ISCSI" = if (builtin.cpu.hasAll(.x86, &.{ .@"64bit", .crc32 })) +pub const @"CRC-32/ISCSI" = if (builtin.target.cpu.arch == .x86_64 and builtin.target.cpu.has(.x86, .crc32)) @import("crc/Crc32c.zig") else Generic(u32, .{ diff --git a/lib/std/lang.zig b/lib/std/lang.zig index b9379a1349..5ac0759d17 100644 --- a/lib/std/lang.zig +++ b/lib/std/lang.zig @@ -393,6 +393,10 @@ pub const CallingConvention = union(enum(u8)) { spirv_task: SpirvKernelOptions, spirv_mesh: SpirvMeshOptions, + // Calling conventions for the `z80` architecture. + z80_cet, + z80_tiflags, + // Calling conventions for the `ez80` architecture. ez80_cet, ez80_tiflags, diff --git a/lib/std/lang/assembly.zig b/lib/std/lang/assembly.zig index 81fdf78ca8..649709025a 100644 --- a/lib/std/lang/assembly.zig +++ b/lib/std/lang/assembly.zig @@ -2094,52 +2094,6 @@ pub const Clobbers = switch (@import("builtin").cpu.arch) { v62: bool = false, v63: bool = false, }, - .kalimba => packed struct { - /// Whether the inline assembly code may perform stores to memory - /// addresses other than those derived from input pointer provenance. - memory: bool = false, - - i0: bool = false, - i1: bool = false, - i2: bool = false, - i3: bool = false, - i4: bool = false, - i5: bool = false, - i6: bool = false, - i7: bool = false, - - m0: bool = false, - m1: bool = false, - m2: bool = false, - m3: bool = false, - l0: bool = false, - l1: bool = false, - l2: bool = false, - l3: bool = false, - l4: bool = false, - l5: bool = false, - doloopstart: bool = false, - doloopend: bool = false, - divresult: bool = false, - divremainder: bool = false, - rmac: bool = false, - rmac0: bool = false, - rmac1: bool = false, - rmac2: bool = false, - rlink: bool = false, - rflags: bool = false, - r0: bool = false, - r1: bool = false, - r2: bool = false, - r3: bool = false, - r4: bool = false, - r5: bool = false, - r6: bool = false, - r7: bool = false, - r8: bool = false, - r9: bool = false, - r10: bool = false, - }, .or1k => packed struct { /// Whether the inline assembly code may perform stores to memory /// addresses other than those derived from input pointer provenance. diff --git a/lib/std/simd.zig b/lib/std/simd.zig index 08674a3573..237687b601 100644 --- a/lib/std/simd.zig +++ b/lib/std/simd.zig @@ -35,6 +35,8 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu) } else if (cpu.arch.isLoongArch()) { if (cpu.has(.loongarch, .lasx)) break :blk 256; if (cpu.has(.loongarch, .lsx)) break :blk 128; + } else if (cpu.arch == .m88k) { + if (cpu.has(.m88k, .sfu2)) break :blk 64; } else if (cpu.arch.isMIPS()) { if (cpu.has(.mips, .msa)) break :blk 128; if (cpu.has(.mips, .mips3d)) break :blk 64; @@ -65,7 +67,7 @@ pub fn suggestVectorLengthForCpu(comptime T: type, comptime cpu: std.Target.Cpu) break :blk 256; } } else if (cpu.arch == .s390x) { - if (cpu.has(.s390x, .vector)) break :blk 128; + if (cpu.has(.s390x, .vx)) break :blk 128; } else if (cpu.arch.isSPARC()) { if (cpu.hasAny(.sparc, &.{ .vis, .vis2, .vis3 })) break :blk 64; } else if (cpu.arch == .kvx) { diff --git a/lib/std/zig/llvm/Builder.zig b/lib/std/zig/llvm/Builder.zig index 39b4f6be0b..e770b9bf0d 100644 --- a/lib/std/zig/llvm/Builder.zig +++ b/lib/std/zig/llvm/Builder.zig @@ -153,7 +153,6 @@ pub fn tripleForTarget(allocator: Allocator, target: *const std.Target) ![]const .ez80, .hppa, .hppa64, - .kalimba, .kvx, .m88k, .microblaze, @@ -165,6 +164,7 @@ pub fn tripleForTarget(allocator: Allocator, target: *const std.Target) ![]const .spork8, .x86_16, .xtensaeb, + .z80, => unreachable, // Gated by hasLlvmSupport(). }; @@ -253,13 +253,10 @@ pub fn tripleForTarget(allocator: Allocator, target: *const std.Target) ![]const .ps5, => "scei", .amdhsa, - .amdpal, => "amd", .cuda, .nvcl, => "nvidia", - .mesa3d, - => "mesa", else => "unknown", }); try llvm_triple.append(allocator, '-'); @@ -281,8 +278,6 @@ pub fn tripleForTarget(allocator: Allocator, target: *const std.Target) ![]const .ps3 => "lv2", .ps4 => "ps4", .ps5 => "ps5", - .mesa3d => "mesa3d", - .amdpal => "amdpal", .hurd => "hurd", .wasi => "wasi", .emscripten => "emscripten", @@ -582,7 +577,6 @@ pub const DataLayout = struct { .ez80, .hppa, .hppa64, - .kalimba, .kvx, .m88k, .microblaze, @@ -591,9 +585,10 @@ pub const DataLayout = struct { .propeller, .sh, .sheb, + .spork8, .x86_16, .xtensaeb, - .spork8, + .z80, => unreachable, }; } diff --git a/lib/std/zig/system.zig b/lib/std/zig/system.zig index 70e2d4b6dd..f79cd2824f 100644 --- a/lib/std/zig/system.zig +++ b/lib/std/zig/system.zig @@ -388,13 +388,6 @@ pub fn resolveTargetQuery(io: Io, query: Target.Query) DetectError!Target { cpu.features.addFeature(@backingInt(Target.x86.Feature.@"32bit_mode")); } }, - .arm, .armeb => { - // XXX What do we do if the target has the noarm feature? - // What do we do if the user specifies +thumb_mode? - }, - .thumb, .thumbeb => { - cpu.features.addFeature(@backingInt(Target.arm.Feature.thumb_mode)); - }, else => {}, } updateCpuFeatures( @@ -434,25 +427,10 @@ pub fn resolveTargetQuery(io: Io, query: Target.Query) DetectError!Target { // These CPU feature hacks have to come after ABI detection. { - if (result.cpu.arch == .hexagon) { - // Both LLVM and LLD have broken support for the small data area. Yet LLVM has the - // feature on by default for all Hexagon CPUs. Clang sort of solves this by defaulting - // the `-gpsize` command line parameter for the Hexagon backend to 0, so that no - // constants get placed in the SDA. (This of course breaks down if the user passes - // `-G ` to Clang...) We can't do the `-gpsize` hack because we can have multiple - // concurrent LLVM emit jobs, and command line options in LLVM are shared globally. So - // just force this feature off. Lovely stuff. - result.cpu.features.removeFeature(@backingInt(Target.hexagon.Feature.small_data)); - } - // https://github.com/llvm/llvm-project/issues/105978 if (result.cpu.arch.isArm() and result.abi.float() == .soft) { result.cpu.features.removeFeature(@backingInt(Target.arm.Feature.vfp2)); } - - if (result.cpu.arch.isXtensa() and result.abi == .call0) { - result.cpu.features.removeFeature(@backingInt(Target.xtensa.Feature.windowed)); - } } // It's possible that we detect the native ABI, but fail to detect the OS version or were told diff --git a/lib/std/zig/system/freebsd.zig b/lib/std/zig/system/freebsd.zig index dc72463e20..962296feac 100644 --- a/lib/std/zig/system/freebsd.zig +++ b/lib/std/zig/system/freebsd.zig @@ -79,8 +79,7 @@ const arm = struct { const powerpc = struct { const models = .{ - .{ "Freescale e500v1 core", &std.Target.powerpc.cpu.e500 }, - .{ "Freescale e500v2 core", &std.Target.powerpc.cpu.e500v2 }, + .{ "Freescale e500v2 core", &std.Target.powerpc.cpu.e500 }, .{ "Freescale e500mc core", &std.Target.powerpc.cpu.e500mc }, .{ "Freescale e5500 core", &std.Target.powerpc.cpu.e5500 }, .{ "Freescale e6500 core", &std.Target.powerpc.cpu.e6500 }, diff --git a/lib/std/zig/system/linux.zig b/lib/std/zig/system/linux.zig index cddd75f27c..5348c88255 100644 --- a/lib/std/zig/system/linux.zig +++ b/lib/std/zig/system/linux.zig @@ -319,7 +319,6 @@ const mips = struct { .{ "mips32r5", &Target.mips.cpu.mips32r5 }, .{ "mips32r2", &Target.mips.cpu.mips32r2 }, .{ "mips32r1", &Target.mips.cpu.mips32 }, - .{ "mips5", &Target.mips.cpu.mips5 }, .{ "mips4", &Target.mips.cpu.mips4 }, .{ "mips3", &Target.mips.cpu.mips3 }, .{ "mips2", &Target.mips.cpu.mips2 }, @@ -448,8 +447,7 @@ const powerpc = struct { .{ "e300c3", &Target.powerpc.cpu.@"603e" }, .{ "e300c4", &Target.powerpc.cpu.@"603e" }, .{ "e500mc", &Target.powerpc.cpu.e500mc }, - .{ "e500v2", &Target.powerpc.cpu.e500v2 }, - .{ "e500", &Target.powerpc.cpu.e500 }, + .{ "e500v2", &Target.powerpc.cpu.e500 }, .{ "e5500", &Target.powerpc.cpu.e5500 }, .{ "e6500", &Target.powerpc.cpu.e6500 }, .{ "G2_LE", &Target.powerpc.cpu.@"603e" }, @@ -722,13 +720,13 @@ const riscv = struct { setFeature(&cpu, .zicbop, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZICBOP)); setFeature(&cpu, .zilsd, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZILSD)); setFeature(&cpu, .zclsd, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZCLSD)); - setFeature(&cpu, .experimental_zicfilp, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZICFILP)); + // setFeature(&cpu, .experimental_zicfilp, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZICFILP)); }, RISCV_HWPROBE.KEY.MISALIGNED_SCALAR_PERF => { - setFeature(&cpu, .unaligned_scalar_mem, value == RISCV_HWPROBE.MISALIGNED_SCALAR.FAST); + setFeature(&cpu, .unaligned_access, value == RISCV_HWPROBE.MISALIGNED_SCALAR.FAST); }, RISCV_HWPROBE.KEY.MISALIGNED_VECTOR_PERF => { - setFeature(&cpu, .unaligned_vector_mem, value == RISCV_HWPROBE.MISALIGNED_VECTOR.FAST); + setFeature(&cpu, .unaligned_vector_access, value == RISCV_HWPROBE.MISALIGNED_VECTOR.FAST); }, RISCV_HWPROBE.KEY.VENDOR_EXT_MIPS_0 => { setFeature(&cpu, .xmipsexectl, ima_support and set(value, RISCV_HWPROBE.MIPS_VENDOR_EXT_XMIPSEXECTL)); @@ -740,7 +738,7 @@ const riscv = struct { setFeature(&cpu, .xsfvfwmaccqqq, ima_support and set(value, RISCV_HWPROBE.SIFIVE_VENDOR_EXT.XSFVFWMACCQQQ)); }, RISCV_HWPROBE.KEY.IMA_EXT_1 => { - setFeature(&cpu, .experimental_zicfiss, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_1_EXT_ZICFISS)); + // setFeature(&cpu, .experimental_zicfiss, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_1_EXT_ZICFISS)); }, else => unreachable, } diff --git a/lib/std/zig/system/loongarch.zig b/lib/std/zig/system/loongarch.zig index 04a628e4e6..b70e113224 100644 --- a/lib/std/zig/system/loongarch.zig +++ b/lib/std/zig/system/loongarch.zig @@ -1,6 +1,23 @@ const builtin = @import("builtin"); const std = @import("std"); +const Prid = packed struct(u32) { + product: u12, + series: enum(u4) { + la132 = 0x8, + la264 = 0xa, + la364 = 0xb, + la464 = 0xc, + la664 = 0xd, + _, + }, + company: enum(u8) { + loongson = 0x14, + _, + }, + reserved: u8, +}; + const Variant = enum(u2) { la32r = 0b00, la32 = 0b01, @@ -19,25 +36,44 @@ fn setFeature(cpu: *std.Target.Cpu, feature: std.Target.loongarch.Feature, enabl } pub fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu { - const variant: Variant = @fromBackingInt(@intCast(cpucfg(1) & 0b11)); + const prid: Prid = @bitCast(cpucfg(0)); var cpu: std.Target.Cpu = .{ .arch = arch, - .model = switch (cpucfg(0) & 0b1111000000000000) { - else => switch (variant) { - .la32r, .la32 => &std.Target.loongarch.cpu.generic_la32, - .la64 => &std.Target.loongarch.cpu.generic_la64, - .reserved => unreachable, + .model = switch (arch) { + .loongarch32 => m: { + switch (prid.company) { + .loongson => switch (prid.series) { + .la132 => break :m &std.Target.loongarch.cpu.la132, + else => {}, + }, + else => {}, + } + + break :m &std.Target.loongarch.cpu.generic_la32; }, - 0xc000 => &std.Target.loongarch.cpu.la464, - 0xd000 => &std.Target.loongarch.cpu.la664, + .loongarch64 => m: { + switch (prid.company) { + .loongson => switch (prid.series) { + .la464 => break :m &std.Target.loongarch.cpu.la464, + .la664 => break :m &std.Target.loongarch.cpu.la664, + else => {}, + }, + else => {}, + } + + break :m &std.Target.loongarch.cpu.generic_la64; + }, + else => unreachable, }, .features = .empty, }; cpu.features.addFeatureSet(cpu.model.features); - setFeature(&cpu, .@"32s", variant != .la32r); + const variant: Variant = @fromBackingInt(@intCast(cpucfg(1) & 0b11)); + + setFeature(&cpu, .@"32s", variant == .la32 or variant == .la64); const cfg2 = cpucfg(2); const cfg3 = cpucfg(3); @@ -49,7 +85,7 @@ pub fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu { else std.os.linux.getauxval(std.elf.AT.HWCAP); - setFeature(&cpu, .ual, (hwcap_bits & HWCAP.UAL) != 0); + setFeature(&cpu, .unaligned_access, (hwcap_bits & HWCAP.UAL) != 0); const has_fpu = (hwcap_bits & HWCAP.FPU) != 0; setFeature(&cpu, .f, has_fpu and bit(cfg2, 1)); @@ -62,7 +98,7 @@ pub fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu { setFeature(&cpu, .lam_bh, (hwcap_bits & HWCAP.LAM_BH) != 0); } else { - setFeature(&cpu, .ual, false); + setFeature(&cpu, .unaligned_access, false); setFeature(&cpu, .f, false); setFeature(&cpu, .d, false); diff --git a/lib/std/zig/target.zig b/lib/std/zig/target.zig index ff82823c89..db68b5fbac 100644 --- a/lib/std/zig/target.zig +++ b/lib/std/zig/target.zig @@ -520,12 +520,12 @@ pub fn intAlignment(target: *const std.Target, bits: u16) u16 { } pub fn compilerRtFloatAbi(target: *const std.Target, bits: u16) std.Target.Abi.Float { - if (target.cpu.has(.x86, .soft_float)) return .soft; + if (target.cpu.arch.isX86() and target.abi.float() == .soft) return .soft; // Marks targets where clang does not even provide a usable C type. const no_c_type_available = .soft; switch (bits) { else => unreachable, - 16 => if (target.cpu.arch.isMIPS() or target.cpu.arch.isPowerPC()) return no_c_type_available, + 16 => if (target.cpu.arch.isMips() or target.cpu.arch.isPowerpc()) return no_c_type_available, 32, 64 => {}, 80 => if (target.cTypeBitSize(.longdouble) != 80) return no_c_type_available, 128 => { @@ -659,9 +659,7 @@ pub fn isNative(query: *const std.Target.Query, target: *const std.Target, host: .alu_lsl_fast, .avoid_ldapur, .disable_fast_inc_vl, - .exynos_cheap_as_move, .fast_ld1_single, - .fixed_load_latency_4, .fuse_address, .fuse_addsub_2reg_const1, .fuse_adrp_add, @@ -677,10 +675,6 @@ pub fn isNative(query: *const std.Target.Query, target: *const std.Target, host: .slow_misaligned_128store, .slow_paired_128, .slow_strqro_store, - .use_experimental_zeroing_pseudos, - .use_fixed_over_scalable_if_equal_cost, - .use_postra_scheduler, - .use_reciprocal_square_root, .use_wzr_to_vec_move, }), else => .empty, diff --git a/lib/zig.h b/lib/zig.h index b14912fc7f..dedaeb4f96 100644 --- a/lib/zig.h +++ b/lib/zig.h @@ -99,6 +99,8 @@ #define zig_x86 #elif defined(__xtensa__) #define zig_xtensa +#elif defined (__z80) +#define zig_z80 #elif defined (__ez80) #define zig_ez80 #define zig_z80 diff --git a/src/Compilation.zig b/src/Compilation.zig index db0dc95d27..0d14738cb3 100644 --- a/src/Compilation.zig +++ b/src/Compilation.zig @@ -92,8 +92,6 @@ windows_libs_num_done: u32, version: ?std.SemanticVersion, libc_installation: ?*const LibCInstallation, skip_linker_dependencies: bool, -function_sections: bool, -data_sections: bool, link_eh_frame_hdr: bool, native_system_include_paths: []const []const u8, /// List of symbols forced as undefined in the symbol table @@ -1486,8 +1484,6 @@ pub const CreateOptions = struct { /// executable this field is ignored. want_compiler_rt: ?bool = null, want_ubsan_rt: ?bool = null, - function_sections: bool = false, - data_sections: bool = false, time_report: bool = false, stack_report: bool = false, link_eh_frame_hdr: bool = false, @@ -1945,8 +1941,8 @@ pub fn create(gpa: Allocator, arena: Allocator, io: Io, diag: *CreateDiagnostic, cache.hash.add(options.config.any_sanitize_thread); cache.hash.add(options.config.any_sanitize_c); cache.hash.add(options.config.any_fuzz); - cache.hash.add(options.function_sections); - cache.hash.add(options.data_sections); + cache.hash.add(options.config.function_sections); + cache.hash.add(options.config.data_sections); cache.hash.add(link_libc); cache.hash.add(options.config.link_libcpp); cache.hash.add(options.config.link_libunwind); @@ -2164,8 +2160,6 @@ pub fn create(gpa: Allocator, arena: Allocator, io: Io, diag: *CreateDiagnostic, .llvm_opt_bisect_limit = options.llvm_opt_bisect_limit, .skip_linker_dependencies = options.skip_linker_dependencies, .queued_jobs = .{}, - .function_sections = options.function_sections, - .data_sections = options.data_sections, .native_system_include_paths = options.native_system_include_paths, .force_undefined_symbols = options.force_undefined_symbols, .link_eh_frame_hdr = link_eh_frame_hdr, @@ -6673,15 +6667,36 @@ pub fn addCCArgs( }); } + if (target.cpu.arch == .hexagon) { + try argv.append("-G0"); // Unsupported by LLD. + } + // We might want to support -mfloat-abi=softfp for Arm and CSKY here in the future. if (target_util.clangSupportsFloatAbiArg(target)) { - const fabi = @tagName(target.abi.float()); + const fabi = target.abi.float(); try argv.append(switch (target.cpu.arch) { // For whatever reason, Clang doesn't support `-mfloat-abi` for s390x. - .s390x => try std.fmt.allocPrint(arena, "-m{s}-float", .{fabi}), - else => try std.fmt.allocPrint(arena, "-mfloat-abi={s}", .{fabi}), + .s390x => try std.fmt.allocPrint(arena, "-m{s}-float", .{@tagName(fabi)}), + else => try std.fmt.allocPrint(arena, "-mfloat-abi={s}", .{@tagName(fabi)}), }); + + if (target.cpu.arch.isMips() and fabi == .hard) { + try argv.appendSlice(if (target.cpu.has(.mips, .single_float)) + &.{ "-msingle-float", "-mno-odd-spreg" } + else if (target.cpu.arch.isMips64() or target.cpu.hasAny(.mips, &.{ .mips32r6, .msa })) + &.{ "-mfp64", "-modd-spreg" } + else if (target.cpu.has(.mips, .mips2)) + &.{ "-mfpxx", "-mno-odd-spreg" } + else + &.{ "-mfp32", "-mno-odd-spreg" }); + } + } + + if (target.cpu.arch.isX86() and target.abi.float() == .soft) { + // This is necessary to get the effects of the `soft-float` backend + // subtarget feature in the frontend as well. + try argv.append("-mgeneral-regs-only"); } if (mod.patchable_function_entry > 0) { @@ -6689,12 +6704,25 @@ pub fn addCCArgs( try argv.append(try std.fmt.allocPrint(arena, "-fpatchable-function-entry={}", .{pf})); } + if (target.cpu.arch.isMips()) { + try argv.append(if (mod.pic) "-mabicalls" else "-mno-abicalls"); + } + try comp.addCommonCCArgs(arena, argv, ext, out_dep_path, mod, comp.config.c_frontend); // Non-preprocessed assembly files don't support these flags. if (ext != .assembly) { - if (target_util.clangSupportsNoImplicitFloatArg(target) and target.abi.float() == .soft) { - try argv.append("-mno-implicit-float"); + if (target.abi.float() == .soft) { + if (target_util.clangSupportsNoImplicitFloatArg(target)) { + try argv.append("-mno-implicit-float"); + } + + // Ensure that Clang emits the `use-soft-float` function attribute. + try argv.appendSlice(&.{ "-Xclang", "-msoft-float" }); + } + + if (target.cpu.arch.isMips() and !mod.pic) { + try argv.append("-mno-gpopt"); } if (target_util.hasRedZone(target)) { @@ -6719,8 +6747,8 @@ pub fn addCCArgs( try argv.append(if (mod.no_builtin) "-fno-builtin" else "-fbuiltin"); - try argv.append(if (comp.function_sections) "-ffunction-sections" else "-fno-function-sections"); - try argv.append(if (comp.data_sections) "-fdata-sections" else "-fno-data-sections"); + try argv.append(if (comp.config.function_sections) "-ffunction-sections" else "-fno-function-sections"); + try argv.append(if (comp.config.data_sections) "-fdata-sections" else "-fno-data-sections"); switch (mod.unwind_tables) { .none => { @@ -6776,17 +6804,9 @@ pub fn addCCArgs( if (feature.llvm_name) |llvm_name| { // We communicate these to Clang through the dedicated options. - if (std.mem.startsWith(u8, llvm_name, "soft-float") or - std.mem.startsWith(u8, llvm_name, "hard-float") or - (target.cpu.arch.isPowerPC() and std.mem.startsWith(u8, llvm_name, "64bit")) or - (target.cpu.arch.isX86() and std.mem.startsWith(u8, llvm_name, "x32")) or - (target.cpu.arch == .s390x and std.mem.eql(u8, llvm_name, "backchain"))) + if (std.mem.startsWith(u8, llvm_name, "soft-float") or std.mem.startsWith(u8, llvm_name, "hard-float")) continue; - // Ignore these until we figure out how to handle the concept of omitting features. - // See https://github.com/ziglang/zig/issues/23539 - if (target_util.isDynamicAMDGCNFeature(target, feature)) continue; - const plus_or_minus = "-+"[@intFromBool(is_enabled)]; const arg = try std.fmt.allocPrint(arena, "{c}{s}", .{ plus_or_minus, llvm_name }); for (xclang_flags) |xclang| { @@ -6794,6 +6814,28 @@ pub fn addCCArgs( } } } + + if (target.cpu.arch.isPowerpc32()) { + // https://github.com/llvm/llvm-project/issues/235393 + for (xclang_flags) |xclang| try argv.appendSlice(&.{ + xclang, + "-target-feature", + xclang, + "-crbits", + }); + } + + if (target.cpu.arch.isXtensa()) { + // LLVM does not currently support specifying windowed vs call0 ABI any other way than + // disabling all windowed instructions altogether. That's kind of silly because a + // windowed core can do call0 just fine. + if (target.abi == .call0) for (xclang_flags) |xclang| try argv.appendSlice(&.{ + xclang, + "-target-feature", + xclang, + "-windowed", + }); + } }, else => {}, } @@ -7346,6 +7388,8 @@ fn buildOutputFromZig( .any_error_tracing = false, .root_error_tracing = false, .lto = if (options.allow_lto) comp.config.lto else .none, + .function_sections = true, + .data_sections = true, }) catch |err| { comp.lockAndSetMiscFailure(misc_task_tag, "sub-compilation of {t} failed: failed to resolve compilation config: {t}", .{ misc_task_tag, err }); return error.AlreadyReported; @@ -7407,8 +7451,6 @@ fn buildOutputFromZig( .root_name = root_name, .libc_installation = comp.libc_installation, .emit_bin = .yes_cache, - .function_sections = true, - .data_sections = true, .verbose_cc = comp.verbose_cc, .verbose_link = comp.verbose_link, .clang_passthrough_mode = comp.clang_passthrough_mode, @@ -7486,6 +7528,8 @@ pub fn build_crt_file( .Lib => if (options.allow_lto) comp.config.lto else .none, .Obj, .Exe => .none, }, + .function_sections = options.function_sections, + .data_sections = options.data_sections, }) catch |err| { comp.lockAndSetMiscFailure(misc_task_tag, "sub-compilation of {t} failed: failed to resolve compilation config: {t}", .{ misc_task_tag, err }); return error.AlreadyReported; @@ -7537,8 +7581,6 @@ pub fn build_crt_file( .root_name = root_name, .libc_installation = comp.libc_installation, .emit_bin = .yes_cache, - .function_sections = options.function_sections, - .data_sections = options.data_sections, .c_source_files = c_source_files, .verbose_cc = comp.verbose_cc, .verbose_link = comp.verbose_link, diff --git a/src/Compilation/Config.zig b/src/Compilation/Config.zig index 0294268834..1372682e7e 100644 --- a/src/Compilation/Config.zig +++ b/src/Compilation/Config.zig @@ -65,6 +65,8 @@ root_error_tracing: bool, dll_export_fns: bool, rdynamic: bool, san_cov_trace_pc_guard: bool, +function_sections: bool, +data_sections: bool, pub const CFrontend = enum { clang, aro }; @@ -119,6 +121,8 @@ pub const Options = struct { dll_export_fns: ?bool = null, rdynamic: ?bool = null, san_cov_trace_pc_guard: bool = false, + function_sections: ?bool = null, + data_sections: ?bool = null, }; pub const ResolveError = error{ @@ -556,6 +560,55 @@ pub fn resolve(options: Options) ResolveError!Config { }; }; + const function_sections = b: { + if (options.function_sections) |x| break :b x; + + // Xtensa *really* wants per-function literal pools or branches will start to break once the + // program grows past 256 KiB. This can only be accomplished with function sections. + if (target.cpu.arch.isXtensa()) break :b true; + + break :b switch (backend) { + // LLVM uses short branches on these targets and is not capable of intelligently using + // long branches when the output object grows big enough. So on these targets, it makes + // for a better user experience to enable function sections by default. + // + // Rule of thumb: If a target needs thunks to reach +/- 2 GiB, it belongs on this list. + .stage2_llvm => switch (target.cpu.arch) { + // +/- 128 MiB + .aarch64, + .aarch64_be, + // +/- 32 MiB + .arm, + .armeb, + // +/- 8 MiB + .hexagon, + // +/- 32 KiB + .m68k, + // 256 MiB region + .mips, + .mipsel, + .mips64, + .mips64el, + // +/- 32 MiB + .powerpc, + .powerpcle, + .powerpc64, + .powerpc64le, + // +/- 4 MiB (Thumb-1), 16 MiB (Thumb-2) + .thumb, + .thumbeb, + => true, + else => false, + }, + else => false, + }; + }; + + const data_sections = b: { + if (options.data_sections) |x| break :b x; + break :b false; + }; + return .{ .output_mode = options.output_mode, .have_zcu = options.have_zcu, @@ -590,6 +643,8 @@ pub fn resolve(options: Options) ResolveError!Config { .root_strip = root_strip, .dll_export_fns = dll_export_fns, .rdynamic = rdynamic, + .function_sections = function_sections, + .data_sections = data_sections, }; } diff --git a/src/Module.zig b/src/Module.zig index 02df432d5e..e455ad89d0 100644 --- a/src/Module.zig +++ b/src/Module.zig @@ -184,9 +184,8 @@ pub fn create(arena: Allocator, options: CreateOptions) !*Module { return error.PieRequiresPic; break :b true; } - if (options.global.output_mode == .Lib and - options.global.link_mode == .dynamic and - target_util.requiresPicForDynamicLink(target)) + if (options.global.link_mode == .dynamic and + target_util.requiresPicForDynamicLink(target, options.global.output_mode)) { if (options.inherited.pic == false) return error.DynamicLinkingRequiresPic; @@ -371,19 +370,7 @@ pub fn create(arena: Allocator, options: CreateOptions) !*Module { var disabled_features = std.array_list.Managed(u8).init(arena); for (target.cpu.arch.allFeaturesList()) |feature| { if (feature.llvm_name) |llvm_name| { - // Ignore these until we figure out how to handle the concept of omitting features. - // See https://github.com/ziglang/zig/issues/23539 - if (target_util.isDynamicAMDGCNFeature(target, feature)) continue; - - if (target.cpu.arch.isPowerPC() and @as(std.Target.powerpc.Feature, @fromBackingInt(@intCast(feature.index))) == .@"64bit") continue; - if (target.cpu.arch.isX86() and @as(std.Target.x86.Feature, @fromBackingInt(@intCast(feature.index))) == .x32) continue; - - var is_enabled = target.cpu.features.isEnabled(feature.index); - if (target.cpu.arch == .s390x and @as(std.Target.s390x.Feature, @fromBackingInt(@intCast(feature.index))) == .backchain) { - is_enabled = !omit_frame_pointer; - } - - if (is_enabled) { + if (target.cpu.features.isEnabled(feature.index)) { try buf.ensureUnusedCapacity(2 + llvm_name.len); buf.appendAssumeCapacity('+'); buf.appendSliceAssumeCapacity(llvm_name); @@ -396,8 +383,47 @@ pub fn create(arena: Allocator, options: CreateOptions) !*Module { } } } - try buf.appendSlice(disabled_features.items); + + if (target.cpu.arch.isArm()) { + try buf.append(if (target.cpu.arch.isThumb()) '+' else '-'); + try buf.appendSlice("thumb-mode,"); + } + + if (target.cpu.arch == .hexagon) { + try buf.appendSlice("-small-data,"); // Unsupported by LLD. + } + + if (target.cpu.arch.isMips()) { + try buf.append(if (pic) '-' else '+'); + try buf.appendSlice("noabicalls,"); + try buf.appendSlice(if (target.cpu.has(.mips, .single_float)) + "-fpxx,+nooddspreg," + else if (target.cpu.arch.isMips64() or target.cpu.hasAny(.mips, &.{ .mips32r6, .msa })) + "-fpxx,-nooddspreg,+fp64," + else if (target.cpu.has(.mips, .mips2)) + "+fpxx,+nooddspreg," + else + "-fpxx,+nooddspreg,"); + } + + if (target.cpu.arch.isPowerpc32()) { + // https://github.com/llvm/llvm-project/issues/235393 + try buf.appendSlice("-crbits,"); + } + + if (target.cpu.arch == .s390x) { + try buf.append(if (omit_frame_pointer) '-' else '+'); + try buf.appendSlice("backchain,"); + } + + if (target.cpu.arch.isXtensa()) { + // LLVM does not currently support specifying windowed vs call0 ABI any other way than + // disabling all windowed instructions altogether. That's kind of silly because a + // windowed core can do call0 just fine. + if (target.abi == .call0) try buf.appendSlice("-windowed,"); + } + if (buf.items.len == 0) break :b ""; assert(buf.items[buf.items.len - 1] == ','); buf.items[buf.items.len - 1] = 0; diff --git a/src/Sema.zig b/src/Sema.zig index d0ec10cea9..67d96add87 100644 --- a/src/Sema.zig +++ b/src/Sema.zig @@ -8522,7 +8522,7 @@ pub fn handleExternLibName( .{lib_name}, ); } - if (!block.ownerModule().pic and target_util.requiresPicForDynamicLink(target)) { + if (!block.ownerModule().pic and target_util.requiresPicForDynamicLink(target, comp.config.output_mode)) { return sema.fail( block, src_loc, diff --git a/src/Zcu.zig b/src/Zcu.zig index d8a0fb55e2..8748802d2e 100644 --- a/src/Zcu.zig +++ b/src/Zcu.zig @@ -4223,6 +4223,7 @@ pub fn atomicPtrAlignment( const max_atomic_bits: u16 = switch (target.cpu.arch) { .ez80, .spork8, + .z80, => 8, .aarch64, @@ -4807,6 +4808,7 @@ pub fn callconvSupported(zcu: *Zcu, cc: std.lang.CallingConvention) union(enum) .avr_interrupt, .avr_signal, .ez80_tiflags, + .z80_tiflags, .loongarch32_preserve_none, .loongarch64_preserve_none, .riscv32_preserve_most, diff --git a/src/codegen/c/type.zig b/src/codegen/c/type.zig index c05b29ee89..b23614ef1b 100644 --- a/src/codegen/c/type.zig +++ b/src/codegen/c/type.zig @@ -223,7 +223,9 @@ pub const CType = union(enum) { .x86_64_interrupt, => .interrupt, - .ez80_tiflags => .tiflags, + .z80_tiflags, + .ez80_tiflags, + => .tiflags, else => unreachable, // `Zcu.callconvSupported` }; diff --git a/src/codegen/llvm.zig b/src/codegen/llvm.zig index 61c5eebf99..bf44a49b6b 100644 --- a/src/codegen/llvm.zig +++ b/src/codegen/llvm.zig @@ -623,8 +623,8 @@ pub const Object = struct { opt_level, reloc_mode, code_model, - comp.function_sections, - comp.data_sections, + comp.config.function_sections, + comp.config.data_sections, switch (target.abi.float()) { .hard => .Hard, .soft => .Soft, @@ -4500,6 +4500,8 @@ pub fn toLlvmCallConvTag(cc_tag: std.lang.CallingConvention.Tag, target: *const .avr_gnu, .bpf_std, .csky_sysv, + .z80_cet, + .z80_tiflags, .ez80_cet, .ez80_tiflags, .hexagon_sysv, @@ -4802,7 +4804,6 @@ pub fn initializeLLVMTarget(io: Io, arch: std.Target.Cpu.Arch) void { .ez80, .hppa, .hppa64, - .kalimba, .kvx, .m88k, .microblaze, @@ -4814,6 +4815,7 @@ pub fn initializeLLVMTarget(io: Io, arch: std.Target.Cpu.Arch) void { .spork8, .x86_16, .xtensaeb, + .z80, => unreachable, } } diff --git a/src/codegen/llvm/FuncGen.zig b/src/codegen/llvm/FuncGen.zig index 1f78dc4804..36c5ed0a9a 100644 --- a/src/codegen/llvm/FuncGen.zig +++ b/src/codegen/llvm/FuncGen.zig @@ -5299,25 +5299,7 @@ fn airLoad(fg: *FuncGen, inst: Air.Inst.Index) Allocator.Error!Builder.Value { fn airTrap(self: *FuncGen, inst: Air.Inst.Index) Allocator.Error!void { _ = inst; - const target = self.object.zcu.getTarget(); - if ((target.cpu.arch == .mips or target.cpu.arch == .mipsel) and - target.cpu.has(.mips, .notraps)) - { - // Emit a MIPS `break` instruction followed by an infinite loop (to fulfil the noreturn) - // since this CPU does not support trap instructions. - const o = self.object; - _ = try self.wip.callAsm( - .none, - try o.builder.fnType(.void, &.{}, .normal), - .{ .sideeffect = true }, - try o.builder.string("break\n0:\nj 0b\nnop"), - try o.builder.string("~{memory}"), - &.{}, - "", - ); - } else { - _ = try self.wip.callIntrinsic(.normal, .none, .trap, &.{}, &.{}, ""); - } + _ = try self.wip.callIntrinsic(.normal, .none, .trap, &.{}, &.{}, ""); _ = try self.wip.@"unreachable"(); } diff --git a/src/codegen/loongarch/Select.zig b/src/codegen/loongarch/Select.zig index a764c0776a..0f283145ac 100644 --- a/src/codegen/loongarch/Select.zig +++ b/src/codegen/loongarch/Select.zig @@ -3998,7 +3998,7 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) codegen.Error!void defer dst_vi.value.deref(isel); // TODO unaligned loads - assert(isel.target.cpu.has(.loongarch, .ual)); + assert(isel.target.cpu.has(.loongarch, .unaligned_access)); const ptr_vi = try isel.use(ty_op.operand); const ptr_mat = try ptr_vi.matIntRegZeroExt(isel); _ = try dst_vi.value.defLoad(isel, ptr_mat.reg(), 0, .{ diff --git a/src/codegen/loongarch/abi.zig b/src/codegen/loongarch/abi.zig index ba9b79d39d..a35b3fd94e 100644 --- a/src/codegen/loongarch/abi.zig +++ b/src/codegen/loongarch/abi.zig @@ -49,12 +49,11 @@ const Classifier = struct { .loongarch32 => 32, .loongarch64 => 64, }, - .frlen = if (target.cpu.has(.loongarch, .d)) - 64 - else if (target.cpu.has(.loongarch, .f)) - 32 - else - 0, + .frlen = switch (target.abi) { + .gnusf, .muslsf => 0, + .gnuf32, .muslf32 => 32, + else => 64, + }, }; } diff --git a/src/codegen/spirv/spec.zig b/src/codegen/spirv/spec.zig index 2a6a90d444..2b40a41915 100644 --- a/src/codegen/spirv/spec.zig +++ b/src/codegen/spirv/spec.zig @@ -86,7 +86,6 @@ pub const Enumerant = struct { }; pub const zig_generator_id: u16 = 41; -pub const version: Version = .{ .major = 1, .minor = 6, .patch = 4 }; pub const magic_number: Word = 0x07230203; pub const Class = enum { @@ -175,6 +174,7 @@ pub const OperandKind = enum { fp_encoding, cooperative_vector_matrix_layout, component_type, + gather_modes, id_result_type, id_result, id_memory_semantics, @@ -257,6 +257,7 @@ pub const OperandKind = enum { .fp_encoding => .value_enum, .cooperative_vector_matrix_layout => .value_enum, .component_type => .value_enum, + .gather_modes => .value_enum, .id_result_type => .id, .id_result => .id, .id_memory_semantics => .id, @@ -326,6 +327,7 @@ pub const OperandKind = enum { .{ .name = "IterationMultiple", .value = 0x0040, .parameters = &.{.{ .kind = .literal_integer }} }, .{ .name = "PeelCount", .value = 0x0080, .parameters = &.{.{ .kind = .literal_integer }} }, .{ .name = "PartialCount", .value = 0x0100, .parameters = &.{.{ .kind = .literal_integer }} }, + .{ .name = "MultipleWaitQueuesQCOM", .value = 0x10000000, .parameters = &.{.{ .kind = .literal_integer }} }, }, .function_control => &.{ .{ .name = "Inline", .value = 0x0001, .parameters = &.{} }, @@ -374,7 +376,7 @@ pub const OperandKind = enum { .{ .name = "CullNoOpaqueKHR", .value = 0x0080, .parameters = &.{} }, .{ .name = "SkipTrianglesKHR", .value = 0x0100, .parameters = &.{} }, .{ .name = "SkipAABBsKHR", .value = 0x0200, .parameters = &.{} }, - .{ .name = "ForceOpacityMicromap2StateEXT", .value = 0x0400, .parameters = &.{} }, + .{ .name = "ForceOpacityMicromap2StateKHR", .value = 0x0400, .parameters = &.{} }, }, .fragment_shading_rate => &.{ .{ .name = "Vertical2Pixels", .value = 0x0001, .parameters = &.{} }, @@ -398,6 +400,8 @@ pub const OperandKind = enum { .{ .name = "Slang", .value = 11, .parameters = &.{} }, .{ .name = "Zig", .value = 12, .parameters = &.{} }, .{ .name = "Rust", .value = 13, .parameters = &.{} }, + .{ .name = "Pred", .value = 14, .parameters = &.{} }, + .{ .name = "ApilaJai", .value = 15, .parameters = &.{} }, }, .execution_model => &.{ .{ .name = "Vertex", .value = 0, .parameters = &.{} }, @@ -486,7 +490,6 @@ pub const OperandKind = enum { .{ .name = "StencilRefLessBackAMD", .value = 5084, .parameters = &.{} }, .{ .name = "QuadDerivativesKHR", .value = 5088, .parameters = &.{} }, .{ .name = "RequireFullQuadsKHR", .value = 5089, .parameters = &.{} }, - .{ .name = "ArithmeticPoisonKHR", .value = 5157, .parameters = &.{} }, .{ .name = "OutputLinesEXT", .value = 5269, .parameters = &.{} }, .{ .name = "OutputPrimitivesEXT", .value = 5270, .parameters = &.{.{ .kind = .literal_integer }} }, .{ .name = "DerivativeGroupQuadsKHR", .value = 5289, .parameters = &.{} }, @@ -501,6 +504,7 @@ pub const OperandKind = enum { .{ .name = "Shader64BitIndexingEXT", .value = 5427, .parameters = &.{} }, .{ .name = "MaximallyReconvergesKHR", .value = 6023, .parameters = &.{} }, .{ .name = "FPFastMathDefault", .value = 6028, .parameters = &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } } }, + .{ .name = "OpacityMicromapIdKHR", .value = 6031, .parameters = &.{.{ .kind = .id_ref }} }, }, .storage_class => &.{ .{ .name = "UniformConstant", .value = 0, .parameters = &.{} }, @@ -734,6 +738,7 @@ pub const OperandKind = enum { .{ .name = "RestrictPointer", .value = 5355, .parameters = &.{} }, .{ .name = "AliasedPointer", .value = 5356, .parameters = &.{} }, .{ .name = "HitObjectShaderRecordBufferEXT", .value = 5389, .parameters = &.{} }, + .{ .name = "CooperativeMatrixTransposeEXT", .value = 5440, .parameters = &.{} }, .{ .name = "CounterBuffer", .value = 5634, .parameters = &.{.{ .kind = .id_ref }} }, .{ .name = "UserSemantic", .value = 5635, .parameters = &.{.{ .kind = .literal_string }} }, }, @@ -890,6 +895,8 @@ pub const OperandKind = enum { .{ .name = "InputAttachment", .value = 40, .parameters = &.{} }, .{ .name = "SparseResidency", .value = 41, .parameters = &.{} }, .{ .name = "MinLod", .value = 42, .parameters = &.{} }, + .{ .name = "Sampled1D", .value = 43, .parameters = &.{} }, + .{ .name = "Image1D", .value = 44, .parameters = &.{} }, .{ .name = "SampledCubeArray", .value = 45, .parameters = &.{} }, .{ .name = "SampledBuffer", .value = 46, .parameters = &.{} }, .{ .name = "ImageBuffer", .value = 47, .parameters = &.{} }, @@ -922,6 +929,11 @@ pub const OperandKind = enum { .{ .name = "TileImageStencilReadAccessEXT", .value = 4168, .parameters = &.{} }, .{ .name = "Float8EXT", .value = 4212, .parameters = &.{} }, .{ .name = "Float8CooperativeMatrixEXT", .value = 4213, .parameters = &.{} }, + .{ .name = "Float6EXT", .value = 4228, .parameters = &.{} }, + .{ .name = "Float4EXT", .value = 4229, .parameters = &.{} }, + .{ .name = "Float8UnsignedE8M0EXT", .value = 4230, .parameters = &.{} }, + .{ .name = "MXInt8EXT", .value = 4231, .parameters = &.{} }, + .{ .name = "BitcastExtractEXT", .value = 4232, .parameters = &.{} }, .{ .name = "FragmentShadingRateKHR", .value = 4422, .parameters = &.{} }, .{ .name = "SubgroupBallotKHR", .value = 4423, .parameters = &.{} }, .{ .name = "DrawParameters", .value = 4427, .parameters = &.{} }, @@ -945,7 +957,8 @@ pub const OperandKind = enum { .{ .name = "DenormPreserve", .value = 4464, .parameters = &.{} }, .{ .name = "DenormFlushToZero", .value = 4465, .parameters = &.{} }, .{ .name = "SignedZeroInfNanPreserve", .value = 4466, .parameters = &.{} }, - .{ .name = "RayQueryProvisionalKHR", .value = 4471, .parameters = &.{} }, + .{ .name = "RoundingModeRTE", .value = 4467, .parameters = &.{} }, + .{ .name = "RoundingModeRTZ", .value = 4468, .parameters = &.{} }, .{ .name = "RayQueryKHR", .value = 4472, .parameters = &.{} }, .{ .name = "UntypedPointersKHR", .value = 4473, .parameters = &.{} }, .{ .name = "RayTraversalPrimitiveCullingKHR", .value = 4478, .parameters = &.{} }, @@ -960,7 +973,6 @@ pub const OperandKind = enum { .{ .name = "AbortKHR", .value = 5120, .parameters = &.{} }, .{ .name = "DescriptorHeapEXT", .value = 5128, .parameters = &.{} }, .{ .name = "ConstantDataKHR", .value = 5146, .parameters = &.{} }, - .{ .name = "PoisonFreezeKHR", .value = 5156, .parameters = &.{} }, .{ .name = "ShaderViewportIndexLayerEXT", .value = 5254, .parameters = &.{} }, .{ .name = "FragmentFullyCoveredEXT", .value = 5265, .parameters = &.{} }, .{ .name = "MeshShadingEXT", .value = 5283, .parameters = &.{} }, @@ -985,16 +997,19 @@ pub const OperandKind = enum { .{ .name = "VulkanMemoryModelDeviceScope", .value = 5346, .parameters = &.{} }, .{ .name = "PhysicalStorageBufferAddresses", .value = 5347, .parameters = &.{} }, .{ .name = "ComputeDerivativeGroupLinearKHR", .value = 5350, .parameters = &.{} }, - .{ .name = "RayTracingProvisionalKHR", .value = 5353, .parameters = &.{} }, .{ .name = "FragmentShaderSampleInterlockEXT", .value = 5363, .parameters = &.{} }, .{ .name = "FragmentShaderShadingRateInterlockEXT", .value = 5372, .parameters = &.{} }, .{ .name = "FragmentShaderPixelInterlockEXT", .value = 5378, .parameters = &.{} }, .{ .name = "DemoteToHelperInvocation", .value = 5379, .parameters = &.{} }, - .{ .name = "RayTracingOpacityMicromapEXT", .value = 5381, .parameters = &.{} }, + .{ .name = "RayTracingOpacityMicromapKHR", .value = 5381, .parameters = &.{} }, .{ .name = "ShaderInvocationReorderEXT", .value = 5388, .parameters = &.{} }, .{ .name = "RayQueryPositionFetchKHR", .value = 5391, .parameters = &.{} }, .{ .name = "LongVectorEXT", .value = 5425, .parameters = &.{} }, .{ .name = "Shader64BitIndexingEXT", .value = 5426, .parameters = &.{} }, + .{ .name = "CooperativeMatrixConversionsEXT", .value = 5429, .parameters = &.{} }, + .{ .name = "CooperativeMatrixReductionsEXT", .value = 5430, .parameters = &.{} }, + .{ .name = "CooperativeMatrixPerElementOperationsEXT", .value = 5432, .parameters = &.{} }, + .{ .name = "CooperativeMatrixGetCoordinateEXT", .value = 5438, .parameters = &.{} }, .{ .name = "AtomicFloat32MinMaxEXT", .value = 5612, .parameters = &.{} }, .{ .name = "AtomicFloat64MinMaxEXT", .value = 5613, .parameters = &.{} }, .{ .name = "AtomicFloat16MinMaxEXT", .value = 5616, .parameters = &.{} }, @@ -1010,10 +1025,12 @@ pub const OperandKind = enum { .{ .name = "GroupNonUniformRotateKHR", .value = 6026, .parameters = &.{} }, .{ .name = "FloatControls2", .value = 6029, .parameters = &.{} }, .{ .name = "FMAKHR", .value = 6030, .parameters = &.{} }, + .{ .name = "RayTracingOpacityMicromapExecutionModeKHR", .value = 6032, .parameters = &.{} }, .{ .name = "AtomicFloat32AddEXT", .value = 6033, .parameters = &.{} }, .{ .name = "AtomicFloat64AddEXT", .value = 6034, .parameters = &.{} }, .{ .name = "OptNoneEXT", .value = 6094, .parameters = &.{} }, .{ .name = "AtomicFloat16AddEXT", .value = 6095, .parameters = &.{} }, + .{ .name = "SplitBarrierEXT", .value = 6141, .parameters = &.{} }, .{ .name = "ArithmeticFenceEXT", .value = 6144, .parameters = &.{} }, .{ .name = "GroupUniformArithmeticKHR", .value = 6400, .parameters = &.{} }, }, @@ -1087,6 +1104,11 @@ pub const OperandKind = enum { .{ .name = "BFloat16KHR", .value = 0, .parameters = &.{} }, .{ .name = "Float8E4M3EXT", .value = 4214, .parameters = &.{} }, .{ .name = "Float8E5M2EXT", .value = 4215, .parameters = &.{} }, + .{ .name = "Float6E2M3EXT", .value = 4223, .parameters = &.{} }, + .{ .name = "Float6E3M2EXT", .value = 4224, .parameters = &.{} }, + .{ .name = "Float4E2M1EXT", .value = 4225, .parameters = &.{} }, + .{ .name = "Float8UnsignedE8M0EXT", .value = 4226, .parameters = &.{} }, + .{ .name = "MXInt8EXT", .value = 4227, .parameters = &.{} }, }, .cooperative_vector_matrix_layout => &.{ .{ .name = "RowMajorNV", .value = 0, .parameters = &.{} }, @@ -1111,6 +1133,12 @@ pub const OperandKind = enum { .{ .name = "FloatE4M3NV", .value = 1000491002, .parameters = &.{} }, .{ .name = "FloatE5M2NV", .value = 1000491003, .parameters = &.{} }, }, + .gather_modes => &.{ + .{ .name = "Gather4x1QCOM", .value = 0, .parameters = &.{} }, + .{ .name = "GatherDQCOM", .value = 1, .parameters = &.{} }, + .{ .name = "GatherH2QCOM", .value = 2, .parameters = &.{} }, + .{ .name = "GatherV2QCOM", .value = 3, .parameters = &.{} }, + }, .id_result_type => unreachable, .id_result => unreachable, .id_memory_semantics => unreachable, @@ -1548,6 +1576,7 @@ pub const Opcode = enum(u16) { OpColorAttachmentReadEXT = 4160, OpDepthAttachmentReadEXT = 4161, OpStencilAttachmentReadEXT = 4162, + OpBitcastExtractEXT = 4195, OpTerminateInvocation = 4416, OpTypeUntypedPointerKHR = 4417, OpUntypedVariableKHR = 4418, @@ -1604,9 +1633,8 @@ pub const Opcode = enum(u16) { OpConstantSizeOfEXT = 5129, OpConstantDataKHR = 5147, OpSpecConstantDataKHR = 5148, - OpPoisonKHR = 5158, - OpFreezeKHR = 5159, OpTypeVectorIdEXT = 5288, + OpCooperativeMatrixConvertUseEXT = 5293, OpEmitMeshTasksEXT = 5294, OpSetMeshOutputsEXT = 5295, OpGroupNonUniformPartitionEXT = 5296, @@ -1649,8 +1677,11 @@ pub const Opcode = enum(u16) { OpHitObjectIsEmptyEXT = 5350, OpHitObjectIsHitEXT = 5351, OpHitObjectIsMissEXT = 5352, + OpCooperativeMatrixGetCoordinateEXT = 5363, OpBeginInvocationInterlockEXT = 5364, OpEndInvocationInterlockEXT = 5365, + OpCooperativeMatrixReduceEXT = 5366, + OpCooperativeMatrixPerElementOpEXT = 5369, OpDemoteToHelperInvocation = 5380, OpIsHelperInvocationEXT = 5381, OpAtomicFMinEXT = 5614, @@ -1677,6 +1708,8 @@ pub const Opcode = enum(u16) { OpRayQueryGetIntersectionObjectToWorldKHR = 6031, OpRayQueryGetIntersectionWorldToObjectKHR = 6032, OpAtomicFAddEXT = 6035, + OpControlBarrierArriveEXT = 6142, + OpControlBarrierWaitEXT = 6143, OpArithmeticFenceEXT = 6145, OpGroupIMulKHR = 6401, OpGroupFMulKHR = 6402, @@ -2036,6 +2069,7 @@ pub const Opcode = enum(u16) { .OpColorAttachmentReadEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, .OpDepthAttachmentReadEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref, .quantifier = .optional } }, .OpStencilAttachmentReadEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref, .quantifier = .optional } }, + .OpBitcastExtractEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, .OpTerminateInvocation => &.{}, .OpTypeUntypedPointerKHR => &.{ .{ .kind = .id_result }, .{ .kind = .storage_class } }, .OpUntypedVariableKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .storage_class }, .{ .kind = .id_ref, .quantifier = .optional }, .{ .kind = .id_ref, .quantifier = .optional } }, @@ -2092,13 +2126,12 @@ pub const Opcode = enum(u16) { .OpConstantSizeOfEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, .OpConstantDataKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .literal_integer, .quantifier = .variadic } }, .OpSpecConstantDataKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .literal_integer, .quantifier = .variadic } }, - .OpPoisonKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result } }, - .OpFreezeKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, .OpTypeVectorIdEXT => &.{ .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .OpCooperativeMatrixConvertUseEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, .OpEmitMeshTasksEXT => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, .OpSetMeshOutputsEXT => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, .OpGroupNonUniformPartitionEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, - .OpHitObjectRecordFromQueryEXT => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .OpHitObjectRecordFromQueryEXT => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, .OpHitObjectRecordMissEXT => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, .OpHitObjectRecordMissMotionEXT => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, .OpHitObjectGetIntersectionTriangleVertexPositionsEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, @@ -2137,8 +2170,11 @@ pub const Opcode = enum(u16) { .OpHitObjectIsEmptyEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, .OpHitObjectIsHitEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, .OpHitObjectIsMissEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, + .OpCooperativeMatrixGetCoordinateEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, .OpBeginInvocationInterlockEXT => &.{}, .OpEndInvocationInterlockEXT => &.{}, + .OpCooperativeMatrixReduceEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .cooperative_matrix_reduce }, .{ .kind = .id_ref } }, + .OpCooperativeMatrixPerElementOpEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, .OpDemoteToHelperInvocation => &.{}, .OpIsHelperInvocationEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result } }, .OpAtomicFMinEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_scope }, .{ .kind = .id_memory_semantics }, .{ .kind = .id_ref } }, @@ -2165,6 +2201,8 @@ pub const Opcode = enum(u16) { .OpRayQueryGetIntersectionObjectToWorldKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, .OpRayQueryGetIntersectionWorldToObjectKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, .OpAtomicFAddEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref }, .{ .kind = .id_scope }, .{ .kind = .id_memory_semantics }, .{ .kind = .id_ref } }, + .OpControlBarrierArriveEXT => &.{ .{ .kind = .id_scope }, .{ .kind = .id_scope }, .{ .kind = .id_memory_semantics } }, + .OpControlBarrierWaitEXT => &.{ .{ .kind = .id_scope }, .{ .kind = .id_scope }, .{ .kind = .id_memory_semantics } }, .OpArithmeticFenceEXT => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_ref } }, .OpGroupIMulKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_scope }, .{ .kind = .group_operation }, .{ .kind = .id_ref } }, .OpGroupFMulKHR => &.{ .{ .kind = .id_result_type }, .{ .kind = .id_result }, .{ .kind = .id_scope }, .{ .kind = .group_operation }, .{ .kind = .id_ref } }, @@ -2526,6 +2564,7 @@ pub const Opcode = enum(u16) { .OpColorAttachmentReadEXT => struct { id_result_type: Id, id_result: Id, attachment: Id, sample: ?Id = null }, .OpDepthAttachmentReadEXT => struct { id_result_type: Id, id_result: Id, sample: ?Id = null }, .OpStencilAttachmentReadEXT => struct { id_result_type: Id, id_result: Id, sample: ?Id = null }, + .OpBitcastExtractEXT => struct { id_result_type: Id, id_result: Id, base: Id, offset: Id }, .OpTerminateInvocation => void, .OpTypeUntypedPointerKHR => struct { id_result: Id, storage_class: StorageClass }, .OpUntypedVariableKHR => struct { id_result_type: Id, id_result: Id, storage_class: StorageClass, data_type: ?Id = null, initializer: ?Id = null }, @@ -2582,13 +2621,12 @@ pub const Opcode = enum(u16) { .OpConstantSizeOfEXT => struct { id_result_type: Id, id_result: Id, type: Id }, .OpConstantDataKHR => struct { id_result_type: Id, id_result: Id, data: []const LiteralInteger = &.{} }, .OpSpecConstantDataKHR => struct { id_result_type: Id, id_result: Id, data: []const LiteralInteger = &.{} }, - .OpPoisonKHR => struct { id_result_type: Id, id_result: Id }, - .OpFreezeKHR => struct { id_result_type: Id, id_result: Id, value: Id }, .OpTypeVectorIdEXT => struct { id_result: Id, component_type: Id, component_count: Id }, + .OpCooperativeMatrixConvertUseEXT => struct { id_result_type: Id, id_result: Id, matrix: Id }, .OpEmitMeshTasksEXT => struct { group_count_x: Id, group_count_y: Id, group_count_z: Id, payload: ?Id = null }, .OpSetMeshOutputsEXT => struct { vertex_count: Id, primitive_count: Id }, .OpGroupNonUniformPartitionEXT => struct { id_result_type: Id, id_result: Id, value: Id }, - .OpHitObjectRecordFromQueryEXT => struct { hit_object: Id, ray_query: Id, sbt_record_index: Id, hit_object_attributes: Id }, + .OpHitObjectRecordFromQueryEXT => struct { hit_object: Id, ray_query: Id, sbt_record_index: Id, hit_object_attributes: Id, hit_kind: ?Id = null }, .OpHitObjectRecordMissEXT => struct { hit_object: Id, ray_flags: Id, miss_index: Id, ray_origin: Id, ray_tmin: Id, ray_direction: Id, ray_tmax: Id }, .OpHitObjectRecordMissMotionEXT => struct { hit_object: Id, ray_flags: Id, miss_index: Id, ray_origin: Id, ray_tmin: Id, ray_direction: Id, ray_tmax: Id, current_time: Id }, .OpHitObjectGetIntersectionTriangleVertexPositionsEXT => struct { id_result_type: Id, id_result: Id, hit_object: Id }, @@ -2627,8 +2665,11 @@ pub const Opcode = enum(u16) { .OpHitObjectIsEmptyEXT => struct { id_result_type: Id, id_result: Id, hit_object: Id }, .OpHitObjectIsHitEXT => struct { id_result_type: Id, id_result: Id, hit_object: Id }, .OpHitObjectIsMissEXT => struct { id_result_type: Id, id_result: Id, hit_object: Id }, + .OpCooperativeMatrixGetCoordinateEXT => struct { id_result_type: Id, id_result: Id, matrix: Id, index: Id }, .OpBeginInvocationInterlockEXT => void, .OpEndInvocationInterlockEXT => void, + .OpCooperativeMatrixReduceEXT => struct { id_result_type: Id, id_result: Id, matrix: Id, reduce: CooperativeMatrixReduce, combine_func: Id }, + .OpCooperativeMatrixPerElementOpEXT => struct { id_result_type: Id, id_result: Id, matrix: Id, func: Id, operands: []const Id = &.{} }, .OpDemoteToHelperInvocation => void, .OpIsHelperInvocationEXT => struct { id_result_type: Id, id_result: Id }, .OpAtomicFMinEXT => struct { id_result_type: Id, id_result: Id, pointer: Id, memory: Id, semantics: Id, value: Id }, @@ -2655,6 +2696,8 @@ pub const Opcode = enum(u16) { .OpRayQueryGetIntersectionObjectToWorldKHR => struct { id_result_type: Id, id_result: Id, ray_query: Id, intersection: Id }, .OpRayQueryGetIntersectionWorldToObjectKHR => struct { id_result_type: Id, id_result: Id, ray_query: Id, intersection: Id }, .OpAtomicFAddEXT => struct { id_result_type: Id, id_result: Id, pointer: Id, memory: Id, semantics: Id, value: Id }, + .OpControlBarrierArriveEXT => struct { execution: Id, memory: Id, semantics: Id }, + .OpControlBarrierWaitEXT => struct { execution: Id, memory: Id, semantics: Id }, .OpArithmeticFenceEXT => struct { id_result_type: Id, id_result: Id, target: Id }, .OpGroupIMulKHR => struct { id_result_type: Id, id_result: Id, execution: Id, operation: GroupOperation, x: Id }, .OpGroupFMulKHR => struct { id_result_type: Id, id_result: Id, execution: Id, operation: GroupOperation, x: Id }, @@ -2709,6 +2752,7 @@ pub const Opcode = enum(u16) { 400 => .composite, 401...403 => .memory, 4160...4162 => .image, + 4195 => .conversion, 4416 => .control_flow, 4417 => .type_declaration, 4418...4420 => .memory, @@ -2735,15 +2779,18 @@ pub const Opcode = enum(u16) { 5126 => .memory, 5127 => .annotation, 5129...5148 => .constant_creation, - 5158...5159 => .miscellaneous, 5288 => .type_declaration, + 5293 => .conversion, 5294...5295 => .reserved, 5296 => .non_uniform, 5304...5312 => .reserved, 5313 => .type_declaration, 5314...5340 => .reserved, 5341 => .type_declaration, - 5347...5365 => .reserved, + 5347...5352 => .reserved, + 5363 => .miscellaneous, + 5364...5365 => .reserved, + 5366...5369 => .function, 5380 => .control_flow, 5381 => .reserved, 5614...5615 => .atomic, @@ -2751,6 +2798,7 @@ pub const Opcode = enum(u16) { 5632...5633 => .annotation, 6016...6032 => .reserved, 6035 => .atomic, + 6142...6143 => .barrier, 6145 => .miscellaneous, 6401...6408 => .group, else => unreachable, @@ -3162,6 +3210,102 @@ pub const OpenClOpcode = enum(u16) { } }; +pub const ShaderDebugInfoOpCode = enum(u16) { + DebugInfoNone = 0, + DebugCompilationUnit = 1, + DebugTypeBasic = 2, + DebugTypePointer = 3, + DebugTypeQualifier = 4, + DebugTypeArray = 5, + DebugTypeVector = 6, + DebugTypedef = 7, + DebugTypeFunction = 8, + DebugTypeEnum = 9, + DebugTypeComposite = 10, + DebugTypeMember = 11, + DebugTypeInheritance = 12, + DebugTypePtrToMember = 13, + DebugTypeTemplate = 14, + DebugTypeTemplateParameter = 15, + DebugTypeTemplateTemplateParameter = 16, + DebugTypeTemplateParameterPack = 17, + DebugGlobalVariable = 18, + DebugFunctionDeclaration = 19, + DebugFunction = 20, + DebugLexicalBlock = 21, + DebugLexicalBlockDiscriminator = 22, + DebugScope = 23, + DebugNoScope = 24, + DebugInlinedAt = 25, + DebugLocalVariable = 26, + DebugInlinedVariable = 27, + DebugDeclare = 28, + DebugValue = 29, + DebugOperation = 30, + DebugExpression = 31, + DebugMacroDef = 32, + DebugMacroUndef = 33, + DebugImportedEntity = 34, + DebugSource = 35, + DebugFunctionDefinition = 101, + DebugSourceContinued = 102, + DebugLine = 103, + DebugNoLine = 104, + DebugBuildIdentifier = 105, + DebugStoragePath = 106, + DebugEntryPoint = 107, + DebugTypeMatrix = 108, + + pub fn operands(opcode: ShaderDebugInfoOpCode) []const Operand { + return switch (opcode) { + .DebugInfoNone => &.{}, + .DebugCompilationUnit => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypeBasic => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypePointer => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypeQualifier => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypeArray => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, + .DebugTypeVector => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypedef => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypeFunction => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, + .DebugTypeEnum => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .pair_id_ref_id_ref, .quantifier = .variadic } }, + .DebugTypeComposite => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, + .DebugTypeMember => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugTypeInheritance => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypePtrToMember => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypeTemplate => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, + .DebugTypeTemplateParameter => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypeTemplateTemplateParameter => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypeTemplateParameterPack => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, + .DebugGlobalVariable => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugFunctionDeclaration => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugFunction => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugLexicalBlock => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugLexicalBlockDiscriminator => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugScope => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugNoScope => &.{}, + .DebugInlinedAt => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugLocalVariable => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugInlinedVariable => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugDeclare => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, + .DebugValue => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, + .DebugOperation => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, + .DebugExpression => &.{.{ .kind = .id_ref, .quantifier = .variadic }}, + .DebugMacroDef => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugMacroUndef => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugImportedEntity => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugSource => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, + .DebugFunctionDefinition => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugSourceContinued => &.{.{ .kind = .id_ref }}, + .DebugLine => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugNoLine => &.{}, + .DebugBuildIdentifier => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugStoragePath => &.{.{ .kind = .id_ref }}, + .DebugEntryPoint => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + .DebugTypeMatrix => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, + }; + } +}; + pub const GlslOpcode = enum(u16) { Round = 1, RoundEven = 2, @@ -3331,102 +3475,6 @@ pub const GlslOpcode = enum(u16) { }; } }; - -pub const ShaderDebugInfoOpCode = enum(u16) { - DebugInfoNone = 0, - DebugCompilationUnit = 1, - DebugTypeBasic = 2, - DebugTypePointer = 3, - DebugTypeQualifier = 4, - DebugTypeArray = 5, - DebugTypeVector = 6, - DebugTypedef = 7, - DebugTypeFunction = 8, - DebugTypeEnum = 9, - DebugTypeComposite = 10, - DebugTypeMember = 11, - DebugTypeInheritance = 12, - DebugTypePtrToMember = 13, - DebugTypeTemplate = 14, - DebugTypeTemplateParameter = 15, - DebugTypeTemplateTemplateParameter = 16, - DebugTypeTemplateParameterPack = 17, - DebugGlobalVariable = 18, - DebugFunctionDeclaration = 19, - DebugFunction = 20, - DebugLexicalBlock = 21, - DebugLexicalBlockDiscriminator = 22, - DebugScope = 23, - DebugNoScope = 24, - DebugInlinedAt = 25, - DebugLocalVariable = 26, - DebugInlinedVariable = 27, - DebugDeclare = 28, - DebugValue = 29, - DebugOperation = 30, - DebugExpression = 31, - DebugMacroDef = 32, - DebugMacroUndef = 33, - DebugImportedEntity = 34, - DebugSource = 35, - DebugFunctionDefinition = 101, - DebugSourceContinued = 102, - DebugLine = 103, - DebugNoLine = 104, - DebugBuildIdentifier = 105, - DebugStoragePath = 106, - DebugEntryPoint = 107, - DebugTypeMatrix = 108, - - pub fn operands(opcode: ShaderDebugInfoOpCode) []const Operand { - return switch (opcode) { - .DebugInfoNone => &.{}, - .DebugCompilationUnit => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypeBasic => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypePointer => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypeQualifier => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypeArray => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, - .DebugTypeVector => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypedef => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypeFunction => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, - .DebugTypeEnum => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .pair_id_ref_id_ref, .quantifier = .variadic } }, - .DebugTypeComposite => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, - .DebugTypeMember => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugTypeInheritance => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypePtrToMember => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypeTemplate => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, - .DebugTypeTemplateParameter => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypeTemplateTemplateParameter => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypeTemplateParameterPack => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, - .DebugGlobalVariable => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugFunctionDeclaration => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugFunction => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugLexicalBlock => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugLexicalBlockDiscriminator => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugScope => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugNoScope => &.{}, - .DebugInlinedAt => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugLocalVariable => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugInlinedVariable => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugDeclare => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, - .DebugValue => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, - .DebugOperation => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .variadic } }, - .DebugExpression => &.{.{ .kind = .id_ref, .quantifier = .variadic }}, - .DebugMacroDef => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugMacroUndef => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugImportedEntity => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugSource => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref, .quantifier = .optional } }, - .DebugFunctionDefinition => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugSourceContinued => &.{.{ .kind = .id_ref }}, - .DebugLine => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugNoLine => &.{}, - .DebugBuildIdentifier => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugStoragePath => &.{.{ .kind = .id_ref }}, - .DebugEntryPoint => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - .DebugTypeMatrix => &.{ .{ .kind = .id_ref }, .{ .kind = .id_ref }, .{ .kind = .id_ref } }, - }; - } -}; pub const ImageOperands = packed struct(Word) { bias: bool = false, lod: bool = false, @@ -3495,7 +3543,9 @@ pub const LoopControl = packed struct(Word) { iteration_multiple: bool = false, peel_count: bool = false, partial_count: bool = false, - _reserved_bits_9_to_31: u23 = 0, + _reserved_bits_9_to_27: u19 = 0, + multiple_wait_queues_qcom: bool = false, + _reserved_bits_29_to_31: u3 = 0, pub const Extended = struct { unroll: bool = false, @@ -3507,7 +3557,9 @@ pub const LoopControl = packed struct(Word) { iteration_multiple: ?struct { literal_integer: LiteralInteger } = null, peel_count: ?struct { literal_integer: LiteralInteger } = null, partial_count: ?struct { literal_integer: LiteralInteger } = null, - _reserved_bits_9_to_31: u23 = 0, + _reserved_bits_9_to_27: u19 = 0, + multiple_wait_queues_qcom: ?struct { literal_integer: LiteralInteger } = null, + _reserved_bits_29_to_31: u3 = 0, }; }; pub const FunctionControl = packed struct(Word) { @@ -3572,7 +3624,7 @@ pub const RayFlags = packed struct(Word) { cull_no_opaque_khr: bool = false, skip_triangles_khr: bool = false, skip_aab_bs_khr: bool = false, - force_opacity_micromap2state_ext: bool = false, + force_opacity_micromap2state_khr: bool = false, _reserved_bits_11_to_31: u21 = 0, }; pub const FragmentShadingRate = packed struct(Word) { @@ -3600,6 +3652,8 @@ pub const SourceLanguage = enum(u32) { slang = 11, zig = 12, rust = 13, + pred = 14, + apila_jai = 15, }; pub const ExecutionModel = enum(u32) { vertex = 0, @@ -3688,7 +3742,6 @@ pub const ExecutionMode = enum(u32) { stencil_ref_less_back_amd = 5084, quad_derivatives_khr = 5088, require_full_quads_khr = 5089, - arithmetic_poison_khr = 5157, output_lines_ext = 5269, output_primitives_ext = 5270, derivative_group_quads_khr = 5289, @@ -3703,6 +3756,7 @@ pub const ExecutionMode = enum(u32) { shader64bit_indexing_ext = 5427, maximally_reconverges_khr = 6023, fp_fast_math_default = 6028, + opacity_micromap_id_khr = 6031, pub const Extended = union(ExecutionMode) { invocations: struct { literal_integer: LiteralInteger }, @@ -3762,7 +3816,6 @@ pub const ExecutionMode = enum(u32) { stencil_ref_less_back_amd, quad_derivatives_khr, require_full_quads_khr, - arithmetic_poison_khr, output_lines_ext, output_primitives_ext: struct { primitive_count: LiteralInteger }, derivative_group_quads_khr, @@ -3777,6 +3830,7 @@ pub const ExecutionMode = enum(u32) { shader64bit_indexing_ext, maximally_reconverges_khr, fp_fast_math_default: struct { target_type: Id, id_ref_1: Id }, + opacity_micromap_id_khr: struct { enable: Id }, }; }; pub const StorageClass = enum(u32) { @@ -4011,6 +4065,7 @@ pub const Decoration = enum(u32) { restrict_pointer = 5355, aliased_pointer = 5356, hit_object_shader_record_buffer_ext = 5389, + cooperative_matrix_transpose_ext = 5440, counter_buffer = 5634, user_semantic = 5635, @@ -4074,6 +4129,7 @@ pub const Decoration = enum(u32) { restrict_pointer, aliased_pointer, hit_object_shader_record_buffer_ext, + cooperative_matrix_transpose_ext, counter_buffer: struct { counter_buffer: Id }, user_semantic: struct { semantic: LiteralString }, }; @@ -4231,6 +4287,8 @@ pub const Capability = enum(u32) { input_attachment = 40, sparse_residency = 41, min_lod = 42, + sampled1d = 43, + image1d = 44, sampled_cube_array = 45, sampled_buffer = 46, image_buffer = 47, @@ -4263,6 +4321,11 @@ pub const Capability = enum(u32) { tile_image_stencil_read_access_ext = 4168, float8ext = 4212, float8cooperative_matrix_ext = 4213, + float6ext = 4228, + float4ext = 4229, + float8unsigned_e8m0ext = 4230, + mx_int8ext = 4231, + bitcast_extract_ext = 4232, fragment_shading_rate_khr = 4422, subgroup_ballot_khr = 4423, draw_parameters = 4427, @@ -4286,7 +4349,8 @@ pub const Capability = enum(u32) { denorm_preserve = 4464, denorm_flush_to_zero = 4465, signed_zero_inf_nan_preserve = 4466, - ray_query_provisional_khr = 4471, + rounding_mode_rte = 4467, + rounding_mode_rtz = 4468, ray_query_khr = 4472, untyped_pointers_khr = 4473, ray_traversal_primitive_culling_khr = 4478, @@ -4301,7 +4365,6 @@ pub const Capability = enum(u32) { abort_khr = 5120, descriptor_heap_ext = 5128, constant_data_khr = 5146, - poison_freeze_khr = 5156, shader_viewport_index_layer_ext = 5254, fragment_fully_covered_ext = 5265, mesh_shading_ext = 5283, @@ -4326,16 +4389,19 @@ pub const Capability = enum(u32) { vulkan_memory_model_device_scope = 5346, physical_storage_buffer_addresses = 5347, compute_derivative_group_linear_khr = 5350, - ray_tracing_provisional_khr = 5353, fragment_shader_sample_interlock_ext = 5363, fragment_shader_shading_rate_interlock_ext = 5372, fragment_shader_pixel_interlock_ext = 5378, demote_to_helper_invocation = 5379, - ray_tracing_opacity_micromap_ext = 5381, + ray_tracing_opacity_micromap_khr = 5381, shader_invocation_reorder_ext = 5388, ray_query_position_fetch_khr = 5391, long_vector_ext = 5425, shader64bit_indexing_ext = 5426, + cooperative_matrix_conversions_ext = 5429, + cooperative_matrix_reductions_ext = 5430, + cooperative_matrix_per_element_operations_ext = 5432, + cooperative_matrix_get_coordinate_ext = 5438, atomic_float32min_max_ext = 5612, atomic_float64min_max_ext = 5613, atomic_float16min_max_ext = 5616, @@ -4351,69 +4417,73 @@ pub const Capability = enum(u32) { group_non_uniform_rotate_khr = 6026, float_controls2 = 6029, fmakhr = 6030, + ray_tracing_opacity_micromap_execution_mode_khr = 6032, atomic_float32add_ext = 6033, atomic_float64add_ext = 6034, opt_none_ext = 6094, atomic_float16add_ext = 6095, + split_barrier_ext = 6141, arithmetic_fence_ext = 6144, group_uniform_arithmetic_khr = 6400, - pub fn dependencies(self: Capability) []const Extension { + pub fn dependencyExtensions(self: Capability) []const Extension { return switch (self) { - .matrix => &.{.v1_0}, - .shader => &.{.v1_0}, - .geometry => &.{.v1_0}, - .tessellation => &.{.v1_0}, - .addresses => &.{.v1_0}, - .linkage => &.{.v1_0}, - .kernel => &.{.v1_0}, - .vector16 => &.{.v1_0}, - .float16buffer => &.{.v1_0}, - .float16 => &.{.v1_0}, - .float64 => &.{.v1_0}, - .int64 => &.{.v1_0}, - .int64atomics => &.{.v1_0}, - .image_basic => &.{.v1_0}, - .image_read_write => &.{.v1_0}, - .image_mipmap => &.{.v1_0}, - .pipes => &.{.v1_0}, - .groups => &.{.v1_0}, - .device_enqueue => &.{.v1_0}, - .literal_sampler => &.{.v1_0}, - .atomic_storage => &.{.v1_0}, - .int16 => &.{.v1_0}, - .tessellation_point_size => &.{.v1_0}, - .geometry_point_size => &.{.v1_0}, - .image_gather_extended => &.{.v1_0}, - .storage_image_multisample => &.{.v1_0}, - .uniform_buffer_array_dynamic_indexing => &.{.v1_0}, - .sampled_image_array_dynamic_indexing => &.{.v1_0}, - .storage_buffer_array_dynamic_indexing => &.{.v1_0}, - .storage_image_array_dynamic_indexing => &.{.v1_0}, - .clip_distance => &.{.v1_0}, - .cull_distance => &.{.v1_0}, - .image_cube_array => &.{.v1_0}, - .sample_rate_shading => &.{.v1_0}, - .image_rect => &.{.v1_0}, - .sampled_rect => &.{.v1_0}, - .generic_pointer => &.{.v1_0}, - .int8 => &.{.v1_0}, - .input_attachment => &.{.v1_0}, - .sparse_residency => &.{.v1_0}, - .min_lod => &.{.v1_0}, - .sampled_cube_array => &.{.v1_0}, - .sampled_buffer => &.{.v1_0}, - .image_buffer => &.{.v1_0}, - .image_ms_array => &.{.v1_0}, - .storage_image_extended_formats => &.{.v1_0}, - .image_query => &.{.v1_0}, - .derivative_control => &.{.v1_0}, - .interpolation_function => &.{.v1_0}, - .transform_feedback => &.{.v1_0}, - .geometry_streams => &.{.v1_0}, - .storage_image_read_without_format => &.{.v1_0}, - .storage_image_write_without_format => &.{.v1_0}, - .multi_viewport => &.{.v1_0}, + .matrix => &.{}, + .shader => &.{}, + .geometry => &.{}, + .tessellation => &.{}, + .addresses => &.{}, + .linkage => &.{}, + .kernel => &.{}, + .vector16 => &.{}, + .float16buffer => &.{}, + .float16 => &.{}, + .float64 => &.{}, + .int64 => &.{}, + .int64atomics => &.{}, + .image_basic => &.{}, + .image_read_write => &.{}, + .image_mipmap => &.{}, + .pipes => &.{}, + .groups => &.{}, + .device_enqueue => &.{}, + .literal_sampler => &.{}, + .atomic_storage => &.{}, + .int16 => &.{}, + .tessellation_point_size => &.{}, + .geometry_point_size => &.{}, + .image_gather_extended => &.{}, + .storage_image_multisample => &.{}, + .uniform_buffer_array_dynamic_indexing => &.{}, + .sampled_image_array_dynamic_indexing => &.{}, + .storage_buffer_array_dynamic_indexing => &.{}, + .storage_image_array_dynamic_indexing => &.{}, + .clip_distance => &.{}, + .cull_distance => &.{}, + .image_cube_array => &.{}, + .sample_rate_shading => &.{}, + .image_rect => &.{}, + .sampled_rect => &.{}, + .generic_pointer => &.{}, + .int8 => &.{}, + .input_attachment => &.{}, + .sparse_residency => &.{}, + .min_lod => &.{}, + .sampled1d => &.{}, + .image1d => &.{}, + .sampled_cube_array => &.{}, + .sampled_buffer => &.{}, + .image_buffer => &.{}, + .image_ms_array => &.{}, + .storage_image_extended_formats => &.{}, + .image_query => &.{}, + .derivative_control => &.{}, + .interpolation_function => &.{}, + .transform_feedback => &.{}, + .geometry_streams => &.{}, + .storage_image_read_without_format => &.{}, + .storage_image_write_without_format => &.{}, + .multi_viewport => &.{}, .subgroup_dispatch => &.{.v1_1}, .named_barrier => &.{.v1_1}, .pipe_storage => &.{.v1_1}, @@ -4428,18 +4498,23 @@ pub const Capability = enum(u32) { .shader_layer => &.{.v1_5}, .shader_viewport_index => &.{.v1_5}, .uniform_decoration => &.{.v1_6}, - .tile_image_color_read_access_ext => &.{ .v1_0, .SPV_EXT_shader_tile_image }, - .tile_image_depth_read_access_ext => &.{ .v1_0, .SPV_EXT_shader_tile_image }, - .tile_image_stencil_read_access_ext => &.{ .v1_0, .SPV_EXT_shader_tile_image }, - .float8ext => &.{ .v1_0, .SPV_EXT_float8 }, - .float8cooperative_matrix_ext => &.{ .v1_0, .SPV_EXT_float8 }, - .fragment_shading_rate_khr => &.{ .v1_0, .SPV_KHR_fragment_shading_rate }, - .subgroup_ballot_khr => &.{ .v1_0, .SPV_KHR_shader_ballot }, + .tile_image_color_read_access_ext => &.{.SPV_EXT_shader_tile_image}, + .tile_image_depth_read_access_ext => &.{.SPV_EXT_shader_tile_image}, + .tile_image_stencil_read_access_ext => &.{.SPV_EXT_shader_tile_image}, + .float8ext => &.{.SPV_EXT_float8}, + .float8cooperative_matrix_ext => &.{.SPV_EXT_float8}, + .float6ext => &.{.SPV_EXT_ocp_microscaling_types}, + .float4ext => &.{.SPV_EXT_ocp_microscaling_types}, + .float8unsigned_e8m0ext => &.{.SPV_EXT_ocp_microscaling_types}, + .mx_int8ext => &.{.SPV_EXT_ocp_microscaling_types}, + .bitcast_extract_ext => &.{.SPV_EXT_ocp_microscaling_types}, + .fragment_shading_rate_khr => &.{.SPV_KHR_fragment_shading_rate}, + .subgroup_ballot_khr => &.{.SPV_KHR_shader_ballot}, .draw_parameters => &.{ .v1_3, .SPV_KHR_shader_draw_parameters }, - .workgroup_memory_explicit_layout_khr => &.{ .v1_0, .SPV_KHR_workgroup_memory_explicit_layout }, - .workgroup_memory_explicit_layout8bit_access_khr => &.{ .v1_0, .SPV_KHR_workgroup_memory_explicit_layout }, - .workgroup_memory_explicit_layout16bit_access_khr => &.{ .v1_0, .SPV_KHR_workgroup_memory_explicit_layout }, - .subgroup_vote_khr => &.{ .v1_0, .SPV_KHR_subgroup_vote }, + .workgroup_memory_explicit_layout_khr => &.{.SPV_KHR_workgroup_memory_explicit_layout}, + .workgroup_memory_explicit_layout8bit_access_khr => &.{.SPV_KHR_workgroup_memory_explicit_layout}, + .workgroup_memory_explicit_layout16bit_access_khr => &.{.SPV_KHR_workgroup_memory_explicit_layout}, + .subgroup_vote_khr => &.{.SPV_KHR_subgroup_vote}, .storage_buffer16bit_access => &.{ .v1_3, .SPV_KHR_16bit_storage }, .uniform_and_storage_buffer16bit_access => &.{ .v1_3, .SPV_KHR_16bit_storage }, .storage_push_constant16 => &.{ .v1_3, .SPV_KHR_16bit_storage }, @@ -4448,37 +4523,37 @@ pub const Capability = enum(u32) { .multi_view => &.{ .v1_3, .SPV_KHR_multiview }, .variable_pointers_storage_buffer => &.{ .v1_3, .SPV_KHR_variable_pointers }, .variable_pointers => &.{ .v1_3, .SPV_KHR_variable_pointers }, - .atomic_storage_ops => &.{ .v1_0, .SPV_KHR_shader_atomic_counter_ops }, - .sample_mask_post_depth_coverage => &.{ .v1_0, .SPV_KHR_post_depth_coverage }, + .atomic_storage_ops => &.{.SPV_KHR_shader_atomic_counter_ops}, + .sample_mask_post_depth_coverage => &.{.SPV_KHR_post_depth_coverage}, .storage_buffer8bit_access => &.{ .v1_5, .SPV_KHR_8bit_storage }, .uniform_and_storage_buffer8bit_access => &.{ .v1_5, .SPV_KHR_8bit_storage }, .storage_push_constant8 => &.{ .v1_5, .SPV_KHR_8bit_storage }, .denorm_preserve => &.{ .v1_4, .SPV_KHR_float_controls }, .denorm_flush_to_zero => &.{ .v1_4, .SPV_KHR_float_controls }, .signed_zero_inf_nan_preserve => &.{ .v1_4, .SPV_KHR_float_controls }, - .ray_query_provisional_khr => &.{ .v1_0, .SPV_KHR_ray_query }, - .ray_query_khr => &.{ .v1_0, .SPV_KHR_ray_query }, - .untyped_pointers_khr => &.{ .v1_0, .SPV_KHR_untyped_pointers }, - .ray_traversal_primitive_culling_khr => &.{ .v1_0, .SPV_KHR_ray_query, .SPV_KHR_ray_tracing }, - .ray_tracing_khr => &.{ .v1_0, .SPV_KHR_ray_tracing }, - .stencil_export_ext => &.{ .v1_0, .SPV_EXT_shader_stencil_export }, - .int64image_ext => &.{ .v1_0, .SPV_EXT_shader_image_int64 }, - .shader_clock_khr => &.{ .v1_0, .SPV_KHR_shader_clock }, - .quad_control_khr => &.{ .v1_0, .SPV_KHR_quad_control }, - .b_float16type_khr => &.{ .v1_0, .SPV_KHR_bfloat16 }, - .b_float16dot_product_khr => &.{ .v1_0, .SPV_KHR_bfloat16 }, - .b_float16cooperative_matrix_khr => &.{ .v1_0, .SPV_KHR_bfloat16 }, - .abort_khr => &.{ .v1_0, .SPV_KHR_abort }, - .descriptor_heap_ext => &.{ .v1_0, .SPV_EXT_descriptor_heap }, - .constant_data_khr => &.{ .v1_0, .SPV_KHR_constant_data }, - .poison_freeze_khr => &.{ .v1_0, .SPV_KHR_poison_freeze }, - .shader_viewport_index_layer_ext => &.{ .v1_0, .SPV_EXT_shader_viewport_index_layer }, - .fragment_fully_covered_ext => &.{ .v1_0, .SPV_EXT_fragment_fully_covered }, - .mesh_shading_ext => &.{ .v1_0, .SPV_EXT_mesh_shader }, - .fragment_barycentric_khr => &.{ .v1_0, .SPV_KHR_fragment_shader_barycentric }, - .compute_derivative_group_quads_khr => &.{ .v1_0, .SPV_KHR_compute_shader_derivatives }, - .fragment_density_ext => &.{ .v1_0, .SPV_EXT_fragment_invocation_density }, - .group_non_uniform_partitioned_ext => &.{ .v1_0, .SPV_EXT_shader_subgroup_partitioned }, + .rounding_mode_rte => &.{ .v1_4, .SPV_KHR_float_controls }, + .rounding_mode_rtz => &.{ .v1_4, .SPV_KHR_float_controls }, + .ray_query_khr => &.{.SPV_KHR_ray_query}, + .untyped_pointers_khr => &.{.SPV_KHR_untyped_pointers}, + .ray_traversal_primitive_culling_khr => &.{ .SPV_KHR_ray_query, .SPV_KHR_ray_tracing }, + .ray_tracing_khr => &.{.SPV_KHR_ray_tracing}, + .stencil_export_ext => &.{.SPV_EXT_shader_stencil_export}, + .int64image_ext => &.{.SPV_EXT_shader_image_int64}, + .shader_clock_khr => &.{.SPV_KHR_shader_clock}, + .quad_control_khr => &.{.SPV_KHR_quad_control}, + .b_float16type_khr => &.{.SPV_KHR_bfloat16}, + .b_float16dot_product_khr => &.{.SPV_KHR_bfloat16}, + .b_float16cooperative_matrix_khr => &.{.SPV_KHR_bfloat16}, + .abort_khr => &.{.SPV_KHR_abort}, + .descriptor_heap_ext => &.{.SPV_EXT_descriptor_heap}, + .constant_data_khr => &.{.SPV_KHR_constant_data}, + .shader_viewport_index_layer_ext => &.{.SPV_EXT_shader_viewport_index_layer}, + .fragment_fully_covered_ext => &.{.SPV_EXT_fragment_fully_covered}, + .mesh_shading_ext => &.{.SPV_EXT_mesh_shader}, + .fragment_barycentric_khr => &.{.SPV_KHR_fragment_shader_barycentric}, + .compute_derivative_group_quads_khr => &.{.SPV_KHR_compute_shader_derivatives}, + .fragment_density_ext => &.{.SPV_EXT_fragment_invocation_density}, + .group_non_uniform_partitioned_ext => &.{.SPV_EXT_shader_subgroup_partitioned}, .shader_non_uniform => &.{ .v1_5, .SPV_EXT_descriptor_indexing }, .runtime_descriptor_array => &.{ .v1_5, .SPV_EXT_descriptor_indexing }, .input_attachment_array_dynamic_indexing => &.{ .v1_5, .SPV_EXT_descriptor_indexing }, @@ -4491,42 +4566,231 @@ pub const Capability = enum(u32) { .input_attachment_array_non_uniform_indexing => &.{ .v1_5, .SPV_EXT_descriptor_indexing }, .uniform_texel_buffer_array_non_uniform_indexing => &.{ .v1_5, .SPV_EXT_descriptor_indexing }, .storage_texel_buffer_array_non_uniform_indexing => &.{ .v1_5, .SPV_EXT_descriptor_indexing }, - .ray_tracing_position_fetch_khr => &.{ .v1_0, .SPV_KHR_ray_tracing_position_fetch }, + .ray_tracing_position_fetch_khr => &.{.SPV_KHR_ray_tracing_position_fetch}, .vulkan_memory_model => &.{ .v1_5, .SPV_KHR_vulkan_memory_model }, .vulkan_memory_model_device_scope => &.{ .v1_5, .SPV_KHR_vulkan_memory_model }, .physical_storage_buffer_addresses => &.{ .v1_5, .SPV_EXT_physical_storage_buffer, .SPV_KHR_physical_storage_buffer }, - .compute_derivative_group_linear_khr => &.{ .v1_0, .SPV_KHR_compute_shader_derivatives }, - .ray_tracing_provisional_khr => &.{ .v1_0, .SPV_KHR_ray_tracing }, - .fragment_shader_sample_interlock_ext => &.{ .v1_0, .SPV_EXT_fragment_shader_interlock }, - .fragment_shader_shading_rate_interlock_ext => &.{ .v1_0, .SPV_EXT_fragment_shader_interlock }, - .fragment_shader_pixel_interlock_ext => &.{ .v1_0, .SPV_EXT_fragment_shader_interlock }, + .compute_derivative_group_linear_khr => &.{.SPV_KHR_compute_shader_derivatives}, + .fragment_shader_sample_interlock_ext => &.{.SPV_EXT_fragment_shader_interlock}, + .fragment_shader_shading_rate_interlock_ext => &.{.SPV_EXT_fragment_shader_interlock}, + .fragment_shader_pixel_interlock_ext => &.{.SPV_EXT_fragment_shader_interlock}, .demote_to_helper_invocation => &.{ .v1_6, .SPV_EXT_demote_to_helper_invocation }, - .ray_tracing_opacity_micromap_ext => &.{ .v1_0, .SPV_EXT_opacity_micromap }, - .shader_invocation_reorder_ext => &.{ .v1_0, .SPV_EXT_shader_invocation_reorder }, - .ray_query_position_fetch_khr => &.{ .v1_0, .SPV_KHR_ray_tracing_position_fetch }, - .long_vector_ext => &.{ .v1_0, .SPV_EXT_long_vector }, - .shader64bit_indexing_ext => &.{ .v1_0, .SPV_EXT_shader_64bit_indexing }, - .atomic_float32min_max_ext => &.{ .v1_0, .SPV_EXT_shader_atomic_float_min_max }, - .atomic_float64min_max_ext => &.{ .v1_0, .SPV_EXT_shader_atomic_float_min_max }, - .atomic_float16min_max_ext => &.{ .v1_0, .SPV_EXT_shader_atomic_float_min_max }, - .expect_assume_khr => &.{ .v1_0, .SPV_KHR_expect_assume }, + .ray_tracing_opacity_micromap_khr => &.{ .SPV_KHR_opacity_micromap, .SPV_EXT_opacity_micromap }, + .shader_invocation_reorder_ext => &.{.SPV_EXT_shader_invocation_reorder}, + .ray_query_position_fetch_khr => &.{.SPV_KHR_ray_tracing_position_fetch}, + .long_vector_ext => &.{.SPV_EXT_long_vector}, + .shader64bit_indexing_ext => &.{.SPV_EXT_shader_64bit_indexing}, + .cooperative_matrix_conversions_ext => &.{.SPV_EXT_cooperative_matrix_maintenance1}, + .cooperative_matrix_reductions_ext => &.{.SPV_EXT_cooperative_matrix_maintenance1}, + .cooperative_matrix_per_element_operations_ext => &.{.SPV_EXT_cooperative_matrix_maintenance1}, + .cooperative_matrix_get_coordinate_ext => &.{.SPV_EXT_cooperative_matrix_maintenance1}, + .atomic_float32min_max_ext => &.{.SPV_EXT_shader_atomic_float_min_max}, + .atomic_float64min_max_ext => &.{.SPV_EXT_shader_atomic_float_min_max}, + .atomic_float16min_max_ext => &.{.SPV_EXT_shader_atomic_float_min_max}, + .expect_assume_khr => &.{.SPV_KHR_expect_assume}, .dot_product_input_all => &.{ .v1_6, .SPV_KHR_integer_dot_product }, .dot_product_input4x8bit => &.{ .v1_6, .SPV_KHR_integer_dot_product }, .dot_product_input4x8bit_packed => &.{ .v1_6, .SPV_KHR_integer_dot_product }, .dot_product => &.{ .v1_6, .SPV_KHR_integer_dot_product }, - .ray_cull_mask_khr => &.{ .v1_0, .SPV_KHR_ray_cull_mask }, - .cooperative_matrix_khr => &.{ .v1_0, .SPV_KHR_cooperative_matrix }, - .replicated_composites_ext => &.{ .v1_0, .SPV_EXT_replicated_composites }, - .bit_instructions => &.{ .v1_0, .SPV_KHR_bit_instructions }, - .group_non_uniform_rotate_khr => &.{ .v1_0, .SPV_KHR_subgroup_rotate }, - .float_controls2 => &.{ .v1_0, .SPV_KHR_float_controls2 }, - .fmakhr => &.{ .v1_0, .SPV_KHR_fma }, - .atomic_float32add_ext => &.{ .v1_0, .SPV_EXT_shader_atomic_float_add }, - .atomic_float64add_ext => &.{ .v1_0, .SPV_EXT_shader_atomic_float_add }, - .opt_none_ext => &.{ .v1_0, .SPV_EXT_optnone }, - .atomic_float16add_ext => &.{ .v1_0, .SPV_EXT_shader_atomic_float16_add }, - .arithmetic_fence_ext => &.{ .v1_0, .SPV_EXT_arithmetic_fence }, - .group_uniform_arithmetic_khr => &.{ .v1_0, .SPV_KHR_uniform_group_instructions }, + .ray_cull_mask_khr => &.{.SPV_KHR_ray_cull_mask}, + .cooperative_matrix_khr => &.{.SPV_KHR_cooperative_matrix}, + .replicated_composites_ext => &.{.SPV_EXT_replicated_composites}, + .bit_instructions => &.{.SPV_KHR_bit_instructions}, + .group_non_uniform_rotate_khr => &.{.SPV_KHR_subgroup_rotate}, + .float_controls2 => &.{.SPV_KHR_float_controls2}, + .fmakhr => &.{.SPV_KHR_fma}, + .ray_tracing_opacity_micromap_execution_mode_khr => &.{.SPV_KHR_opacity_micromap}, + .atomic_float32add_ext => &.{.SPV_EXT_shader_atomic_float_add}, + .atomic_float64add_ext => &.{.SPV_EXT_shader_atomic_float_add}, + .opt_none_ext => &.{.SPV_EXT_optnone}, + .atomic_float16add_ext => &.{.SPV_EXT_shader_atomic_float16_add}, + .split_barrier_ext => &.{.SPV_EXT_split_barrier}, + .arithmetic_fence_ext => &.{.SPV_EXT_arithmetic_fence}, + .group_uniform_arithmetic_khr => &.{.SPV_KHR_uniform_group_instructions}, + }; + } + + pub fn dependencyCapabilities(self: Capability) []const Capability { + return switch (self) { + .matrix => &.{}, + .shader => &.{.matrix}, + .geometry => &.{.shader}, + .tessellation => &.{.shader}, + .addresses => &.{}, + .linkage => &.{}, + .kernel => &.{}, + .vector16 => &.{.kernel}, + .float16buffer => &.{.kernel}, + .float16 => &.{}, + .float64 => &.{}, + .int64 => &.{}, + .int64atomics => &.{.int64}, + .image_basic => &.{.kernel}, + .image_read_write => &.{.image_basic}, + .image_mipmap => &.{.image_basic}, + .pipes => &.{.kernel}, + .groups => &.{}, + .device_enqueue => &.{.kernel}, + .literal_sampler => &.{.kernel}, + .atomic_storage => &.{.shader}, + .int16 => &.{}, + .tessellation_point_size => &.{.tessellation}, + .geometry_point_size => &.{.geometry}, + .image_gather_extended => &.{.shader}, + .storage_image_multisample => &.{.shader}, + .uniform_buffer_array_dynamic_indexing => &.{.shader}, + .sampled_image_array_dynamic_indexing => &.{.shader}, + .storage_buffer_array_dynamic_indexing => &.{.shader}, + .storage_image_array_dynamic_indexing => &.{.shader}, + .clip_distance => &.{.shader}, + .cull_distance => &.{.shader}, + .image_cube_array => &.{.sampled_cube_array}, + .sample_rate_shading => &.{.shader}, + .image_rect => &.{.sampled_rect}, + .sampled_rect => &.{.shader}, + .generic_pointer => &.{.addresses}, + .int8 => &.{}, + .input_attachment => &.{.shader}, + .sparse_residency => &.{.shader}, + .min_lod => &.{.shader}, + .sampled1d => &.{}, + .image1d => &.{.sampled1d}, + .sampled_cube_array => &.{.shader}, + .sampled_buffer => &.{}, + .image_buffer => &.{.sampled_buffer}, + .image_ms_array => &.{.shader}, + .storage_image_extended_formats => &.{.shader}, + .image_query => &.{.shader}, + .derivative_control => &.{.shader}, + .interpolation_function => &.{.shader}, + .transform_feedback => &.{.shader}, + .geometry_streams => &.{.geometry}, + .storage_image_read_without_format => &.{.shader}, + .storage_image_write_without_format => &.{.shader}, + .multi_viewport => &.{.geometry}, + .subgroup_dispatch => &.{.device_enqueue}, + .named_barrier => &.{.kernel}, + .pipe_storage => &.{.pipes}, + .group_non_uniform => &.{}, + .group_non_uniform_vote => &.{.group_non_uniform}, + .group_non_uniform_arithmetic => &.{.group_non_uniform}, + .group_non_uniform_ballot => &.{.group_non_uniform}, + .group_non_uniform_shuffle => &.{.group_non_uniform}, + .group_non_uniform_shuffle_relative => &.{.group_non_uniform}, + .group_non_uniform_clustered => &.{.group_non_uniform}, + .group_non_uniform_quad => &.{.group_non_uniform}, + .shader_layer => &.{}, + .shader_viewport_index => &.{}, + .uniform_decoration => &.{}, + .tile_image_color_read_access_ext => &.{}, + .tile_image_depth_read_access_ext => &.{}, + .tile_image_stencil_read_access_ext => &.{}, + .float8ext => &.{}, + .float8cooperative_matrix_ext => &.{ .float8ext, .cooperative_matrix_khr }, + .float6ext => &.{}, + .float4ext => &.{}, + .float8unsigned_e8m0ext => &.{}, + .mx_int8ext => &.{}, + .bitcast_extract_ext => &.{}, + .fragment_shading_rate_khr => &.{.shader}, + .subgroup_ballot_khr => &.{}, + .draw_parameters => &.{.shader}, + .workgroup_memory_explicit_layout_khr => &.{.shader}, + .workgroup_memory_explicit_layout8bit_access_khr => &.{.workgroup_memory_explicit_layout_khr}, + .workgroup_memory_explicit_layout16bit_access_khr => &.{.workgroup_memory_explicit_layout_khr}, + .subgroup_vote_khr => &.{}, + .storage_buffer16bit_access => &.{}, + .uniform_and_storage_buffer16bit_access => &.{.storage_buffer16bit_access}, + .storage_push_constant16 => &.{}, + .storage_input_output16 => &.{}, + .device_group => &.{}, + .multi_view => &.{.shader}, + .variable_pointers_storage_buffer => &.{.shader}, + .variable_pointers => &.{.variable_pointers_storage_buffer}, + .atomic_storage_ops => &.{.atomic_storage}, + .sample_mask_post_depth_coverage => &.{}, + .storage_buffer8bit_access => &.{}, + .uniform_and_storage_buffer8bit_access => &.{.storage_buffer8bit_access}, + .storage_push_constant8 => &.{}, + .denorm_preserve => &.{}, + .denorm_flush_to_zero => &.{}, + .signed_zero_inf_nan_preserve => &.{}, + .rounding_mode_rte => &.{}, + .rounding_mode_rtz => &.{}, + .ray_query_khr => &.{.shader}, + .untyped_pointers_khr => &.{}, + .ray_traversal_primitive_culling_khr => &.{ .ray_query_khr, .ray_tracing_khr }, + .ray_tracing_khr => &.{.shader}, + .stencil_export_ext => &.{.shader}, + .int64image_ext => &.{.int64}, + .shader_clock_khr => &.{}, + .quad_control_khr => &.{}, + .b_float16type_khr => &.{}, + .b_float16dot_product_khr => &.{.b_float16type_khr}, + .b_float16cooperative_matrix_khr => &.{ .b_float16type_khr, .cooperative_matrix_khr }, + .abort_khr => &.{}, + .descriptor_heap_ext => &.{.untyped_pointers_khr}, + .constant_data_khr => &.{}, + .shader_viewport_index_layer_ext => &.{.multi_viewport}, + .fragment_fully_covered_ext => &.{.shader}, + .mesh_shading_ext => &.{.shader}, + .fragment_barycentric_khr => &.{}, + .compute_derivative_group_quads_khr => &.{.shader}, + .fragment_density_ext => &.{.shader}, + .group_non_uniform_partitioned_ext => &.{}, + .shader_non_uniform => &.{.shader}, + .runtime_descriptor_array => &.{.shader}, + .input_attachment_array_dynamic_indexing => &.{.input_attachment}, + .uniform_texel_buffer_array_dynamic_indexing => &.{.sampled_buffer}, + .storage_texel_buffer_array_dynamic_indexing => &.{.image_buffer}, + .uniform_buffer_array_non_uniform_indexing => &.{.shader_non_uniform}, + .sampled_image_array_non_uniform_indexing => &.{.shader_non_uniform}, + .storage_buffer_array_non_uniform_indexing => &.{.shader_non_uniform}, + .storage_image_array_non_uniform_indexing => &.{.shader_non_uniform}, + .input_attachment_array_non_uniform_indexing => &.{ .input_attachment, .shader_non_uniform }, + .uniform_texel_buffer_array_non_uniform_indexing => &.{ .sampled_buffer, .shader_non_uniform }, + .storage_texel_buffer_array_non_uniform_indexing => &.{ .image_buffer, .shader_non_uniform }, + .ray_tracing_position_fetch_khr => &.{.shader}, + .vulkan_memory_model => &.{}, + .vulkan_memory_model_device_scope => &.{}, + .physical_storage_buffer_addresses => &.{.shader}, + .compute_derivative_group_linear_khr => &.{.shader}, + .fragment_shader_sample_interlock_ext => &.{.shader}, + .fragment_shader_shading_rate_interlock_ext => &.{.shader}, + .fragment_shader_pixel_interlock_ext => &.{.shader}, + .demote_to_helper_invocation => &.{.shader}, + .ray_tracing_opacity_micromap_khr => &.{.shader}, + .shader_invocation_reorder_ext => &.{.ray_tracing_khr}, + .ray_query_position_fetch_khr => &.{.shader}, + .long_vector_ext => &.{}, + .shader64bit_indexing_ext => &.{}, + .cooperative_matrix_conversions_ext => &.{}, + .cooperative_matrix_reductions_ext => &.{}, + .cooperative_matrix_per_element_operations_ext => &.{}, + .cooperative_matrix_get_coordinate_ext => &.{}, + .atomic_float32min_max_ext => &.{}, + .atomic_float64min_max_ext => &.{}, + .atomic_float16min_max_ext => &.{}, + .expect_assume_khr => &.{}, + .dot_product_input_all => &.{}, + .dot_product_input4x8bit => &.{.int8}, + .dot_product_input4x8bit_packed => &.{}, + .dot_product => &.{}, + .ray_cull_mask_khr => &.{}, + .cooperative_matrix_khr => &.{}, + .replicated_composites_ext => &.{}, + .bit_instructions => &.{}, + .group_non_uniform_rotate_khr => &.{.group_non_uniform}, + .float_controls2 => &.{}, + .fmakhr => &.{}, + .ray_tracing_opacity_micromap_execution_mode_khr => &.{.shader}, + .atomic_float32add_ext => &.{}, + .atomic_float64add_ext => &.{}, + .opt_none_ext => &.{}, + .atomic_float16add_ext => &.{}, + .split_barrier_ext => &.{}, + .arithmetic_fence_ext => &.{}, + .group_uniform_arithmetic_khr => &.{}, }; } }; @@ -4604,6 +4868,11 @@ pub const FPEncoding = enum(u32) { b_float16khr = 0, float8e4m3ext = 4214, float8e5m2ext = 4215, + float6e2m3ext = 4223, + float6e3m2ext = 4224, + float4e2m1ext = 4225, + float8unsigned_e8m0ext = 4226, + mx_int8ext = 4227, }; pub const CooperativeVectorMatrixLayout = enum(u32) { row_major_nv = 0, @@ -4628,6 +4897,12 @@ pub const ComponentType = enum(u32) { float_e4m3nv = 1000491002, float_e5m2nv = 1000491003, }; +pub const GatherModes = enum(u32) { + gather4x1qcom = 0, + gather_dqcom = 1, + gather_h2qcom = 2, + gather_v2qcom = 3, +}; pub const TensorOperands = packed struct(Word) { _reserved_bits_0_to_31: u32 = 0, }; @@ -4709,20 +4984,19 @@ pub const @"NonSemantic.Shader.DebugInfo.100.DebugImportedEntity" = enum(u32) { pub const InstructionSet = enum { core, @"OpenCL.std", - @"GLSL.std.450", @"NonSemantic.Shader.DebugInfo.100", + @"GLSL.std.450", pub fn operands(inst_set: InstructionSet, opcode: Word) ?[]const Operand { return switch (inst_set) { .core => if (std.enums.fromInt(Opcode, opcode)) |op| op.operands() else null, .@"OpenCL.std" => if (std.enums.fromInt(OpenClOpcode, opcode)) |op| op.operands() else null, - .@"GLSL.std.450" => if (std.enums.fromInt(GlslOpcode, opcode)) |op| op.operands() else null, .@"NonSemantic.Shader.DebugInfo.100" => if (std.enums.fromInt(ShaderDebugInfoOpCode, opcode)) |op| op.operands() else null, + .@"GLSL.std.450" => if (std.enums.fromInt(GlslOpcode, opcode)) |op| op.operands() else null, }; } }; pub const Extension = enum { - v1_0, v1_1, v1_2, v1_3, @@ -4731,6 +5005,7 @@ pub const Extension = enum { v1_6, SPV_EXT_shader_tile_image, SPV_EXT_float8, + SPV_EXT_ocp_microscaling_types, SPV_KHR_fragment_shading_rate, SPV_KHR_shader_ballot, SPV_KHR_shader_draw_parameters, @@ -4755,7 +5030,6 @@ pub const Extension = enum { SPV_KHR_abort, SPV_EXT_descriptor_heap, SPV_KHR_constant_data, - SPV_KHR_poison_freeze, SPV_EXT_shader_viewport_index_layer, SPV_EXT_fragment_fully_covered, SPV_EXT_mesh_shader, @@ -4770,10 +5044,12 @@ pub const Extension = enum { SPV_KHR_physical_storage_buffer, SPV_EXT_fragment_shader_interlock, SPV_EXT_demote_to_helper_invocation, + SPV_KHR_opacity_micromap, SPV_EXT_opacity_micromap, SPV_EXT_shader_invocation_reorder, SPV_EXT_long_vector, SPV_EXT_shader_64bit_indexing, + SPV_EXT_cooperative_matrix_maintenance1, SPV_EXT_shader_atomic_float_min_max, SPV_KHR_expect_assume, SPV_KHR_integer_dot_product, @@ -4787,6 +5063,7 @@ pub const Extension = enum { SPV_EXT_shader_atomic_float_add, SPV_EXT_optnone, SPV_EXT_shader_atomic_float16_add, + SPV_EXT_split_barrier, SPV_EXT_arithmetic_fence, SPV_KHR_uniform_group_instructions, }; diff --git a/src/codegen/x86_64/abi.zig b/src/codegen/x86_64/abi.zig index 2d48907ae2..9dee915233 100644 --- a/src/codegen/x86_64/abi.zig +++ b/src/codegen/x86_64/abi.zig @@ -123,14 +123,14 @@ pub fn classifyWindows(init_ty: Type, zcu: *Zcu, target: *const std.Target, ctx: else => switch (ty.zigTypeTag(zcu)) { .int => .win_i128, .@"struct", .@"union" => if (ty.containerLayout(zcu) != .@"packed" or - target.cpu.has(.x86, .soft_float)) .memory else .win_i128, + target.abi.float() == .soft) .memory else .win_i128, else => .memory, }, }, .noreturn => unreachable, .float => switch (ty.floatBits(target)) { else => unreachable, - 16, 32, 64 => if (target.cpu.has(.x86, .soft_float)) .integer else .sse, + 16, 32, 64 => if (target.abi.float() == .soft) .integer else .sse, 80, 128 => .memory, }, .vector => { @@ -193,7 +193,7 @@ pub fn classifySystemV(ty: Type, zcu: *Zcu, target: *const std.Target, ctx: Cont if (bits <= 64 * 4) return Class.four_integers; return Class.stack; }, - .float => if (target.cpu.has(.x86, .soft_float)) switch (ty.floatBits(target)) { + .float => if (target.abi.float() == .soft) switch (ty.floatBits(target)) { else => unreachable, 16, 32, 64 => return Class.one_integer, 80, 128 => return Class.two_integers, diff --git a/src/libs/freebsd.zig b/src/libs/freebsd.zig index 8f07d8fb8a..afb5229dbb 100644 --- a/src/libs/freebsd.zig +++ b/src/libs/freebsd.zig @@ -84,10 +84,6 @@ pub fn buildCrtFile(comp: *Compilation, crt_file: CrtFile, prog_node: std.Progre "-w", // Disable all warnings. }); - if (target.cpu.arch.isPowerPC64()) { - try cflags.append("-mlongcall"); - } - var acflags = std.array_list.Managed([]const u8).init(arena); try acflags.appendSlice(&.{ "-DLOCORE", diff --git a/src/libs/libcxx.zig b/src/libs/libcxx.zig index 376887fd9e..4fd360c2bc 100644 --- a/src/libs/libcxx.zig +++ b/src/libs/libcxx.zig @@ -147,6 +147,8 @@ pub fn buildLibCxx(comp: *Compilation, prog_node: std.Progress.Node) BuildError! .link_libc = true, .lto = comp.config.lto, .any_sanitize_thread = comp.config.any_sanitize_thread, + .function_sections = true, + .data_sections = true, }) catch |err| { comp.lockAndSetMiscFailure( .libcxx, @@ -255,8 +257,6 @@ pub fn buildLibCxx(comp: *Compilation, prog_node: std.Progress.Node) BuildError! .root_name = root_name, .libc_installation = comp.libc_installation, .emit_bin = .yes_cache, - .function_sections = true, - .data_sections = true, .c_source_files = c_source_files.items, .verbose_cc = comp.verbose_cc, .verbose_link = comp.verbose_link, @@ -328,6 +328,8 @@ pub fn buildLibCxxAbi(comp: *Compilation, prog_node: std.Progress.Node) BuildErr .any_unwind_tables = unwind_tables != .none, .lto = comp.config.lto, .any_sanitize_thread = comp.config.any_sanitize_thread, + .function_sections = true, + .data_sections = true, }) catch |err| { comp.lockAndSetMiscFailure( .libcxxabi, @@ -436,8 +438,6 @@ pub fn buildLibCxxAbi(comp: *Compilation, prog_node: std.Progress.Node) BuildErr .root_name = root_name, .libc_installation = comp.libc_installation, .emit_bin = .yes_cache, - .function_sections = true, - .data_sections = true, .c_source_files = c_source_files.items, .verbose_cc = comp.verbose_cc, .verbose_link = comp.verbose_link, diff --git a/src/libs/libtsan.zig b/src/libs/libtsan.zig index bc8cacd84c..2201a28649 100644 --- a/src/libs/libtsan.zig +++ b/src/libs/libtsan.zig @@ -69,6 +69,8 @@ pub fn buildTsan(comp: *Compilation, prog_node: std.Progress.Node) BuildError!vo .any_unwind_tables = unwind_tables != .none, // LLVM disables LTO for its libtsan. .lto = .none, + .function_sections = true, + .data_sections = true, }) catch |err| { comp.lockAndSetMiscFailure( .libtsan, @@ -290,8 +292,6 @@ pub fn buildTsan(comp: *Compilation, prog_node: std.Progress.Node) BuildError!vo .root_name = root_name, .libc_installation = comp.libc_installation, .emit_bin = .yes_cache, - .function_sections = true, - .data_sections = true, .c_source_files = c_source_files.items, .verbose_cc = comp.verbose_cc, .verbose_link = comp.verbose_link, diff --git a/src/libs/libunwind.zig b/src/libs/libunwind.zig index d8d3456d15..76bbbc47c1 100644 --- a/src/libs/libunwind.zig +++ b/src/libs/libunwind.zig @@ -42,6 +42,8 @@ pub fn buildStaticLib(comp: *Compilation, prog_node: std.Progress.Node) BuildErr .link_libc = true, .any_unwind_tables = unwind_tables != .none, .lto = comp.config.lto, + .function_sections = true, + .data_sections = true, }) catch |err| { comp.lockAndSetMiscFailure( .libunwind, @@ -152,8 +154,6 @@ pub fn buildStaticLib(comp: *Compilation, prog_node: std.Progress.Node) BuildErr .main_mod = null, .libc_installation = comp.libc_installation, .emit_bin = .yes_cache, - .function_sections = true, - .data_sections = true, .c_source_files = &c_source_files, .verbose_cc = comp.verbose_cc, .verbose_link = comp.verbose_link, diff --git a/src/link/Elf.zig b/src/link/Elf.zig index 1067b9a50a..01e6b4c9a2 100644 --- a/src/link/Elf.zig +++ b/src/link/Elf.zig @@ -1538,8 +1538,6 @@ pub fn writeElfHeader(self: *Elf) !void { hdr_buf[index] = @backingInt(@as(elf.OSABI, switch (target.cpu.arch) { .amdgcn => switch (target.os.tag) { .amdhsa => .AMDGPU_HSA, - .amdpal => .AMDGPU_PAL, - .mesa3d => .AMDGPU_MESA3D, else => .NONE, }, .msp430 => .STANDALONE, diff --git a/src/link/Elf2.zig b/src/link/Elf2.zig index 4be20575d8..3386f9928b 100644 --- a/src/link/Elf2.zig +++ b/src/link/Elf2.zig @@ -5076,8 +5076,6 @@ fn create( .openbsd => .OPENBSD, .cuda => .CUDA, .amdhsa => .AMDGPU_HSA, - .amdpal => .AMDGPU_PAL, - .mesa3d => .AMDGPU_MESA3D, }; const @"type": EhdrType = switch (comp.config.output_mode) { .Exe => if (comp.config.pie or target.os.tag == .haiku) .DYN else .EXEC, @@ -5704,11 +5702,10 @@ fn initHeaders( ehdr.shoff = 0; ehdr.flags = switch (machine) { .LOONGARCH => .{ .loongarch = .{ - .base_abi_modifier = mod: { - const cpu = comp.getTarget().cpu; - if (cpu.has(.loongarch, .d)) break :mod .d; - if (cpu.has(.loongarch, .f)) break :mod .f; - break :mod .s; + .base_abi_modifier = switch (comp.getTarget().abi) { + .gnusf, .muslsf => .s, + .gnuf32, .muslf32 => .f, + else => .d, }, .abi_extension = .base, .abi_version = 1, diff --git a/src/main.zig b/src/main.zig index 8e044e0751..7df79f83f2 100644 --- a/src/main.zig +++ b/src/main.zig @@ -921,8 +921,6 @@ fn buildOutputType( var version: std.SemanticVersion = .{ .major = 0, .minor = 0, .patch = 0 }; var have_version = false; var compatibility_version: ?std.SemanticVersion = null; - var function_sections = false; - var data_sections = false; var listen: Listen = .none; var debug_compile_errors = false; var debug_incremental = false; @@ -1684,13 +1682,13 @@ fn buildOutputType( } else if (mem.eql(u8, arg, "-fno-single-threaded")) { mod_opts.single_threaded = false; } else if (mem.eql(u8, arg, "-ffunction-sections")) { - function_sections = true; + create_module.opts.function_sections = true; } else if (mem.eql(u8, arg, "-fno-function-sections")) { - function_sections = false; + create_module.opts.function_sections = false; } else if (mem.eql(u8, arg, "-fdata-sections")) { - data_sections = true; + create_module.opts.data_sections = true; } else if (mem.eql(u8, arg, "-fno-data-sections")) { - data_sections = false; + create_module.opts.data_sections = false; } else if (mem.eql(u8, arg, "-fbuiltin")) { mod_opts.no_builtin = false; } else if (mem.eql(u8, arg, "-fno-builtin")) { @@ -2137,10 +2135,10 @@ fn buildOutputType( .no_red_zone => mod_opts.red_zone = false, .omit_frame_pointer => mod_opts.omit_frame_pointer = true, .no_omit_frame_pointer => mod_opts.omit_frame_pointer = false, - .function_sections => function_sections = true, - .no_function_sections => function_sections = false, - .data_sections => data_sections = true, - .no_data_sections => data_sections = false, + .function_sections => create_module.opts.function_sections = true, + .no_function_sections => create_module.opts.function_sections = false, + .data_sections => create_module.opts.data_sections = true, + .no_data_sections => create_module.opts.data_sections = false, .builtin => mod_opts.no_builtin = false, .no_builtin => mod_opts.no_builtin = true, .color_diagnostics => color = .on, @@ -3722,8 +3720,6 @@ fn buildOutputType( .force_undefined_symbols = force_undefined_symbols, .stack_size = stack_size, .image_base = image_base, - .function_sections = function_sections, - .data_sections = data_sections, .clang_passthrough_mode = clang_passthrough_mode, .clang_preprocessor_mode = clang_preprocessor_mode, .version = optional_version, diff --git a/src/target.zig b/src/target.zig index bb46a9135e..b4d9486fd3 100644 --- a/src/target.zig +++ b/src/target.zig @@ -76,12 +76,16 @@ pub fn requiresPic(target: *const std.Target) bool { return (target.os.tag == .windows or target.os.tag == .uefi) and (target.cpu.arch == .aarch64 or target.cpu.arch == .x86_64); } -pub fn requiresPicForDynamicLink(target: *const std.Target) bool { +pub fn requiresPicForDynamicLink(target: *const std.Target, output_mode: std.lang.OutputMode) bool { assert(canDynamicLink(target)); - return switch (target.os.tag) { - .windows => target.cpu.arch == .aarch64 or target.cpu.arch == .x86_64, - else => !target.cpu.arch.isWasm(), + return switch (output_mode) { + .Lib => switch (target.os.tag) { + .windows => target.cpu.arch == .aarch64 or target.cpu.arch == .x86_64, + else => !target.cpu.arch.isWasm(), + }, + .Exe => target.cpu.arch.isMips(), + .Obj => false, }; } @@ -254,6 +258,7 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat) // Third-party LLVM backend exists. .ez80, + .z80, => false, // No LLVM backend exists. @@ -261,7 +266,6 @@ pub fn hasLlvmSupport(target: *const std.Target, ofmt: std.Target.ObjectFormat) .arceb, .hppa, .hppa64, - .kalimba, .kvx, .m88k, .microblaze, @@ -534,6 +538,8 @@ pub fn clangSupportsTargetCpuArg(target: *const std.Target) bool { return switch (target.cpu.arch) { .arc, .msp430, + .spirv32, + .spirv64, .ve, .xcore, .xtensa, @@ -651,8 +657,7 @@ pub fn addrSpaceIsLogical(target: *const std.Target, as: AddressSpace) bool { .push_constant, => true, .shared => !features.isEnabled(@backingInt(std.Target.spirv.Feature.variable_pointers)), - .storage_buffer => !features.isEnabled(@backingInt(std.Target.spirv.Feature.variable_pointers)) and - !features.isEnabled(@backingInt(std.Target.spirv.Feature.variable_pointers_storage_buffer)), + .storage_buffer => !features.isEnabled(@backingInt(std.Target.spirv.Feature.variable_pointers_storage_buffer)), .physical_storage_buffer => false, else => unreachable, }, @@ -660,56 +665,14 @@ pub fn addrSpaceIsLogical(target: *const std.Target, as: AddressSpace) bool { }; } -pub fn isDynamicAMDGCNFeature(target: *const std.Target, feature: std.Target.Cpu.Feature) bool { - if (target.cpu.arch != .amdgcn) return false; - - const sramecc_only = &[_]*const std.Target.Cpu.Model{ - &std.Target.amdgcn.cpu.gfx1010, - &std.Target.amdgcn.cpu.gfx1011, - &std.Target.amdgcn.cpu.gfx1012, - &std.Target.amdgcn.cpu.gfx1013, - }; - const xnack_or_sramecc = &[_]*const std.Target.Cpu.Model{ - &std.Target.amdgcn.cpu.gfx1030, - &std.Target.amdgcn.cpu.gfx1031, - &std.Target.amdgcn.cpu.gfx1032, - &std.Target.amdgcn.cpu.gfx1033, - &std.Target.amdgcn.cpu.gfx1034, - &std.Target.amdgcn.cpu.gfx1035, - &std.Target.amdgcn.cpu.gfx1036, - &std.Target.amdgcn.cpu.gfx1100, - &std.Target.amdgcn.cpu.gfx1101, - &std.Target.amdgcn.cpu.gfx1102, - &std.Target.amdgcn.cpu.gfx1103, - &std.Target.amdgcn.cpu.gfx1150, - &std.Target.amdgcn.cpu.gfx1151, - &std.Target.amdgcn.cpu.gfx1152, - &std.Target.amdgcn.cpu.gfx1153, - &std.Target.amdgcn.cpu.gfx1200, - &std.Target.amdgcn.cpu.gfx1201, - }; - const feature_tag: std.Target.amdgcn.Feature = @fromBackingInt(@intCast(feature.index)); - - if (feature_tag == .sramecc) { - if (std.mem.findScalar( - *const std.Target.Cpu.Model, - sramecc_only ++ xnack_or_sramecc, - target.cpu.model, - )) |_| return true; - } - if (feature_tag == .xnack) { - if (std.mem.findScalar( - *const std.Target.Cpu.Model, - xnack_or_sramecc, - target.cpu.model, - )) |_| return true; - } - - return false; -} - pub fn llvmMachineAbi(target: *const std.Target) ?[:0]const u8 { return switch (target.cpu.arch) { + .aarch64, .aarch64_be => if (target.abi.float() == .soft) + "aapcs-soft" + else if (target.os.tag.isDarwin()) + "darwinpcs" + else + "aapcs", .arm, .armeb, .thumb, .thumbeb => "aapcs", .loongarch64 => switch (target.abi) { .gnusf, .muslsf => "lp64s", diff --git a/stage1/zig.h b/stage1/zig.h index 98e8e6a579..dedaeb4f96 100644 --- a/stage1/zig.h +++ b/stage1/zig.h @@ -99,6 +99,8 @@ #define zig_x86 #elif defined(__xtensa__) #define zig_xtensa +#elif defined (__z80) +#define zig_z80 #elif defined (__ez80) #define zig_ez80 #define zig_z80 @@ -261,6 +263,12 @@ #define zig_no_builtin #endif +#if zig_has_attribute(patchable_function_entry) +#define zig_patchable_function_entry(count) __attribute__((patchable_function_entry(count))) +#else +#define zig_patchable_function_entry(count) zig_patchable_function_entry_unavailable +#endif + #if zig_has_attribute(aligned) || defined(zig_tinyc) #define zig_under_align(alignment) __attribute__((aligned(alignment))) #elif defined(zig_msvc) @@ -6725,19 +6733,7 @@ static inline void* zig_e_zig_windows_peb(void) { #endif -#if defined(zig_loongarch) - -static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) zig_mangled(zig_e_zig_loongarch_cpucfg, "zig_loongarch_cpucfg"); - -static inline void zig_e_zig_loongarch_cpucfg(uint32_t word, uint32_t* result) { -#if defined(zig_gnuc_asm) - __asm__("cpucfg %[result], %[word]" : [result] "=r" (*result) : [word] "r" (word)); -#else - *result = 0; -#endif -} - -#elif defined(zig_x86) && !defined(zig_x86_16) +#if defined(zig_x86) && !defined(zig_x86_16) static inline void zig_e_zig_x86_cpuid(uint32_t leaf_id, uint32_t subid, uint32_t* eax, uint32_t* ebx, uint32_t* ecx, uint32_t* edx) zig_mangled(zig_e_zig_x86_cpuid, "zig_x86_cpuid"); static inline uint32_t zig_e_zig_x86_get_xcr0(void) zig_mangled(zig_e_zig_x86_get_xcr0, "zig_x86_get_xcr0"); diff --git a/stage1/zig1.wasm b/stage1/zig1.wasm index 8587696fd7..36eecad204 100644 Binary files a/stage1/zig1.wasm and b/stage1/zig1.wasm differ diff --git a/test/cases/compile_errors/callconv_spirv_on_unsupported_platform.zig b/test/cases/compile_errors/callconv_spirv_on_unsupported_platform.zig index 1eb4fee387..72fdae9524 100644 --- a/test/cases/compile_errors/callconv_spirv_on_unsupported_platform.zig +++ b/test/cases/compile_errors/callconv_spirv_on_unsupported_platform.zig @@ -22,7 +22,7 @@ export fn entry4() void { // error // backend=selfhosted // target=spirv64-opencl -// cpu_features=opencl_v2+mesh_shading_ext +// cpu_features=opencl_v2_1+mesh_shading_ext // // :1:28: error: calling convention 'spirv_fragment' not supported by compiler backend 'stage2_spirv' // :2:28: error: calling convention 'spirv_vertex' not supported by compiler backend 'stage2_spirv' diff --git a/test/llvm/allowzero b/test/llvm/allowzero index f5ecf7cf30..e8945c03eb 100644 --- a/test/llvm/allowzero +++ b/test/llvm/allowzero @@ -1,6 +1,4 @@ #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic #skip bpfeb-freestanding-none-baseline-whole-llvm-lld-pic diff --git a/test/llvm/array_to_vector b/test/llvm/array_to_vector index fdc727efc4..773db908d5 100644 --- a/test/llvm/array_to_vector +++ b/test/llvm/array_to_vector @@ -1,6 +1,4 @@ #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic #skip csky-freestanding-eabi-baseline-whole-llvm-lld-pic #skip csky-freestanding-eabihf-baseline-whole-llvm-lld-pic diff --git a/test/llvm/dead_store b/test/llvm/dead_store index cdccf17e30..c3c0d3b957 100644 --- a/test/llvm/dead_store +++ b/test/llvm/dead_store @@ -1,6 +1,4 @@ #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic #skip csky-freestanding-eabi-baseline-whole-llvm-lld-pic #skip csky-freestanding-eabihf-baseline-whole-llvm-lld-pic diff --git a/test/llvm/empty_analyze b/test/llvm/empty_analyze index 83f8b9adfa..ecb6017231 100644 --- a/test/llvm/empty_analyze +++ b/test/llvm/empty_analyze @@ -1,6 +1,3 @@ -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic - #skip arm-uefi-eabi-baseline-whole-llvm-lld-pic #skip arm-uefi-eabihf-baseline-whole-llvm-lld-pic diff --git a/test/llvm/empty_assembly b/test/llvm/empty_assembly index 30a58733d0..f80c5f384b 100644 --- a/test/llvm/empty_assembly +++ b/test/llvm/empty_assembly @@ -1,6 +1,3 @@ -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic - #skip arm-uefi-eabi-baseline-whole-llvm-lld-pic #skip arm-uefi-eabihf-baseline-whole-llvm-lld-pic diff --git a/test/llvm/empty_object b/test/llvm/empty_object index b42e86be09..393187750f 100644 --- a/test/llvm/empty_object +++ b/test/llvm/empty_object @@ -1,6 +1,3 @@ -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic - #skip arc-freestanding-none-baseline-whole-llvm-lld-pic #skip arc-linux-gnu-baseline-whole-llvm-lld-pic #skip arc-linux-none-baseline-whole-llvm-lld-pic diff --git a/test/llvm/load_store_bool b/test/llvm/load_store_bool index a405f1d6ad..9561f96945 100644 --- a/test/llvm/load_store_bool +++ b/test/llvm/load_store_bool @@ -1,6 +1,4 @@ #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic #skip bpfeb-freestanding-none-baseline-whole-llvm-lld-pic diff --git a/test/llvm/matrix.zon b/test/llvm/matrix.zon index f2aa87c2c8..4a7dc5a9a5 100644 --- a/test/llvm/matrix.zon +++ b/test/llvm/matrix.zon @@ -38,8 +38,6 @@ .{ .cpu = .{ .aarch64_be = .{} }, .os = .{ .netbsd = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .amdgcn = .{} }, .os = .{ .amdhsa = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, - .{ .cpu = .{ .amdgcn = .{} }, .os = .{ .amdpal = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, - .{ .cpu = .{ .amdgcn = .{} }, .os = .{ .mesa3d = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .arc = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .arc = .{} }, .os = .{ .linux = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, @@ -65,6 +63,7 @@ .{ .cpu = .{ .arm = .{} }, .os = .{ .openbsd = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .arm = .{} }, .os = .{ .rtems = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .arm = .{} }, .os = .{ .rtems = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, + .{ .cpu = .{ .arm = .{} }, .os = .{ .@"switch" = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .arm = .{} }, .os = .{ .uefi = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .arm = .{} }, .os = .{ .uefi = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .arm = .{} }, .os = .{ .vita = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, @@ -238,18 +237,21 @@ .{ .cpu = .{ .riscv64be = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, - .{ .cpu = .{ .s390x = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, + .{ .cpu = .{ .s390x = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, + .{ .cpu = .{ .s390x = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .s390x = .{} }, .os = .{ .linux = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .s390x = .{} }, .os = .{ .linux = .{} }, .abi = .{ .musl = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .s390x = .{} }, .os = .{ .linux = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, - .{ .cpu = .{ .sparc = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, + .{ .cpu = .{ .sparc = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, + .{ .cpu = .{ .sparc = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .sparc = .{} }, .os = .{ .linux = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .sparc = .{} }, .os = .{ .linux = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .sparc = .{} }, .os = .{ .netbsd = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .sparc = .{} }, .os = .{ .rtems = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, - .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, + .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, + .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .linux = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .linux = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, .{ .cpu = .{ .sparc64 = .{} }, .os = .{ .netbsd = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, @@ -299,7 +301,8 @@ .{ .cpu = .{ .wasm64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .wasm64 = .{} }, .os = .{ .wasi = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, - .{ .cpu = .{ .x86 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, + .{ .cpu = .{ .x86 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, + .{ .cpu = .{ .x86 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .x86 = .{} }, .os = .{ .haiku = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .x86 = .{} }, .os = .{ .hurd = .{} }, .abi = .{ .gnu = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .x86 = .{} }, .os = .{ .illumos = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, @@ -316,8 +319,8 @@ .{ .cpu = .{ .x86 = .{} }, .os = .{ .windows = .{} }, .abi = .{ .msvc = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .lld, .pic = .pic }, .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .freebsd = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, - .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, - .{ .cpu = .{ .x86_64 = .{ .features = .{ .add = .{.soft_float}, .remove = .{ .mmx, .sse, .sse2, .avx, .avx2 } } } }, .os = .{ .freestanding = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, + .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabi = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, + .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .freestanding = .{} }, .abi = .{ .eabihf = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .fuchsia = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .dragonfly = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .new, .pic = .pic }, .{ .cpu = .{ .x86_64 = .{} }, .os = .{ .driverkit = .{} }, .abi = .{ .none = .{} }, .cache_mode = .whole, .backend = .llvm, .linker = .old, .pic = .pic }, diff --git a/test/llvm/nonnull b/test/llvm/nonnull index 82452ee40c..2f63e658d2 100644 --- a/test/llvm/nonnull +++ b/test/llvm/nonnull @@ -1,6 +1,4 @@ #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic #skip csky-freestanding-eabi-baseline-whole-llvm-lld-pic #skip csky-freestanding-eabihf-baseline-whole-llvm-lld-pic diff --git a/test/llvm/unused_load b/test/llvm/unused_load index e1e2aa78c7..12c25689c2 100644 --- a/test/llvm/unused_load +++ b/test/llvm/unused_load @@ -1,6 +1,4 @@ #skip amdgcn-amdhsa-none-baseline-whole-llvm-lld-pic -#skip amdgcn-amdpal-none-baseline-whole-llvm-lld-pic -#skip amdgcn-mesa3d-none-baseline-whole-llvm-lld-pic #skip csky-freestanding-eabi-baseline-whole-llvm-lld-pic #skip csky-freestanding-eabihf-baseline-whole-llvm-lld-pic diff --git a/test/tests.zig b/test/tests.zig index af1be75dee..c2b02eb273 100644 --- a/test/tests.zig +++ b/test/tests.zig @@ -420,25 +420,27 @@ const module_test_targets = blk: { .link_libc = true, }, - // Similar to Thumb, we need long calls on Hexagon due to relocation range issues. .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "hexagon-linux-none", - .cpu_features = "baseline+long_calls", - }) catch unreachable, + .target = .{ + .cpu_arch = .hexagon, + .os_tag = .linux, + .abi = .none, + }, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "hexagon-linux-musl", - .cpu_features = "baseline+long_calls", - }) catch unreachable, + .target = .{ + .cpu_arch = .hexagon, + .os_tag = .linux, + .abi = .musl, + }, .link_libc = true, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "hexagon-linux-musl", - .cpu_features = "baseline+long_calls", - }) catch unreachable, + .target = .{ + .cpu_arch = .hexagon, + .os_tag = .linux, + .abi = .musl, + }, .linkage = .dynamic, .link_libc = true, .extra_target = true, @@ -1074,69 +1076,66 @@ const module_test_targets = blk: { .link_libc = true, }, - // Calls are normally lowered to branch instructions that only support +/- 16 MB range when - // targeting Thumb. This easily becomes insufficient for our test binaries, so use long - // calls to avoid out-of-range relocations. .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumb-linux-eabi", - .cpu_features = "baseline+long_calls", - }) catch unreachable, - .pic = false, // Long calls don't work with PIC. + .target = .{ + .cpu_arch = .thumb, + .os_tag = .linux, + .abi = .eabi, + }, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumb-linux-eabihf", - .cpu_features = "baseline+long_calls", - }) catch unreachable, - .pic = false, // Long calls don't work with PIC. + .target = .{ + .cpu_arch = .thumb, + .os_tag = .linux, + .abi = .eabihf, + }, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumb-linux-musleabi", - .cpu_features = "baseline+long_calls", - }) catch unreachable, + .target = .{ + .cpu_arch = .thumb, + .os_tag = .linux, + .abi = .musleabi, + }, .link_libc = true, - .pic = false, // Long calls don't work with PIC. }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumb-linux-musleabihf", - .cpu_features = "baseline+long_calls", - }) catch unreachable, + .target = .{ + .cpu_arch = .thumb, + .os_tag = .linux, + .abi = .musleabihf, + }, .link_libc = true, - .pic = false, // Long calls don't work with PIC. }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumbeb-linux-eabi", - .cpu_features = "baseline+long_calls", - }) catch unreachable, - .pic = false, // Long calls don't work with PIC. + .target = .{ + .cpu_arch = .thumbeb, + .os_tag = .linux, + .abi = .eabi, + }, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumbeb-linux-eabihf", - .cpu_features = "baseline+long_calls", - }) catch unreachable, - .pic = false, // Long calls don't work with PIC. + .target = .{ + .cpu_arch = .thumbeb, + .os_tag = .linux, + .abi = .eabihf, + }, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumbeb-linux-musleabi", - .cpu_features = "baseline+long_calls", - }) catch unreachable, + .target = .{ + .cpu_arch = .thumbeb, + .os_tag = .linux, + .abi = .musleabi, + }, .link_libc = true, - .pic = false, // Long calls don't work with PIC. }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumbeb-linux-musleabihf", - .cpu_features = "baseline+long_calls", - }) catch unreachable, + .target = .{ + .cpu_arch = .thumbeb, + .os_tag = .linux, + .abi = .musleabihf, + }, .link_libc = true, - .pic = false, // Long calls don't work with PIC. }, .{ @@ -1980,33 +1979,33 @@ const c_abi_targets = blk: { }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumb-linux-musleabi", - .cpu_features = "baseline+long_calls", - }) catch unreachable, - .pic = false, // Long calls don't work with PIC. + .target = .{ + .cpu_arch = .thumb, + .os_tag = .linux, + .abi = .musleabi, + }, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumb-linux-musleabihf", - .cpu_features = "baseline+long_calls", - }) catch unreachable, - .pic = false, // Long calls don't work with PIC. + .target = .{ + .cpu_arch = .thumb, + .os_tag = .linux, + .abi = .musleabihf, + }, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumbeb-linux-musleabi", - .cpu_features = "baseline+long_calls", - }) catch unreachable, - .pic = false, // Long calls don't work with PIC. + .target = .{ + .cpu_arch = .thumbeb, + .os_tag = .linux, + .abi = .musleabi, + }, }, .{ - .target = std.Target.Query.parse(.{ - .arch_os_abi = "thumbeb-linux-musleabihf", - .cpu_features = "baseline+long_calls", - }) catch unreachable, - .pic = false, // Long calls don't work with PIC. + .target = .{ + .cpu_arch = .thumbeb, + .os_tag = .linux, + .abi = .musleabihf, + }, }, .{ @@ -2693,8 +2692,8 @@ fn addOneModuleTest( if (options.build_options) |build_options| { these_tests.root_module.addOptions("build_options", build_options); } - if (test_target.function_sections) |fs| these_tests.link_function_sections = fs; - if (test_target.data_sections) |ds| these_tests.link_data_sections = ds; + if (test_target.function_sections) |fs| these_tests.function_sections = fs; + if (test_target.data_sections) |ds| these_tests.data_sections = ds; const single_threaded_suffix = if (test_target.single_threaded == true) "-single" else ""; const backend_suffix = if (test_target.use_llvm == true) "-llvm" diff --git a/tools/gen_spirv_spec.zig b/tools/gen_spirv_spec.zig index 4c9f4b0c9a..43324945e9 100644 --- a/tools/gen_spirv_spec.zig +++ b/tools/gen_spirv_spec.zig @@ -268,13 +268,10 @@ fn render( ); try writer.print( - \\pub const version: Version = .{{ .major = {}, .minor = {}, .patch = {} }}; \\pub const magic_number: Word = {s}; \\ \\ - , - .{ registry.major_version, registry.minor_version, registry.revision, registry.magic_number }, - ); + , .{registry.magic_number}); var all_operand_kinds: OperandKindMap = .empty; for (registry.operand_kinds) |kind| { @@ -311,7 +308,6 @@ fn renderExtension( ) !void { try writer.writeAll( \\pub const Extension = enum { - \\v1_0, \\v1_1, \\v1_2, \\v1_3, @@ -808,17 +804,50 @@ fn renderValueEnum( if (std.mem.eql(u8, "Capability", enumeration.kind)) { try writer.writeAll( \\ - \\pub fn dependencies(self: Capability) []const Extension { + \\pub fn dependencyExtensions(self: Capability) []const Extension { \\ return switch (self) { ); for (enum_indices) |i| { const enumerant = enumerants[i]; const enum_version = enumerant.version.?; const minor = if (enum_version[0] == 'N') '0' else enum_version[2]; - try writer.print("\n.{f} => &.{{.v1_{c}", .{ formatId(enumerant.enumerant), minor }); + try writer.print("\n.{f} => &.{{", .{formatId(enumerant.enumerant)}); + var comma = if (minor != '0') b: { + try writer.print(".v1_{c}", .{minor}); + break :b true; + } else false; for (enumerant.extensions) |extension| { if (!isAllowedExtension(extension)) continue; - try writer.print(", .{s}", .{extension}); + if (comma) try writer.writeAll(", "); + try writer.print(".{s}", .{extension}); + comma = true; + } + try writer.writeAll("},"); + } + try writer.writeAll( + \\}; + \\} + \\ + \\pub fn dependencyCapabilities(self: Capability) []const Capability { + \\ return switch (self) { + ); + var by_name: std.StringHashMapUnmanaged(u31) = .empty; + for (enumerants) |enumerant| { + const value: u31 = switch (enumerant.value) { + .int => |value| value, + .bitflag => |value| try std.fmt.parseInt(u31, value, 10), + }; + try by_name.putNoClobber(arena, enumerant.enumerant, value); + for (enumerant.aliases) |alias| try by_name.putNoClobber(arena, alias, value); + } + for (enum_indices) |i| { + const enumerant = enumerants[i]; + try writer.print("\n.{f} => &.{{", .{formatId(enumerant.enumerant)}); + var comma = false; + for (enumerant.capabilities) |name| { + if (comma) try writer.writeAll(", "); + try writer.print(".{f}", .{formatId(enumerants[enum_map.get(by_name.get(name).?).?].enumerant)}); + comma = true; } try writer.writeAll("},"); } @@ -1057,6 +1086,7 @@ fn renderFieldName(writer: *std.Io.Writer, operands: []const Operand, field_inde } fn isAllowedCapability(name: []const u8) bool { + if (std.mem.find(u8, name, "Provisional") != null) return false; const last = name[name.len - 1]; if (std.ascii.isLower(last) or std.ascii.isDigit(last)) return true; for (allowed_vendors) |vendor| { @@ -1091,6 +1121,7 @@ fn isEnabled(version: ?[]const u8, capabilities: []const []const u8, extensions: fn keepEnabled(instructions: *[]Instruction, kinds: []OperandKind) void { var kept: usize = 0; for (instructions.*) |inst| { + if (inst.provisional) continue; if (!isEnabled(inst.version, inst.capabilities, inst.extensions)) continue; instructions.*[kept] = inst; kept += 1; @@ -1100,8 +1131,9 @@ fn keepEnabled(instructions: *[]Instruction, kinds: []OperandKind) void { const enumerants = kind.enumerants orelse continue; var kept_enumerants: usize = 0; for (enumerants) |enumerant| { + if (enumerant.provisional) continue; const enabled = if (std.mem.eql(u8, kind.kind, "Capability")) - isAllowedCapability(enumerant.enumerant) + isEnabled(enumerant.version, &.{}, enumerant.extensions) and std.mem.find(u8, enumerant.enumerant, "Provisional") == null else isEnabled(enumerant.version, enumerant.capabilities, enumerant.extensions); if (!enabled) continue; diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig index 5c9df210ea..a71bb6316e 100644 --- a/tools/update_cpu_features.zig +++ b/tools/update_cpu_features.zig @@ -64,35 +64,56 @@ const spirv_omitted_capabilities = [_][]const u8{ "shader", // implied by Vulkan/OpenGL targets "kernel", // implied by OpenCL/AMDHSA targets "addresses", // implied by OpenCL/AMDHSA targets + "matrix", // implied by shader "physical_storage_buffer_addresses", // implied by spirv64-vulkan "linkage", // automatically emitted when externs need linkage decorations }; const spirv_omitted_extensions = [_][]const u8{ "SPV_KHR_physical_storage_buffer", // paired with physical_storage_buffer_addresses + "SPV_EXT_physical_storage_buffer", }; +const spirv_no_deps_capabilities = [_][]const u8{ + "ray_traversal_primitive_culling_khr", +}; + +fn spirvOmitCapability(name: []const u8) bool { + for (spirv_omitted_capabilities) |omitted| { + if (std.mem.eql(u8, omitted, name)) return true; + } + return false; +} const spirv_extra_features: []const Feature = blk: { @setEvalBranchQuota(15_000); var features: []const Feature = &.{}; - cap: for ( + for ( @typeInfo(spirv_spec.Capability).@"enum".field_names, @typeInfo(spirv_spec.Capability).@"enum".field_values, ) |name, value| { - for (spirv_omitted_capabilities) |omitted| { - if (std.mem.eql(u8, omitted, name)) continue :cap; - } + if (spirvOmitCapability(name)) continue; + features = features ++ &[_]Feature{.{ .zig_name = name, .desc = "Enable " ++ name ++ " capability", - .deps = &struct { - const extensions = spirv_spec.Capability.dependencies(@fromBackingInt(@intCast(value))); - const deps: [extensions.len][]const u8 = inner: { - var out: [extensions.len][]const u8 = undefined; - for (extensions, 0..) |ext, i| out[i] = @tagName(ext); + .deps = struct { + const cap: spirv_spec.Capability = @fromBackingInt(@intCast(value)); + const deps: []const spirv_spec.Capability = for (spirv_no_deps_capabilities) |no_deps| { + if (std.mem.eql(u8, no_deps, name)) break &.{}; + } else cap.dependencyCapabilities(); + const result: []const []const u8 = inner: { + var out: []const []const u8 = &.{}; + for (cap.dependencyExtensions()) |ext| { + out = out ++ &[_][]const u8{@tagName(ext)}; + } + for (deps) |dep| { + if (spirvOmitCapability(@tagName(dep))) continue; + + out = out ++ &[_][]const u8{@tagName(dep)}; + } break :inner out; }; - }.deps, + }.result, }}; } @@ -113,8 +134,6 @@ const spirv_extra_features: []const Feature = blk: { &.{"v1_2"} else if (std.mem.eql(u8, name, "v1_2")) &.{"v1_1"} - else if (std.mem.eql(u8, name, "v1_1")) - &.{"v1_0"} else &.{}, }}; @@ -132,23 +151,303 @@ const targets = [_]ArchTarget{ }, .branch_quota = 2000, .feature_overrides = &.{ + .{ + .llvm_name = "aggressive-interleaving", + .omit = true, + }, .{ .llvm_name = "all", .omit = true, }, .{ - .llvm_name = "CONTEXTIDREL2", - .zig_name = "contextidr_el2", - .desc = "Enable RW operand Context ID Register (EL2)", + .llvm_name = "ascend-store-address", + .omit = true, }, .{ - .llvm_name = "hip12", - .flatten = true, + .llvm_name = "call-saved-x8", + .omit = true, + }, + .{ + .llvm_name = "call-saved-x9", + .omit = true, + }, + .{ + .llvm_name = "call-saved-x10", + .omit = true, + }, + .{ + .llvm_name = "call-saved-x11", + .omit = true, + }, + .{ + .llvm_name = "call-saved-x12", + .omit = true, + }, + .{ + .llvm_name = "call-saved-x13", + .omit = true, + }, + .{ + .llvm_name = "call-saved-x14", + .omit = true, + }, + .{ + .llvm_name = "call-saved-x15", + .omit = true, + }, + .{ + .llvm_name = "call-saved-x18", + .omit = true, + }, + .{ + .llvm_name = "disable-distinct-predicate-dst-reg", + .omit = true, + }, + .{ + .llvm_name = "disable-latency-sched-heuristic", + .omit = true, + }, + .{ + .llvm_name = "disable-ldp", + .omit = true, + }, + .{ + .llvm_name = "disable-maximize-scalable-bandwidth", + .omit = true, + }, + .{ + .llvm_name = "enable-select-opt", + .omit = true, + }, + .{ + .llvm_name = "disable-stp", + .omit = true, + }, + .{ + .llvm_name = "execute-only", + .omit = true, + }, + .{ + .llvm_name = "exynos-cheap-as-move", + .omit = true, + }, + .{ + .llvm_name = "fixed-load-latency-4", + .omit = true, + }, + .{ + .llvm_name = "fmv", + .omit = true, + }, + .{ + .llvm_name = "force-32bit-jump-tables", + .omit = true, + }, + .{ + .llvm_name = "harden-sls-blr", + .omit = true, + }, + .{ + .llvm_name = "harden-sls-nocomdat", + .omit = true, + }, + .{ + .llvm_name = "harden-sls-retbr", + .omit = true, + }, + .{ + .llvm_name = "max-interleave-factor-4", + .omit = true, }, .{ .llvm_name = "mca-streaming-sched", .omit = true, }, + .{ + .llvm_name = "no-bti-at-return-twice", + .omit = true, + }, + .{ + .llvm_name = "no-lfi-loads", + .omit = true, + }, + .{ + .llvm_name = "no-lfi-stores", + .omit = true, + }, + .{ + .llvm_name = "no-neg-immediates", + .omit = true, + }, + .{ + .llvm_name = "outline-atomics", + .omit = true, + }, + .{ + .llvm_name = "reserve-lr-for-ra", + .omit = true, + }, + .{ + .llvm_name = "reserve-x1", + .omit = true, + }, + .{ + .llvm_name = "reserve-x2", + .omit = true, + }, + .{ + .llvm_name = "reserve-x3", + .omit = true, + }, + .{ + .llvm_name = "reserve-x4", + .omit = true, + }, + .{ + .llvm_name = "reserve-x5", + .omit = true, + }, + .{ + .llvm_name = "reserve-x6", + .omit = true, + }, + .{ + .llvm_name = "reserve-x7", + .omit = true, + }, + .{ + .llvm_name = "reserve-x9", + .omit = true, + }, + .{ + .llvm_name = "reserve-x10", + .omit = true, + }, + .{ + .llvm_name = "reserve-x11", + .omit = true, + }, + .{ + .llvm_name = "reserve-x12", + .omit = true, + }, + .{ + .llvm_name = "reserve-x13", + .omit = true, + }, + .{ + .llvm_name = "reserve-x14", + .omit = true, + }, + .{ + .llvm_name = "reserve-x15", + .omit = true, + }, + .{ + .llvm_name = "reserve-x18", + .omit = true, + }, + .{ + .llvm_name = "reserve-x20", + .omit = true, + }, + .{ + .llvm_name = "reserve-x21", + .omit = true, + }, + .{ + .llvm_name = "reserve-x22", + .omit = true, + }, + .{ + .llvm_name = "reserve-x23", + .omit = true, + }, + .{ + .llvm_name = "reserve-x24", + .omit = true, + }, + .{ + .llvm_name = "reserve-x25", + .omit = true, + }, + .{ + .llvm_name = "reserve-x26", + .omit = true, + }, + .{ + .llvm_name = "reserve-x27", + .omit = true, + }, + .{ + .llvm_name = "reserve-x28", + .omit = true, + }, + .{ + .llvm_name = "reserve-x1", + .omit = true, + }, + .{ + .llvm_name = "reserve-x1", + .omit = true, + }, + .{ + .llvm_name = "reserve-x1", + .omit = true, + }, + .{ + .llvm_name = "reserve-x1", + .omit = true, + }, + .{ + .llvm_name = "reserve-x1", + .omit = true, + }, + .{ + .llvm_name = "reserve-x1", + .omit = true, + }, + .{ + .llvm_name = "store-pair-suppress", + .omit = true, + }, + .{ + .llvm_name = "tpidr-el1", + .omit = true, + }, + .{ + .llvm_name = "tpidr-el2", + .omit = true, + }, + .{ + .llvm_name = "tpidr-el3", + .omit = true, + }, + .{ + .llvm_name = "tpidrro-el0", + .omit = true, + }, + .{ + .llvm_name = "tagged-globals", + .omit = true, + }, + .{ + .llvm_name = "use-fixed-over-scalable-if-equal-cost", + .omit = true, + }, + .{ + .llvm_name = "use-postra-scheduler", + .omit = true, + }, + .{ + .llvm_name = "use-reciprocal-square-root", + .omit = true, + }, + + .{ + .llvm_name = "hip12", + .flatten = true, + }, .{ .llvm_name = "neoversee1", .flatten = true, @@ -197,6 +496,10 @@ const targets = [_]ArchTarget{ .llvm_name = "exynosm4", .flatten = true, }, + .{ + .llvm_name = "a320", + .flatten = true, + }, .{ .llvm_name = "a35", .flatten = true, @@ -397,10 +700,18 @@ const targets = [_]ArchTarget{ .llvm_name = "falkor", .flatten = true, }, + .{ + .llvm_name = "fujitsu-monaka", + .flatten = true, + }, .{ .llvm_name = "kryo", .flatten = true, }, + .{ + .llvm_name = "olympus", + .flatten = true, + }, .{ .llvm_name = "saphira", .flatten = true, @@ -416,6 +727,7 @@ const targets = [_]ArchTarget{ .{ .llvm_name = "thunderx3t110", .flatten = true, + .omit_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "thunderxt81", @@ -441,6 +753,22 @@ const targets = [_]ArchTarget{ .llvm_name = "ampere1b", .flatten = true, }, + + .{ + .llvm_name = "CONTEXTIDREL2", + .zig_name = "contextidr_el2", + .desc = "Enable RW operand Context ID Register (EL2)", + }, + .{ + .llvm_name = "strict-align", + .zig_name = "no_unaligned_access", + }, + + // Future ISA extensions; omit until they are stabilized. + .{ + .llvm_name = "use-experimental-zeroing-pseudos", + .omit = true, + }, }, .model_overrides = &.{ .{ @@ -449,43 +777,136 @@ const targets = [_]ArchTarget{ .llvm_name = "apple-latest", .omit = true, }, + .{ + .llvm_name = "generic", + .omit = true, + }, }, .extra_models = &.{ .{ - .llvm_name = null, + .llvm_name = "generic", + .zig_name = "armv8a", + .features = &.{"v8a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8r", + .features = &.{"v8r"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_1a", + .features = &.{"v8_1a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_2a", + .features = &.{"v8_2a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_3a", + .features = &.{"v8_3a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_4a", + .features = &.{"v8_4a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_5a", + .features = &.{"v8_5a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_6a", + .features = &.{"v8_6a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_7a", + .features = &.{"v8_7a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_8a", + .features = &.{"v8_8a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv8_9a", + .features = &.{"v8_9a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv9a", + .features = &.{"v9a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv9_1a", + .features = &.{"v9_1a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv9_2a", + .features = &.{"v9_2a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv9_3a", + .features = &.{"v9_3a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv9_4a", + .features = &.{"v9_4a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv9_5a", + .features = &.{"v9_5a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv9_6a", + .features = &.{"v9_6a"}, + }, + .{ + .llvm_name = "generic", + .zig_name = "armv9_7a", + .features = &.{"v9_7a"}, + }, + + .{ + .llvm_name = "generic", .zig_name = "exynos_m1", .features = &.{ "crc", "crypto", - "exynos_cheap_as_move", - "force_32bit_jump_tables", "fuse_aes", "perfmon", "slow_misaligned_128store", "slow_paired_128", - "use_postra_scheduler", - "use_reciprocal_square_root", "v8a", }, }, .{ - .llvm_name = null, + .llvm_name = "generic", .zig_name = "exynos_m2", .features = &.{ "crc", "crypto", - "exynos_cheap_as_move", - "force_32bit_jump_tables", "fuse_aes", "perfmon", "slow_misaligned_128store", "slow_paired_128", - "use_postra_scheduler", "v8a", }, }, .{ - .llvm_name = null, + .llvm_name = "generic", .zig_name = "xgene1", .features = &.{ "perfmon", @@ -493,7 +914,7 @@ const targets = [_]ArchTarget{ }, }, .{ - .llvm_name = null, + .llvm_name = "generic", .zig_name = "emag", .features = &.{ "crc", @@ -589,6 +1010,58 @@ const targets = [_]ArchTarget{ }, .branch_quota = 2000, .feature_overrides = &.{ + // The `zig_name`s on these are placeholders to avoid collision with + // the real features defined further below. + .{ + .llvm_name = "gfx9", + .zig_name = "__gfx9", + .flatten = true, + }, + .{ + .llvm_name = "gfx10", + .zig_name = "__gfx10", + .flatten = true, + }, + .{ + .llvm_name = "gfx11", + .zig_name = "__gfx11", + .flatten = true, + }, + .{ + .llvm_name = "gfx12", + .zig_name = "__gfx12", + .flatten = true, + }, + .{ + .llvm_name = "gfx13", + .zig_name = "__gfx13", + .flatten = true, + }, + .{ + .llvm_name = "sea-islands", + .flatten = true, + }, + .{ + .llvm_name = "southern-islands", + .flatten = true, + }, + .{ + .llvm_name = "volcanic-islands", + .flatten = true, + }, + + .{ + .llvm_name = "assembler-permissive-wavesize", + .omit = true, + }, + .{ + .llvm_name = "block-vgpr-csr", + .omit = true, + }, + .{ + .llvm_name = "cumode", + .omit = true, + }, .{ .llvm_name = "DumpCode", .omit = true, @@ -599,15 +1072,150 @@ const targets = [_]ArchTarget{ }, .{ .llvm_name = "enable-ds128", - .zig_name = "ds128", + .omit = true, }, .{ .llvm_name = "enable-flat-scratch", - .zig_name = "flat_scratch", + .omit = true, }, .{ .llvm_name = "enable-prt-strict-null", - .zig_name = "prt_strict_null", + .omit = true, + }, + .{ + .llvm_name = "flat-for-global", + .omit = true, + }, + .{ + .llvm_name = "fmaf", + .omit = true, + }, + .{ + .llvm_name = "load-store-opt", + .omit = true, + }, + .{ + .llvm_name = "max-private-element-size-4", + .omit = true, + }, + .{ + .llvm_name = "max-private-element-size-8", + .omit = true, + }, + .{ + .llvm_name = "max-private-element-size-16", + .omit = true, + }, + .{ + .llvm_name = "precise-memory", + .omit = true, + }, + .{ + .llvm_name = "real-true16", + .omit = true, + }, + .{ + .llvm_name = "si-scheduler", + .omit = true, + }, + .{ + .llvm_name = "sramecc", + .omit = true, + }, + .{ + .llvm_name = "trap-handler", + .omit = true, + }, + .{ + .llvm_name = "unaligned-access-mode", + .omit = true, + }, + .{ + .llvm_name = "unsafe-ds-offset-folding", + .omit = true, + }, + .{ + .llvm_name = "use-add-pc64-inst", + .omit = true, + }, + .{ + .llvm_name = "xnack", + .flatten = true, + }, + + .{ + .llvm_name = "ci-insts", + .zig_name = "gfx7", + }, + .{ + .llvm_name = "gfx8-insts", + .zig_name = "gfx8", + .extra_deps = &.{"gfx7"}, + }, + .{ + .llvm_name = "gfx9-insts", + .zig_name = "gfx9", + .extra_deps = &.{"gfx8"}, + }, + .{ + .llvm_name = "gfx90a-insts", + .zig_name = "gfx9_0a", + .extra_deps = &.{"gfx9"}, + }, + .{ + .llvm_name = "gfx940-insts", + .zig_name = "gfx9_4", + .extra_deps = &.{"gfx9_0a"}, + }, + .{ + .llvm_name = "gfx950-insts", + .zig_name = "gfx9_5", + .extra_deps = &.{"gfx9_4"}, + }, + .{ + .llvm_name = "gfx10-insts", + .zig_name = "gfx10", + .extra_deps = &.{"gfx9"}, + }, + .{ + .llvm_name = "gfx10-3-insts", + .zig_name = "gfx10_3", + .extra_deps = &.{"gfx10"}, + }, + .{ + .llvm_name = "gfx11-insts", + .zig_name = "gfx11", + .extra_deps = &.{"gfx10_3"}, + }, + .{ + .llvm_name = "gfx11-7-insts", + .zig_name = "gfx11_7", + .extra_deps = &.{"gfx11"}, + }, + .{ + .llvm_name = "gfx12-insts", + .zig_name = "gfx12", + .extra_deps = &.{"gfx11"}, + }, + .{ + .llvm_name = "gfx1250-insts", + .zig_name = "gfx12_5", + .extra_deps = &.{"gfx12"}, + }, + .{ + .llvm_name = "gfx13-insts", + .zig_name = "gfx13", + .extra_deps = &.{"gfx12"}, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + .{ + .llvm_name = "generic-hsa", + .omit = true, }, }, }, @@ -617,6 +1225,12 @@ const targets = [_]ArchTarget{ .name = "ARC", .td_name = "ARC", }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .zig_name = "arcv2", + }, + }, }, .{ .zig_name = "arm", @@ -706,6 +1320,10 @@ const targets = [_]ArchTarget{ .llvm_name = "cortex-a78ae", .flatten = true, }, + .{ + .llvm_name = "cortex-a510", + .flatten = true, + }, .{ .llvm_name = "cortex-a710", .flatten = true, @@ -738,6 +1356,14 @@ const targets = [_]ArchTarget{ .llvm_name = "m7", .flatten = true, }, + .{ + .llvm_name = "m55", + .flatten = true, + }, + .{ + .llvm_name = "m85", + .flatten = true, + }, .{ .llvm_name = "neoverse-v1", .flatten = true, @@ -767,50 +1393,131 @@ const targets = [_]ArchTarget{ .flatten = true, }, + .{ + .llvm_name = "32bit", + .omit = true, + }, + .{ + .llvm_name = "aapcs-frame-chain", + .omit = true, + }, + .{ + .llvm_name = "big-endian-instructions", + .omit = true, + }, + .{ + .llvm_name = "disable-postra-scheduler", + .omit = true, + }, + .{ + .llvm_name = "execute-only", + .omit = true, + }, + .{ + .llvm_name = "harden-sls-blr", + .omit = true, + }, + .{ + .llvm_name = "harden-sls-nocomdat", + .omit = true, + }, + .{ + .llvm_name = "harden-sls-retbr", + .omit = true, + }, + .{ + .llvm_name = "long-calls", + .omit = true, + }, + .{ + .llvm_name = "no-bti-at-return-twice", + .omit = true, + }, + .{ + .llvm_name = "no-movt", + .omit = true, + }, + .{ + .llvm_name = "no-neg-immediates", + .omit = true, + }, + .{ + .llvm_name = "read-tp-tpidrprw", + .omit = true, + }, + .{ + .llvm_name = "read-tp-tpidruro", + .omit = true, + }, + .{ + .llvm_name = "read-tp-tpidrurw", + .omit = true, + }, + .{ + .llvm_name = "reserve-r9", + .omit = true, + }, + .{ + .llvm_name = "soft-float", + .omit = true, + }, + .{ + .llvm_name = "thumb-mode", + .omit = true, + }, + .{ + .llvm_name = "use-mipipeliner", + .omit = true, + }, + .{ + .llvm_name = "use-misched", + .omit = true, + }, + .{ .llvm_name = "armv2", .zig_name = "v2", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv2a", .zig_name = "v2a", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv3", .zig_name = "v3", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv3m", .zig_name = "v3m", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv4", .zig_name = "v4", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv4t", .zig_name = "v4t", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv5t", .zig_name = "v5t", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv5te", .zig_name = "v5te", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv5tej", .zig_name = "v5tej", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv6", @@ -972,6 +1679,10 @@ const targets = [_]ArchTarget{ .llvm_name = "armv9-a", .zig_name = "v9a", }, + .{ + .llvm_name = "strict-align", + .zig_name = "no_unaligned_access", + }, .{ .llvm_name = "v4t", .zig_name = "has_v4t", @@ -1098,22 +1809,22 @@ const targets = [_]ArchTarget{ .{ .zig_name = "v2", .desc = "ARMv2 architecture", - .deps = &.{"strict_align"}, + .deps = &.{"no_unaligned_access"}, }, .{ .zig_name = "v2a", .desc = "ARMv2a architecture", - .deps = &.{"strict_align"}, + .deps = &.{"no_unaligned_access"}, }, .{ .zig_name = "v3", .desc = "ARMv3 architecture", - .deps = &.{"strict_align"}, + .deps = &.{"no_unaligned_access"}, }, .{ .zig_name = "v3m", .desc = "ARMv3m architecture", - .deps = &.{"strict_align"}, + .deps = &.{"no_unaligned_access"}, }, }, .model_overrides = &.{ @@ -1278,12 +1989,12 @@ const targets = [_]ArchTarget{ .features = &.{ "v7a", "vfp3d16" }, }, .{ - .llvm_name = null, + .llvm_name = "generic", .zig_name = "exynos_m1", .features = &.{ "v8a", "exynos" }, }, .{ - .llvm_name = null, + .llvm_name = "generic", .zig_name = "exynos_m2", .features = &.{ "v8a", "exynos" }, }, @@ -1315,6 +2026,12 @@ const targets = [_]ArchTarget{ .name = "AVR", .td_name = "AVR", }, + .feature_overrides = &.{ + .{ + .llvm_name = "special", + .omit = true, + }, + }, }, .{ .zig_name = "bpf", @@ -1331,6 +2048,21 @@ const targets = [_]ArchTarget{ .llvm_name = "dwarfris", .omit = true, }, + + .{ + .llvm_name = "allows-misaligned-mem-access", + .zig_name = "unaligned_access", + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + .{ + .llvm_name = "probe", + .omit = true, + }, }, }, .{ @@ -1348,6 +2080,18 @@ const targets = [_]ArchTarget{ .llvm_name = "constpool", .omit = true, }, + .{ + .llvm_name = "hard-float", + .omit = true, + }, + .{ + .llvm_name = "hard-float-abi", + .omit = true, + }, + .{ + .llvm_name = "hard-tp", + .omit = true, + }, .{ .llvm_name = "multiple_stld", .omit = true, @@ -1365,11 +2109,11 @@ const targets = [_]ArchTarget{ .omit = true, }, .{ - .llvm_name = "soft_tp", + .llvm_name = "soft-tp", .omit = true, }, .{ - .llvm_name = "stack_size", + .llvm_name = "stack-size", .omit = true, }, @@ -1418,6 +2162,19 @@ const targets = [_]ArchTarget{ .flatten = true, }, }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "e2", + .features = &.{"e2"}, + }, + }, }, .{ .zig_name = "hexagon", @@ -1425,6 +2182,251 @@ const targets = [_]ArchTarget{ .name = "Hexagon", .td_name = "Hexagon", }, + .feature_overrides = &.{ + .{ + .llvm_name = "compound", + .omit = true, + }, + .{ + .llvm_name = "duplex", + .omit = true, + }, + .{ + .llvm_name = "long-calls", + .omit = true, + }, + .{ + .llvm_name = "memops", + .omit = true, + }, + .{ + .llvm_name = "noreturn-stack-elim", + .omit = true, + }, + .{ + .llvm_name = "nvj", + .omit = true, + }, + .{ + .llvm_name = "nvs", + .omit = true, + }, + .{ + .llvm_name = "packets", + .omit = true, + }, + .{ + .llvm_name = "reserved-r6", + .omit = true, + }, + .{ + .llvm_name = "reserved-r7", + .omit = true, + }, + .{ + .llvm_name = "reserved-r8", + .omit = true, + }, + .{ + .llvm_name = "reserved-r9", + .omit = true, + }, + .{ + .llvm_name = "reserved-r10", + .omit = true, + }, + .{ + .llvm_name = "reserved-r11", + .omit = true, + }, + .{ + .llvm_name = "reserved-r12", + .omit = true, + }, + .{ + .llvm_name = "reserved-r13", + .omit = true, + }, + .{ + .llvm_name = "reserved-r14", + .omit = true, + }, + .{ + .llvm_name = "reserved-r15", + .omit = true, + }, + .{ + .llvm_name = "reserved-r16", + .omit = true, + }, + .{ + .llvm_name = "reserved-r17", + .omit = true, + }, + .{ + .llvm_name = "reserved-r18", + .omit = true, + }, + .{ + .llvm_name = "reserved-r19", + .omit = true, + }, + .{ + .llvm_name = "reserved-r20", + .omit = true, + }, + .{ + .llvm_name = "reserved-r21", + .omit = true, + }, + .{ + .llvm_name = "reserved-r22", + .omit = true, + }, + .{ + .llvm_name = "reserved-r23", + .omit = true, + }, + .{ + .llvm_name = "reserved-r24", + .omit = true, + }, + .{ + .llvm_name = "reserved-r25", + .omit = true, + }, + .{ + .llvm_name = "reserved-r26", + .omit = true, + }, + .{ + .llvm_name = "reserved-r27", + .omit = true, + }, + .{ + .llvm_name = "reserved-r28", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r16", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r17", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r18", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r19", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r20", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r21", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r22", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r23", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r24", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r25", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r26", + .omit = true, + }, + .{ + .llvm_name = "scs-reg-r27", + .omit = true, + }, + .{ + .llvm_name = "small-data", + .omit = true, + }, + + .{ + .llvm_name = "hvx-ieee-fp", + .extra_deps = &.{"hvxv68"}, + }, + .{ + .llvm_name = "hvx-qfloat", + .extra_deps = &.{"hvxv68"}, + }, + .{ + .llvm_name = "v55", + .extra_deps = &.{"v5"}, + }, + .{ + .llvm_name = "v60", + .extra_deps = &.{"v55"}, + }, + .{ + .llvm_name = "v62", + .extra_deps = &.{"v60"}, + }, + .{ + .llvm_name = "v65", + .extra_deps = &.{"v62"}, + }, + .{ + .llvm_name = "v66", + .extra_deps = &.{"v65"}, + }, + .{ + .llvm_name = "v67", + .extra_deps = &.{"v66"}, + }, + .{ + .llvm_name = "v68", + .extra_deps = &.{"v67"}, + }, + .{ + .llvm_name = "v69", + .extra_deps = &.{"v68"}, + }, + .{ + .llvm_name = "v71", + .extra_deps = &.{"v69"}, + }, + .{ + .llvm_name = "v73", + .extra_deps = &.{"v71"}, + }, + .{ + .llvm_name = "v75", + .extra_deps = &.{"v73"}, + }, + .{ + .llvm_name = "v79", + .extra_deps = &.{"v75"}, + }, + .{ + .llvm_name = "v81", + .extra_deps = &.{"v79"}, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + }, }, .{ .zig_name = "hppa", @@ -1610,6 +2612,12 @@ const targets = [_]ArchTarget{ .name = "Lanai", .td_name = "Lanai", }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + }, }, .{ .zig_name = "loongarch", @@ -1617,11 +2625,42 @@ const targets = [_]ArchTarget{ .name = "LoongArch", .td_name = "LoongArch", }, + .feature_overrides = &.{ + .{ + .llvm_name = "la-global-with-abs", + .omit = true, + }, + .{ + .llvm_name = "la-global-with-pcrel", + .omit = true, + }, + .{ + .llvm_name = "la-local-with-abs", + .omit = true, + }, + .{ + .llvm_name = "prefer-w-inst", + .omit = true, + }, + .{ + .llvm_name = "relax", + .omit = true, + }, + + .{ + .llvm_name = "ual", + .zig_name = "unaligned_access", + }, + }, .model_overrides = &.{ .{ .llvm_name = "generic", .omit = true, }, + .{ + .llvm_name = "generic-la32", + .omit = true, + }, .{ .llvm_name = "generic-la64", .omit = true, @@ -1636,6 +2675,13 @@ const targets = [_]ArchTarget{ }, }, .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "generic_la32", + .features = &.{ + "32bit", + }, + }, .{ .llvm_name = null, .zig_name = "generic_la64", @@ -1650,7 +2696,7 @@ const targets = [_]ArchTarget{ "32bit", "32s", "d", - "ual", + "unaligned_access", }, }, .{ @@ -1658,7 +2704,7 @@ const targets = [_]ArchTarget{ .zig_name = "la32rv1_0", .features = &.{ "32bit", - "ual", + "unaligned_access", }, }, .{ @@ -1667,7 +2713,7 @@ const targets = [_]ArchTarget{ .features = &.{ "64bit", "lsx", - "ual", + "unaligned_access", }, }, .{ @@ -1682,7 +2728,15 @@ const targets = [_]ArchTarget{ "ld_seq_sa", "lsx", "scq", - "ual", + "unaligned_access", + }, + }, + .{ + .llvm_name = null, + .zig_name = "la132", + .features = &.{ + "32bit", + "32s", }, }, }, @@ -1693,6 +2747,414 @@ const targets = [_]ArchTarget{ .name = "M68k", .td_name = "M68k", }, + .feature_overrides = &.{ + .{ + .llvm_name = "reserve-a0", + .omit = true, + }, + .{ + .llvm_name = "reserve-a1", + .omit = true, + }, + .{ + .llvm_name = "reserve-a2", + .omit = true, + }, + .{ + .llvm_name = "reserve-a3", + .omit = true, + }, + .{ + .llvm_name = "reserve-a4", + .omit = true, + }, + .{ + .llvm_name = "reserve-a5", + .omit = true, + }, + .{ + .llvm_name = "reserve-a6", + .omit = true, + }, + .{ + .llvm_name = "reserve-d0", + .omit = true, + }, + .{ + .llvm_name = "reserve-d1", + .omit = true, + }, + .{ + .llvm_name = "reserve-d2", + .omit = true, + }, + .{ + .llvm_name = "reserve-d3", + .omit = true, + }, + .{ + .llvm_name = "reserve-d4", + .omit = true, + }, + .{ + .llvm_name = "reserve-d5", + .omit = true, + }, + .{ + .llvm_name = "reserve-d6", + .omit = true, + }, + .{ + .llvm_name = "reserve-d7", + .omit = true, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + + .{ + .llvm_name = "M68000", + .zig_name = "m68000", + }, + .{ + .llvm_name = "M68010", + .zig_name = "m68010", + }, + .{ + .llvm_name = "M68020", + .zig_name = "m68020", + .extra_deps = &.{"isa_68881"}, + }, + .{ + .llvm_name = "M68030", + .zig_name = "m68030", + .extra_deps = &.{"isa_68881"}, + }, + .{ + .llvm_name = "M68040", + .zig_name = "m68040", + }, + .{ + .llvm_name = "M68060", + .zig_name = "m68060", + }, + }, + }, + .{ + .zig_name = "m88k", + .llvm = null, + .extra_features = &.{ + .{ + .zig_name = "isa_88110", + .desc = "Enable MC88110 additions to the base instruction set", + .deps = &.{}, + }, + .{ + .zig_name = "sfu1", + .desc = "Enable floating-point unit", + .deps = &.{}, + }, + .{ + .zig_name = "sfu2", + .desc = "Enable graphics unit", + .deps = &.{}, + }, + .{ + .zig_name = "xmem_imm", + .desc = "Enable xmem with 16-bit immediate offset", + .deps = &.{}, + }, + .{ + .zig_name = "xrf", + .desc = "Enable extended register file", + .deps = &.{"sfu1"}, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "m88000", + .features = &.{ + "sfu1", + }, + }, + .{ + .llvm_name = null, + .zig_name = "m88100", + .features = &.{ + "sfu1", + "xmem_imm", + }, + }, + .{ + .llvm_name = null, + .zig_name = "m88110", + .features = &.{ + "sfu1", + "sfu2", + "xrf", + }, + }, + }, + }, + .{ + .zig_name = "microblaze", + .llvm = null, + .extra_features = &.{ + .{ + .zig_name = "barrel", + .desc = "Enable barrel shift instructions (C_USE_BARREL)", + .deps = &.{}, + }, + .{ + .zig_name = "div", + .desc = "Enable hardware divide instructions (C_USE_DIV)", + .deps = &.{}, + }, + .{ + .zig_name = "fpu", + .desc = "Enable single-precision floating point instructions (C_USE_FPU >= 1)", + .deps = &.{}, + }, + .{ + .zig_name = "fpu2", + .desc = "Enable floating point conversion and square root instructions (C_USE_FPU = 2)", + .deps = &.{"fpu"}, + }, + .{ + .zig_name = "msr", + .desc = "Enable msrset and msrclr instructions (C_USE_MSR_INSTR)", + .deps = &.{}, + }, + .{ + .zig_name = "mul", + .desc = "Enable 32-bit multiply instructions (C_USE_HW_MUL >= 1)", + .deps = &.{}, + }, + .{ + .zig_name = "mul64", + .desc = "Enable multiply high instructions (C_USE_HW_MUL = 2)", + .deps = &.{"mul"}, + }, + .{ + .zig_name = "pcmp", + .desc = "Enable pattern compare instructions, and clz with v8.10 (C_USE_PCMP_INSTR)", + .deps = &.{}, + }, + .{ + .zig_name = "pipe3", + .desc = "Tune for the 3-stage pipeline (C_AREA_OPTIMIZED = 1)", + .deps = &.{}, + }, + .{ + .zig_name = "pipe8", + .desc = "Tune for the 8-stage pipeline (C_AREA_OPTIMIZED = 2)", + .deps = &.{}, + }, + .{ + .zig_name = "reorder", + .desc = "Enable byte-reversed load/store instructions, and swapb and swaph with v8.30 (C_USE_REORDER_INSTR)", + .deps = &.{}, + }, + .{ + .zig_name = "v7_20", + .desc = "Enable MicroBlaze v7.20 instructions (lwx, swx)", + .deps = &.{}, + }, + .{ + .zig_name = "v8_10", + .desc = "Enable MicroBlaze v8.10 instructions (mbar)", + .deps = &.{"v7_20"}, + }, + .{ + .zig_name = "v8_30", + .desc = "Enable MicroBlaze v8.30 instructions (swapb and swaph with reorder)", + .deps = &.{"v8_10"}, + }, + .{ + .zig_name = "v10_0", + .desc = "Enable MicroBlaze v10.0 instructions (bsefi and bsifi with barrel)", + .deps = &.{"v8_30"}, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "v2_00", + .features = &.{ + "pipe3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v2_10", + .features = &.{ + "pipe3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v3_00", + .features = &.{ + "pipe3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v4_00", + .features = &.{ + "pipe3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v5_00", + .features = &.{ + "msr", + "pcmp", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v6_00", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "v7_00", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "v7_10", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "v7_20", + .features = &.{ + "v7_20", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v7_30", + .features = &.{ + "v7_20", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_00", + .features = &.{ + "reorder", + "v7_20", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_10", + .features = &.{ + "reorder", + "v8_10", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_20", + .features = &.{ + "reorder", + "v8_10", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_30", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_40", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_50", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_0", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_1", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_2", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_3", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_4", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_5", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_6", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v10_0", + .features = &.{ + "v10_0", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v11_0", + .features = &.{ + "v10_0", + }, + }, + }, }, .{ .zig_name = "msp430", @@ -1700,6 +3162,18 @@ const targets = [_]ArchTarget{ .name = "MSP430", .td_name = "MSP430", }, + .feature_overrides = &.{ + .{ + .llvm_name = "hwmult32", + .extra_deps = &.{"hwmult16"}, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + }, }, .{ .zig_name = "mips", @@ -1707,27 +3181,112 @@ const targets = [_]ArchTarget{ .name = "Mips", .td_name = "Mips", }, - .extra_features = &.{ + .feature_overrides = &.{ .{ - .zig_name = "notraps", - .desc = "Disable trap instructions", - .deps = &.{}, + .llvm_name = "i6400", + .flatten = true, + }, + .{ + .llvm_name = "i6500", + .flatten = true, + }, + .{ + .llvm_name = "p5600", + .flatten = true, + }, + + .{ + .llvm_name = "fp64", + .omit = true, + }, + .{ + .llvm_name = "fpxx", + .omit = true, + }, + .{ + .llvm_name = "gp64", + .omit = true, + }, + .{ + .llvm_name = "long-calls", + .omit = true, + }, + .{ + .llvm_name = "micromips", + .omit = true, + }, + .{ + .llvm_name = "mips16", + .omit = true, + }, + .{ + .llvm_name = "noabicalls", + .omit = true, + }, + .{ + .llvm_name = "nooddspreg", + .omit = true, + }, + .{ + .llvm_name = "ptr64", + .omit = true, + }, + .{ + .llvm_name = "soft-float", + .omit = true, + }, + .{ + .llvm_name = "sym32", + .omit = true, + }, + .{ + .llvm_name = "use-compact-branches", + .omit = true, + }, + .{ + .llvm_name = "use-indirect-jump-hazard", + .omit = true, + }, + .{ + .llvm_name = "use-tcc-in-div", + .omit = true, + }, + .{ + .llvm_name = "xgot", + .omit = true, + }, + + .{ + .llvm_name = "strict-align", + .zig_name = "no_unaligned_access", + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + .{ + .llvm_name = "mips5", + .omit = true, }, }, .extra_models = &.{ .{ - .llvm_name = null, + .llvm_name = "mips1", .zig_name = "r3000a", .features = &.{ "mips1", - "soft_float", - "notraps", }, }, .{ - .llvm_name = null, + .llvm_name = "mips2", .zig_name = "allegrex", - .features = &.{ "mips2", "single_float", "notraps" }, + .features = &.{ + "mips2", + "single_float", + "vfpu", + }, }, }, }, @@ -1738,6 +3297,202 @@ const targets = [_]ArchTarget{ .td_name = "NVPTX", }, }, + .{ + .zig_name = "or1k", + .llvm = null, + .extra_features = &.{ + .{ + .zig_name = "adrp", + .desc = "Enable PC-relative page address instruction (l.adrp)", + .deps = &.{}, + }, + .{ + .zig_name = "atomic", + .desc = "Enable load-linked/store-conditional instructions (l.lwa, l.swa)", + .deps = &.{}, + }, + .{ + .zig_name = "cmov", + .desc = "Enable conditional move instruction (l.cmov)", + .deps = &.{}, + }, + .{ + .zig_name = "csync", + .desc = "Enable context synchronization instruction (l.csync)", + .deps = &.{}, + }, + .{ + .zig_name = "div", + .desc = "Enable hardware divide instructions (l.div, l.divu)", + .deps = &.{}, + }, + .{ + .zig_name = "ext", + .desc = "Enable sign/zero extension instructions (l.extbs, l.extbz, l.exths, l.exthz, l.extws, l.extwz)", + .deps = &.{}, + }, + .{ + .zig_name = "ff1", + .desc = "Enable find first 1 instruction (l.ff1)", + .deps = &.{}, + }, + .{ + .zig_name = "fl1", + .desc = "Enable find last 1 instruction (l.fl1)", + .deps = &.{}, + }, + .{ + .zig_name = "mac", + .desc = "Enable multiply-accumulate instructions (l.mac, l.maci, l.macrc, l.macu, l.msb, l.msbu)", + .deps = &.{}, + }, + .{ + .zig_name = "madd_s", + .desc = "Enable single-precision floating point multiply-add instruction (lf.madd.s)", + .deps = &.{"orfpx32"}, + }, + .{ + .zig_name = "madd_d", + .desc = "Enable double-precision floating point multiply-add instruction (lf.madd.d)", + .deps = &.{"orfpx64a32"}, + }, + .{ + .zig_name = "msync", + .desc = "Enable memory synchronization instruction (l.msync)", + .deps = &.{}, + }, + .{ + .zig_name = "mul", + .desc = "Enable hardware multiply instructions (l.mul, l.muli, l.mulu)", + .deps = &.{}, + }, + .{ + .zig_name = "muld", + .desc = "Enable widening multiply instructions (l.muld, l.muldu)", + .deps = &.{}, + }, + .{ + .zig_name = "no_addc", + .desc = "Disable add with carry instructions (l.addc, l.addic)", + .deps = &.{}, + }, + .{ + .zig_name = "no_sr_cy", + .desc = "Disable carry flag (SR[CY]) updates", + .deps = &.{"no_addc"}, + }, + .{ + .zig_name = "no_sr_ov", + .desc = "Disable overflow flag (SR[OV]) updates", + .deps = &.{}, + }, + .{ + .zig_name = "no_sra", + .desc = "Disable arithmetic shift right instructions (l.sra, l.srai)", + .deps = &.{}, + }, + .{ + .zig_name = "orfpx32", + .desc = "Enable single-precision floating point instructions", + .deps = &.{}, + }, + .{ + .zig_name = "orfpx64a32", + .desc = "Enable double-precision floating point instructions on register pairs", + .deps = &.{ "orfpx32", "sfun_s" }, + }, + .{ + .zig_name = "psync", + .desc = "Enable pipeline synchronization instruction (l.psync)", + .deps = &.{}, + }, + .{ + .zig_name = "ror", + .desc = "Enable rotate right instructions (l.ror, l.rori)", + .deps = &.{}, + }, + .{ + .zig_name = "sfimm", + .desc = "Enable set flag with immediate instructions (l.sfeqi, l.sfnei, l.sfgtsi, l.sfgtui, l.sfgesi, l.sfgeui, l.sfltsi, l.sfltui, l.sflesi, l.sfleui)", + .deps = &.{}, + }, + .{ + .zig_name = "sfun_s", + .desc = "Enable unordered single-precision floating point comparison instructions (lf.sfueq.s, lf.sfune.s, lf.sfugt.s, lf.sfuge.s, lf.sfult.s, lf.sfule.s, lf.sfun.s)", + .deps = &.{"orfpx32"}, + }, + .{ + .zig_name = "stod_dtos", + .desc = "Enable floating point precision conversion instructions (lf.stod.d, lf.dtos.d)", + .deps = &.{"orfpx64a32"}, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "ar100", + .features = &.{ + "csync", + "ff1", + "msync", + "psync", + "sfimm", + }, + }, + .{ + .llvm_name = null, + .zig_name = "marocchino", + .features = &.{ + "atomic", + "cmov", + "div", + "ext", + "ff1", + "fl1", + "msync", + "mul", + "orfpx64a32", + "ror", + "sfimm", + }, + }, + .{ + .llvm_name = null, + .zig_name = "mor1kx", + .features = &.{ + "atomic", + "cmov", + "div", + "ff1", + "fl1", + "msync", + "mul", + "sfimm", + }, + }, + .{ + .llvm_name = null, + .zig_name = "or1200", + .features = &.{ + "cmov", + "csync", + "div", + "ext", + "ff1", + "fl1", + "msync", + "mul", + "psync", + "sfimm", + }, + }, + .{ + .llvm_name = null, + .zig_name = "orbis32", + .features = &.{}, + }, + }, + }, .{ .zig_name = "powerpc", .llvm = .{ @@ -1745,6 +3500,27 @@ const targets = [_]ArchTarget{ .td_name = "PPC", }, .feature_overrides = &.{ + .{ + .llvm_name = "e500", + .flatten = true, + }, + .{ + .llvm_name = "ppc4xx", + .flatten = true, + }, + .{ + .llvm_name = "ppc6xx", + .flatten = true, + }, + + .{ + .llvm_name = "64bit", + .omit = true, + }, + .{ + .llvm_name = "64bitregs", + .omit = true, + }, .{ .llvm_name = "aix", .omit = true, @@ -1761,23 +3537,96 @@ const targets = [_]ArchTarget{ .llvm_name = "aix-small-local-exec-tls", .omit = true, }, + .{ + .llvm_name = "crbits", + .omit = true, + }, + .{ + .llvm_name = "hard-float", + .omit = true, + }, + .{ + .llvm_name = "invariant-function-descriptors", + .omit = true, + }, + .{ + .llvm_name = "longcall", + .omit = true, + }, .{ .llvm_name = "modern-aix-as", .omit = true, }, + .{ + .llvm_name = "ppc-postra-sched", + .omit = true, + }, + .{ + .llvm_name = "ppc-prera-sched", + .omit = true, + }, + .{ + .llvm_name = "privileged", + .omit = true, + }, + .{ + .llvm_name = "rop-protect", + .omit = true, + }, + .{ + .llvm_name = "secure-plt", + .omit = true, + }, + .{ + .llvm_name = "use-ptrgl-helper", + .omit = true, + }, + + // Future ISA extensions; omit until they are stabilized. + .{ + .llvm_name = "future-vector", + .omit = true, + }, + .{ + .llvm_name = "isa-future-instructions", + .omit = true, + }, + + .{ + .llvm_name = "64bit-support", + .zig_name = "64bit", + }, + .{ + .llvm_name = "fast-MFLR", + .zig_name = "fast_mflr", + }, + .{ + .llvm_name = "allow-unaligned-fp-access", + .zig_name = "unaligned_fp_access", + }, }, .model_overrides = &.{ .{ - .llvm_name = "ppc32", + .llvm_name = "generic", + .omit = true, + }, + .{ + .llvm_name = "ppc", + .omit = true, + }, + + // Future ISA extensions; omit until they are stabilized. + .{ + .llvm_name = "future", .omit = true, }, }, .extra_models = &.{ .{ - .llvm_name = null, + .llvm_name = "970", .zig_name = "cell", .features = &.{ - "64bit_support", + "64bit", "altivec", "fres", "frsqrte", @@ -1787,23 +3636,20 @@ const targets = [_]ArchTarget{ }, }, .{ - .llvm_name = null, - .zig_name = "e500v2", - .features = &.{ - "efpu2", - "isel", - "msync", - }, - }, - .{ - .llvm_name = null, + .llvm_name = "e5500", .zig_name = "e6500", .features = &.{ - "64bit_support", + "64bit", "altivec", "booke", + "bpermd", + "cmpb", + "fres", + "frsqrte", "isel", "mfocrf", + "partword_atomics", + "popcntd", "stfiwx", }, }, @@ -1840,7 +3686,78 @@ const targets = [_]ArchTarget{ }, .branch_quota = 2000, .extra_features = spirv_extra_features, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + }, .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "v1_0", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "v1_1", + .features = &.{"v1_1"}, + }, + .{ + .llvm_name = null, + .zig_name = "v1_2", + .features = &.{"v1_2"}, + }, + .{ + .llvm_name = null, + .zig_name = "v1_3", + .features = &.{"v1_3"}, + }, + .{ + .llvm_name = null, + .zig_name = "v1_4", + .features = &.{"v1_4"}, + }, + .{ + .llvm_name = null, + .zig_name = "v1_5", + .features = &.{"v1_5"}, + }, + .{ + .llvm_name = null, + .zig_name = "v1_6", + .features = &.{"v1_6"}, + }, + .{ + .llvm_name = null, + .zig_name = "opencl_v2_1", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "opencl_v2_2", + .features = &.{"v1_2"}, + }, + .{ + .llvm_name = null, + .zig_name = "opencl_v3_1", + .features = &.{"v1_4"}, + }, + .{ + .llvm_name = null, + .zig_name = "opengl_v4_6", + .features = &.{"v1_4"}, + }, + .{ + .llvm_name = null, + .zig_name = "vulkan_v1_0", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "vulkan_v1_1", + .features = &.{"v1_3"}, + }, .{ .llvm_name = null, .zig_name = "vulkan_v1_2", @@ -1848,8 +3765,13 @@ const targets = [_]ArchTarget{ }, .{ .llvm_name = null, - .zig_name = "opencl_v2", - .features = &.{"v1_2"}, + .zig_name = "vulkan_v1_3", + .features = &.{"v1_6"}, + }, + .{ + .llvm_name = null, + .zig_name = "vulkan_v1_4", + .features = &.{"v1_6"}, }, }, }, @@ -1861,21 +3783,746 @@ const targets = [_]ArchTarget{ }, .branch_quota = 2000, .feature_overrides = &.{ + .{ + .llvm_name = "rva20s64", + .flatten = true, + }, + .{ + .llvm_name = "rva20u64", + .flatten = true, + }, + .{ + .llvm_name = "rva22s64", + .flatten = true, + }, + .{ + .llvm_name = "rva22u64", + .flatten = true, + }, + .{ + .llvm_name = "rva23s64", + .flatten = true, + }, + .{ + .llvm_name = "rva23u64", + .flatten = true, + }, + .{ + .llvm_name = "rvb23s64", + .flatten = true, + }, + .{ + .llvm_name = "rvb23u64", + .flatten = true, + }, + .{ + .llvm_name = "rvi20u32", + .flatten = true, + }, + .{ + .llvm_name = "rvi20u64", + .flatten = true, + }, + .{ + .llvm_name = "andes45", + .flatten = true, + }, + .{ + .llvm_name = "mips-p8700", + .flatten = true, + }, .{ .llvm_name = "sifive7", .flatten = true, }, + .{ + .llvm_name = "ventana-veyron", + .flatten = true, + }, + + .{ + .llvm_name = "exact-asm", + .omit = true, + }, + .{ + .llvm_name = "disable-latency-sched-heuristic", + .omit = true, + }, + .{ + .llvm_name = "disable-misched-load-clustering", + .omit = true, + }, + .{ + .llvm_name = "disable-misched-store-clustering", + .omit = true, + }, + .{ + .llvm_name = "disable-postmisched-load-clustering", + .omit = true, + }, + .{ + .llvm_name = "disable-postmisched-store-clustering", + .omit = true, + }, + .{ + .llvm_name = "enable-select-opt", + .omit = true, + }, + .{ + .llvm_name = "enable-vsetvli-sched-heuristic", + .omit = true, + }, + .{ + .llvm_name = "forced-atomics", + .omit = true, + }, + .{ + .llvm_name = "no-default-unroll", + .omit = true, + }, + .{ + .llvm_name = "no-trailing-seq-cst-fence", + .omit = true, + }, + .{ + .llvm_name = "relax", + .omit = true, + }, + .{ + .llvm_name = "reserve-x1", + .omit = true, + }, + .{ + .llvm_name = "reserve-x2", + .omit = true, + }, + .{ + .llvm_name = "reserve-x3", + .omit = true, + }, + .{ + .llvm_name = "reserve-x4", + .omit = true, + }, + .{ + .llvm_name = "reserve-x5", + .omit = true, + }, + .{ + .llvm_name = "reserve-x6", + .omit = true, + }, + .{ + .llvm_name = "reserve-x7", + .omit = true, + }, + .{ + .llvm_name = "reserve-x8", + .omit = true, + }, + .{ + .llvm_name = "reserve-x9", + .omit = true, + }, + .{ + .llvm_name = "reserve-x10", + .omit = true, + }, + .{ + .llvm_name = "reserve-x11", + .omit = true, + }, + .{ + .llvm_name = "reserve-x12", + .omit = true, + }, + .{ + .llvm_name = "reserve-x13", + .omit = true, + }, + .{ + .llvm_name = "reserve-x14", + .omit = true, + }, + .{ + .llvm_name = "reserve-x15", + .omit = true, + }, + .{ + .llvm_name = "reserve-x16", + .omit = true, + }, + .{ + .llvm_name = "reserve-x17", + .omit = true, + }, + .{ + .llvm_name = "reserve-x18", + .omit = true, + }, + .{ + .llvm_name = "reserve-x19", + .omit = true, + }, + .{ + .llvm_name = "reserve-x20", + .omit = true, + }, + .{ + .llvm_name = "reserve-x21", + .omit = true, + }, + .{ + .llvm_name = "reserve-x22", + .omit = true, + }, + .{ + .llvm_name = "reserve-x23", + .omit = true, + }, + .{ + .llvm_name = "reserve-x24", + .omit = true, + }, + .{ + .llvm_name = "reserve-x25", + .omit = true, + }, + .{ + .llvm_name = "reserve-x26", + .omit = true, + }, + .{ + .llvm_name = "reserve-x27", + .omit = true, + }, + .{ + .llvm_name = "reserve-x28", + .omit = true, + }, + .{ + .llvm_name = "reserve-x29", + .omit = true, + }, + .{ + .llvm_name = "reserve-x30", + .omit = true, + }, + .{ + .llvm_name = "reserve-x31", + .omit = true, + }, + .{ + .llvm_name = "save-restore", + .omit = true, + }, + .{ + .llvm_name = "tagged-globals", + .omit = true, + }, + .{ + .llvm_name = "use-postra-scheduler", + .omit = true, + }, + .{ + .llvm_name = "xcheriot", + .omit = true, + }, + + // Future ISA extensions; omit until they are stabilized. + .{ + .llvm_name = "experimental", + .omit = true, + }, + .{ + .llvm_name = "experimental-p", + .omit = true, + }, + .{ + .llvm_name = "experimental-rvm23u32", + .omit = true, + }, + .{ + .llvm_name = "experimental-smpmpmt", + .omit = true, + }, + .{ + .llvm_name = "experimental-svukte", + .omit = true, + }, + .{ + .llvm_name = "experimental-xqccmt", + .omit = true, + }, + .{ + .llvm_name = "experimental-xsfmclic", + .omit = true, + }, + .{ + .llvm_name = "experimental-xsfsclic", + .omit = true, + }, + .{ + .llvm_name = "experimental-y", + .omit = true, + }, + .{ + .llvm_name = "experimental-zibi", + .omit = true, + }, + .{ + .llvm_name = "experimental-zicfilp", + .omit = true, + }, + .{ + .llvm_name = "experimental-zicfiss", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvabd", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvbc32e", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvdot4a8i", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvfbdota32f", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvfbfa", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvfofp8min", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvfqwbdota8f", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvfqwdota8f", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvfwbdota16bf", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvfwdota16bf", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvkgs", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvqwbdota16i", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvqwbdota8i", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvqwdota16i", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvqwdota8i", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvvfmm", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvvmm", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvvmtls", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvvmttls", + .omit = true, + }, + .{ + .llvm_name = "experimental-zvzip", + .omit = true, + }, + + .{ + .llvm_name = "unaligned-scalar-mem", + .zig_name = "unaligned_access", + }, + .{ + .llvm_name = "unaligned-vector-mem", + .zig_name = "unaligned_vector_access", + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + .{ + .llvm_name = "generic-ooo", + .omit = true, + }, + .{ + .llvm_name = "generic-rv32", + .omit = true, + }, + .{ + .llvm_name = "generic-rv64", + .omit = true, + }, }, .extra_models = &.{ .{ .llvm_name = null, - .zig_name = "baseline_rv32", - .features = &.{ "32bit", "a", "c", "d", "f", "i", "m" }, + .zig_name = "rv32e", + .features = &.{ "32bit", "e" }, }, .{ .llvm_name = null, - .zig_name = "baseline_rv64", - .features = &.{ "64bit", "a", "c", "d", "f", "i", "m" }, + .zig_name = "rv32ec", + .features = &.{ "32bit", "c", "e" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32emc", + .features = &.{ "32bit", "c", "e", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32gc", + .features = &.{ "32bit", "a", "c", "d", "i", "m", "zcd", "zcf", "zicsr", "zifencei" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32i", + .features = &.{ "32bit", "i" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32im", + .features = &.{ "32bit", "i", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32ima", + .features = &.{ "32bit", "a", "i", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32imac", + .features = &.{ "32bit", "a", "c", "i", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32imafc", + .features = &.{ "32bit", "a", "c", "f", "i", "m", "zcf" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32imafdc", + .features = &.{ "32bit", "a", "c", "d", "i", "m", "zcd", "zcf" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv32imc", + .features = &.{ "32bit", "c", "i", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv64gc", + .features = &.{ "64bit", "a", "c", "d", "i", "m", "zcd", "zicsr", "zifencei" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv64i", + .features = &.{ "64bit", "i" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv64im", + .features = &.{ "64bit", "i", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv64ima", + .features = &.{ "64bit", "a", "i", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv64imac", + .features = &.{ "64bit", "a", "c", "i", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv64imafc", + .features = &.{ "64bit", "a", "c", "f", "i", "m" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv64imafdc", + .features = &.{ "64bit", "a", "c", "d", "i", "m", "zcd" }, + }, + .{ + .llvm_name = null, + .zig_name = "rv64imc", + .features = &.{ "64bit", "c", "i", "m" }, + }, + + .{ + .llvm_name = null, + .zig_name = "rva20s64", + .features = &.{"rva20s64"}, + }, + .{ + .llvm_name = null, + .zig_name = "rva20u64", + .features = &.{"rva20u64"}, + }, + .{ + .llvm_name = null, + .zig_name = "rva22s64", + .features = &.{"rva22s64"}, + }, + .{ + .llvm_name = null, + .zig_name = "rva22u64", + .features = &.{"rva22u64"}, + }, + .{ + .llvm_name = null, + .zig_name = "rva23s64", + .features = &.{"rva23s64"}, + }, + .{ + .llvm_name = null, + .zig_name = "rva23u64", + .features = &.{"rva23u64"}, + }, + .{ + .llvm_name = null, + .zig_name = "rvb23s64", + .features = &.{"rvb23s64"}, + }, + .{ + .llvm_name = null, + .zig_name = "rvb23u64", + .features = &.{"rvb23u64"}, + }, + .{ + .llvm_name = null, + .zig_name = "rvi20u32", + .features = &.{"rvi20u32"}, + }, + .{ + .llvm_name = null, + .zig_name = "rvi20u64", + .features = &.{"rvi20u64"}, + }, + }, + }, + .{ + .zig_name = "sh", + .llvm = null, + .extra_features = &.{ + .{ + .zig_name = "cas", + .desc = "Enable cas.l instruction", + .deps = &.{}, + }, + .{ + .zig_name = "dsp", + .desc = "Enable DSP extension", + .deps = &.{}, + }, + .{ + .zig_name = "dynshift", + .desc = "Enable dynamic shift instructions", + .deps = &.{}, + }, + .{ + .zig_name = "fpu", + .desc = "Enable floating point unit", + .deps = &.{}, + }, + .{ + .zig_name = "fsca", + .desc = "Enable fsca instruction", + .deps = &.{"fpu"}, + }, + .{ + .zig_name = "fsrra", + .desc = "Enable fsrra instruction", + .deps = &.{"fpu"}, + }, + .{ + .zig_name = "mmu", + .desc = "Enable memory management unit", + .deps = &.{}, + }, + .{ + .zig_name = "sh2", + .desc = "Enable SH-2 instructions", + .deps = &.{}, + }, + .{ + .zig_name = "sh2a", + .desc = "Enable SH-2A instructions", + .deps = &.{ "dynshift", "sh2" }, + }, + .{ + .zig_name = "sh3", + .desc = "Enable SH-3 instructions", + .deps = &.{ "dynshift", "sh2" }, + }, + .{ + .zig_name = "sh4", + .desc = "Enable SH-4 instructions", + .deps = &.{"sh3"}, + }, + .{ + .zig_name = "sh4a", + .desc = "Enable SH-4A instructions", + .deps = &.{"sh4"}, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "j2", + .features = &.{ + "cas", + "dynshift", + "sh2", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh1", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "sh2", + .features = &.{ + "sh2", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh2_dsp", + .features = &.{ + "dsp", + "sh2", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh2a", + .features = &.{ + "fpu", + "sh2a", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh2a_nofpu", + .features = &.{ + "sh2a", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh2e", + .features = &.{ + "fpu", + "sh2", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh3", + .features = &.{ + "mmu", + "sh3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh3_dsp", + .features = &.{ + "dsp", + "mmu", + "sh3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh3e", + .features = &.{ + "fpu", + "mmu", + "sh3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh4", + .features = &.{ + "fpu", + "mmu", + "sh4", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh4_nofpu", + .features = &.{ + "mmu", + "sh4", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh4a", + .features = &.{ + "fpu", + "fsca", + "fsrra", + "mmu", + "sh4a", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh4a_nofpu", + .features = &.{ + "mmu", + "sh4a", + }, + }, + .{ + .llvm_name = null, + .zig_name = "sh4al_dsp", + .features = &.{ + "dsp", + "mmu", + "sh4a", + }, }, }, }, @@ -1885,6 +4532,143 @@ const targets = [_]ArchTarget{ .name = "Sparc", .td_name = "Sparc", }, + .feature_overrides = &.{ + .{ + .llvm_name = "leon", + .flatten = true, + }, + + .{ + .llvm_name = "64bit", + .omit = true, + }, + .{ + .llvm_name = "detectroundchange", + .omit = true, + }, + .{ + .llvm_name = "reserve-g1", + .omit = true, + }, + .{ + .llvm_name = "reserve-g2", + .omit = true, + }, + .{ + .llvm_name = "reserve-g3", + .omit = true, + }, + .{ + .llvm_name = "reserve-g4", + .omit = true, + }, + .{ + .llvm_name = "reserve-g5", + .omit = true, + }, + .{ + .llvm_name = "reserve-g6", + .omit = true, + }, + .{ + .llvm_name = "reserve-g7", + .omit = true, + }, + .{ + .llvm_name = "reserve-i0", + .omit = true, + }, + .{ + .llvm_name = "reserve-i1", + .omit = true, + }, + .{ + .llvm_name = "reserve-i2", + .omit = true, + }, + .{ + .llvm_name = "reserve-i3", + .omit = true, + }, + .{ + .llvm_name = "reserve-i4", + .omit = true, + }, + .{ + .llvm_name = "reserve-i5", + .omit = true, + }, + .{ + .llvm_name = "reserve-l0", + .omit = true, + }, + .{ + .llvm_name = "reserve-l1", + .omit = true, + }, + .{ + .llvm_name = "reserve-l2", + .omit = true, + }, + .{ + .llvm_name = "reserve-l3", + .omit = true, + }, + .{ + .llvm_name = "reserve-l4", + .omit = true, + }, + .{ + .llvm_name = "reserve-l5", + .omit = true, + }, + .{ + .llvm_name = "reserve-l6", + .omit = true, + }, + .{ + .llvm_name = "reserve-l7", + .omit = true, + }, + .{ + .llvm_name = "reserve-o0", + .omit = true, + }, + .{ + .llvm_name = "reserve-o1", + .omit = true, + }, + .{ + .llvm_name = "reserve-o2", + .omit = true, + }, + .{ + .llvm_name = "reserve-o3", + .omit = true, + }, + .{ + .llvm_name = "reserve-o4", + .omit = true, + }, + .{ + .llvm_name = "reserve-o5", + .omit = true, + }, + .{ + .llvm_name = "soft-float", + .omit = true, + }, + .{ + .llvm_name = "v8plus", + .omit = true, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + }, }, .{ .zig_name = "s390x", @@ -1892,6 +4676,225 @@ const targets = [_]ArchTarget{ .name = "SystemZ", .td_name = "SystemZ", }, + .feature_overrides = &.{ + .{ + .llvm_name = "backchain", + .omit = true, + }, + .{ + .llvm_name = "soft-float", + .omit = true, + }, + .{ + .llvm_name = "unaligned-symbols", + .omit = true, + }, + + // LLVM's names for s390x features are horribly long. + .{ + .llvm_name = "bear-enhancement", + .zig_name = "beareh", + }, + .{ + .llvm_name = "concurrent-functions", + .zig_name = "ccf", + }, + .{ + .llvm_name = "deflate-conversion", + .zig_name = "deflate", + }, + .{ + .llvm_name = "dfp-packed-conversion", + .zig_name = "dfppc", + }, + .{ + .llvm_name = "dfp-zoned-conversion", + .zig_name = "dfpzc", + }, + .{ + .llvm_name = "distinct-ops", + .zig_name = "distops", + }, + .{ + .llvm_name = "enhanced-dat-2", + .zig_name = "edat2", + }, + .{ + .llvm_name = "enhanced-sort", + .zig_name = "esort", + }, + .{ + .llvm_name = "execution-hint", + .zig_name = "exhint", + }, + .{ + .llvm_name = "fast-serialization", + .zig_name = "fbcrs", + }, + .{ + .llvm_name = "fp-extension", + .zig_name = "fpe", + }, + .{ + .llvm_name = "guarded-storage", + .zig_name = "gs", + }, + .{ + .llvm_name = "high-word", + .zig_name = "hiword", + }, + .{ + .llvm_name = "insert-reference-bits-multiple", + .zig_name = "irbm", + }, + .{ + .llvm_name = "interlocked-access1", + .zig_name = "iacc", + }, + .{ + .llvm_name = "load-and-trap", + .zig_name = "lat", + }, + .{ + .llvm_name = "load-and-zero-rightmost-byte", + .zig_name = "lzr", + }, + .{ + .llvm_name = "load-store-on-cond", + .zig_name = "loc", + }, + .{ + .llvm_name = "load-store-on-cond-2", + .zig_name = "loc2", + }, + .{ + .llvm_name = "message-security-assist-extension3", + .zig_name = "msa3", + }, + .{ + .llvm_name = "message-security-assist-extension4", + .zig_name = "msa4", + }, + .{ + .llvm_name = "message-security-assist-extension5", + .zig_name = "msa5", + }, + .{ + .llvm_name = "message-security-assist-extension7", + .zig_name = "msa7", + .extra_deps = &.{"msa5"}, + }, + .{ + .llvm_name = "message-security-assist-extension8", + .zig_name = "msa8", + .extra_deps = &.{"msa3"}, + }, + .{ + .llvm_name = "message-security-assist-extension9", + .zig_name = "msa9", + .extra_deps = &.{ "msa3", "msa4" }, + }, + .{ + .llvm_name = "message-security-assist-extension12", + .zig_name = "msa12", + }, + .{ + .llvm_name = "miscellaneous-extensions", + .zig_name = "minste", + }, + .{ + .llvm_name = "miscellaneous-extensions-2", + .zig_name = "minste2", + }, + .{ + .llvm_name = "miscellaneous-extensions-3", + .zig_name = "minste3", + .extra_deps = &.{ "distops", "fbcrs", "hiword", "iacc", "loc", "popcnt" }, + }, + .{ + .llvm_name = "miscellaneous-extensions-4", + .zig_name = "minste4", + }, + .{ + .llvm_name = "nnp-assist", + .zig_name = "nnpa", + .extra_deps = &.{"vx"}, + }, + .{ + .llvm_name = "population-count", + .zig_name = "popcnt", + }, + .{ + .llvm_name = "processor-activity-instrumentation", + .zig_name = "pai", + }, + .{ + .llvm_name = "processor-assist", + .zig_name = "ppa", + }, + .{ + .llvm_name = "reset-dat-protection", + .zig_name = "rdp", + }, + .{ + .llvm_name = "reset-reference-bits-multiple", + .zig_name = "rrbm", + }, + .{ + .llvm_name = "test-pending-external-interruption", + .zig_name = "tpei", + }, + .{ + .llvm_name = "transactional-execution", + .zig_name = "te", + .extra_deps = &.{ "exhint", "lat", "minste", "ppa" }, + }, + .{ + .llvm_name = "vector", + .zig_name = "vx", + }, + .{ + .llvm_name = "vector-enhancements-1", + .zig_name = "vxeh", + .extra_deps = &.{"vx"}, + }, + .{ + .llvm_name = "vector-enhancements-2", + .zig_name = "vxeh2", + .extra_deps = &.{"vxeh"}, + }, + .{ + .llvm_name = "vector-enhancements-3", + .zig_name = "vxeh3", + .extra_deps = &.{"vxeh2"}, + }, + .{ + .llvm_name = "vector-packed-decimal", + .zig_name = "vxpd", + .extra_deps = &.{"vx"}, + }, + .{ + .llvm_name = "vector-packed-decimal-enhancement", + .zig_name = "vxpdeh", + .extra_deps = &.{"vxpd"}, + }, + .{ + .llvm_name = "vector-packed-decimal-enhancement-2", + .zig_name = "vxpdeh2", + .extra_deps = &.{"vxpdeh"}, + }, + .{ + .llvm_name = "vector-packed-decimal-enhancement-3", + .zig_name = "vxpdeh3", + .extra_deps = &.{"vxpdeh2"}, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + }, }, .{ .zig_name = "ve", @@ -1944,13 +4947,17 @@ const targets = [_]ArchTarget{ .extra_deps = &.{"bulk_memory_opt"}, }, .{ - .llvm_name = "f16", + .llvm_name = "fp16", .extra_deps = &.{"simd128"}, }, .{ .llvm_name = "reference-types", .extra_deps = &.{ "bulk_memory", "call_indirect_overlong" }, }, + .{ + .llvm_name = "relaxed-atomics", + .extra_deps = &.{"atomics"}, + }, .{ .llvm_name = "relaxed-simd", .extra_deps = &.{"simd128"}, @@ -1997,10 +5004,8 @@ const targets = [_]ArchTarget{ .llvm_name = null, .zig_name = "wasm_v3_0", .features = &.{ - "atomics", "exception_handling", "extended_const", - "fp16", "gc", "multimemory", "mutable_globals", @@ -2035,10 +5040,167 @@ const targets = [_]ArchTarget{ .llvm_name = "evex512", .omit = true, }, + .{ + .llvm_name = "harden-sls-ijmp", + .omit = true, + }, + .{ + .llvm_name = "harden-sls-ret", + .omit = true, + }, + .{ + .llvm_name = "inline-asm-use-gpr32", + .omit = true, + }, + .{ + .llvm_name = "lvi-cfi", + .omit = true, + }, + .{ + .llvm_name = "lvi-load-hardening", + .omit = true, + }, + .{ + .llvm_name = "reserve-edi", + .omit = true, + }, + .{ + .llvm_name = "reserve-r8", + .omit = true, + }, + .{ + .llvm_name = "reserve-r9", + .omit = true, + }, + .{ + .llvm_name = "reserve-r10", + .omit = true, + }, + .{ + .llvm_name = "reserve-r11", + .omit = true, + }, + .{ + .llvm_name = "reserve-r12", + .omit = true, + }, + .{ + .llvm_name = "reserve-r13", + .omit = true, + }, + .{ + .llvm_name = "reserve-r14", + .omit = true, + }, + .{ + .llvm_name = "reserve-r15", + .omit = true, + }, + .{ + .llvm_name = "reserve-r16", + .omit = true, + }, + .{ + .llvm_name = "reserve-r17", + .omit = true, + }, + .{ + .llvm_name = "reserve-r18", + .omit = true, + }, + .{ + .llvm_name = "reserve-r19", + .omit = true, + }, + .{ + .llvm_name = "reserve-r20", + .omit = true, + }, + .{ + .llvm_name = "reserve-r21", + .omit = true, + }, + .{ + .llvm_name = "reserve-r22", + .omit = true, + }, + .{ + .llvm_name = "reserve-r23", + .omit = true, + }, + .{ + .llvm_name = "reserve-r24", + .omit = true, + }, + .{ + .llvm_name = "reserve-r25", + .omit = true, + }, + .{ + .llvm_name = "reserve-r26", + .omit = true, + }, + .{ + .llvm_name = "reserve-r27", + .omit = true, + }, + .{ + .llvm_name = "reserve-r28", + .omit = true, + }, + .{ + .llvm_name = "reserve-r29", + .omit = true, + }, + .{ + .llvm_name = "reserve-r30", + .omit = true, + }, + .{ + .llvm_name = "reserve-r31", + .omit = true, + }, + .{ + .llvm_name = "retpoline", + .omit = true, + }, + .{ + .llvm_name = "retpoline-external-thunk", + .omit = true, + }, + .{ + .llvm_name = "retpoline-indirect-branches", + .omit = true, + }, + .{ + .llvm_name = "retpoline-indirect-calls", + .omit = true, + }, + .{ + .llvm_name = "seses", + .omit = true, + }, + .{ + .llvm_name = "soft-float", + .omit = true, + }, + .{ + .llvm_name = "tagged-globals", + .omit = true, + }, + .{ + .llvm_name = "x32", + .omit = true, + }, + .{ .llvm_name = "sse4.2", .extra_deps = &.{"crc32"}, }, + .{ + .llvm_name = "sse-unaligned-mem", + .zig_name = "unaligned_sse_access", + }, }, .extra_features = &.{ // Features removed from LLVM @@ -2067,6 +5229,7 @@ const targets = [_]ArchTarget{ .desc = "Prefetch with Intent to Write and T1 Hint", .deps = &.{}, }, + // Custom Zig features .{ .zig_name = "bsf_bsr_0_clobbers_result", @@ -2085,6 +5248,136 @@ const targets = [_]ArchTarget{ }, }, .model_overrides = &.{ + .{ + .llvm_name = "generic", + .omit = true, + }, + // LLVM defines a bunch of dumb aliases with foreach loops in X86.td. + .{ + .llvm_name = "pentium_mmx", + .omit = true, + }, + .{ + .llvm_name = "pentium_pro", + .omit = true, + }, + .{ + .llvm_name = "pentium_ii", + .omit = true, + }, + .{ + .llvm_name = "pentium_3m", + .omit = true, + }, + .{ + .llvm_name = "pentium_iii", + .omit = true, + }, + .{ + .llvm_name = "pentium_iii_no_xmm_regs", + .omit = true, + }, + .{ + .llvm_name = "pentium_m", + .omit = true, + }, + .{ + .llvm_name = "pentium4m", + .omit = true, + }, + .{ + .llvm_name = "pentium_4", + .omit = true, + }, + .{ + .llvm_name = "pentium_4_sse3", + .omit = true, + }, + .{ + .llvm_name = "core_2_duo_ssse3", + .omit = true, + }, + .{ + .llvm_name = "core_2_duo_sse4_1", + .omit = true, + }, + .{ + .llvm_name = "atom_sse4_2", + .omit = true, + }, + .{ + .llvm_name = "goldmont-plus", + .omit = true, + }, + .{ + .llvm_name = "core_i7_sse4_2", + .omit = true, + }, + .{ + .llvm_name = "core_aes_pclmulqdq", + .omit = true, + }, + .{ + .llvm_name = "corei7-avx", + .omit = true, + }, + .{ + .llvm_name = "core_2nd_gen_avx", + .omit = true, + }, + .{ + .llvm_name = "core-avx-i", + .omit = true, + }, + .{ + .llvm_name = "core_3rd_gen_avx", + .omit = true, + }, + .{ + .llvm_name = "core-avx2", + .omit = true, + }, + .{ + .llvm_name = "core_4th_gen_avx", + .omit = true, + }, + .{ + .llvm_name = "core_4th_gen_avx_tsx", + .omit = true, + }, + .{ + .llvm_name = "core_5th_gen_avx", + .omit = true, + }, + .{ + .llvm_name = "core_5th_gen_avx_tsx", + .omit = true, + }, + .{ + .llvm_name = "mic_avx512", + .omit = true, + }, + .{ + .llvm_name = "skylake-avx512", + .omit = true, + }, + .{ + .llvm_name = "icelake-client", + .omit = true, + }, + .{ + .llvm_name = "icelake-server", + .omit = true, + }, + .{ + .llvm_name = "graniterapids_d", + .omit = true, + }, + .{ + .llvm_name = "arrowlake_s", + .omit = true, + }, + .{ .llvm_name = "amdfam10", .extra_deps = &.{"3dnowa"}, @@ -2213,10 +5506,6 @@ const targets = [_]ArchTarget{ "prefetchwt1", }, }, - .{ - .llvm_name = "lakemont", - .extra_deps = &.{"soft_float"}, - }, .{ .llvm_name = "meteorlake", .extra_deps = &.{ "smap", "smep" }, @@ -2297,132 +5586,6 @@ const targets = [_]ArchTarget{ .llvm_name = "znver5", .extra_deps = &.{ "smap", "smep" }, }, - - // LLVM defines a bunch of dumb aliases with foreach loops in X86.td. - .{ - .llvm_name = "pentium_mmx", - .omit = true, - }, - .{ - .llvm_name = "pentium_pro", - .omit = true, - }, - .{ - .llvm_name = "pentium_ii", - .omit = true, - }, - .{ - .llvm_name = "pentium_3m", - .omit = true, - }, - .{ - .llvm_name = "pentium_iii", - .omit = true, - }, - .{ - .llvm_name = "pentium_iii_no_xmm_regs", - .omit = true, - }, - .{ - .llvm_name = "pentium_m", - .omit = true, - }, - .{ - .llvm_name = "pentium4m", - .omit = true, - }, - .{ - .llvm_name = "pentium_4", - .omit = true, - }, - .{ - .llvm_name = "pentium_4_sse3", - .omit = true, - }, - .{ - .llvm_name = "core_2_duo_ssse3", - .omit = true, - }, - .{ - .llvm_name = "core_2_duo_sse4_1", - .omit = true, - }, - .{ - .llvm_name = "atom_sse4_2", - .omit = true, - }, - .{ - .llvm_name = "goldmont-plus", - .omit = true, - }, - .{ - .llvm_name = "core_i7_sse4_2", - .omit = true, - }, - .{ - .llvm_name = "core_aes_pclmulqdq", - .omit = true, - }, - .{ - .llvm_name = "corei7-avx", - .omit = true, - }, - .{ - .llvm_name = "core_2nd_gen_avx", - .omit = true, - }, - .{ - .llvm_name = "core-avx-i", - .omit = true, - }, - .{ - .llvm_name = "core_3rd_gen_avx", - .omit = true, - }, - .{ - .llvm_name = "core-avx2", - .omit = true, - }, - .{ - .llvm_name = "core_4th_gen_avx", - .omit = true, - }, - .{ - .llvm_name = "core_4th_gen_avx_tsx", - .omit = true, - }, - .{ - .llvm_name = "core_5th_gen_avx", - .omit = true, - }, - .{ - .llvm_name = "core_5th_gen_avx_tsx", - .omit = true, - }, - .{ - .llvm_name = "mic_avx512", - .omit = true, - }, - .{ - .llvm_name = "skylake-avx512", - .omit = true, - }, - .{ - .llvm_name = "icelake-client", - .omit = true, - }, - .{ - .llvm_name = "icelake-server", - .omit = true, - }, - .{ - .llvm_name = "graniterapids_d", - .omit = true, - }, - .{ - .llvm_name = "arrowlake_s", - .omit = true, - }, }, .extra_models = &.{ .{ @@ -2467,15 +5630,10 @@ const targets = [_]ArchTarget{ }, .{ .llvm_name = "xs1b-generic", - .omit = true, + .zig_name = "xs1b", }, }, .extra_models = &.{ - .{ - .llvm_name = null, - .zig_name = "xs1b", - .features = &.{}, - }, .{ .llvm_name = null, .zig_name = "xs2a", @@ -2494,6 +5652,191 @@ const targets = [_]ArchTarget{ .name = "Xtensa", .td_name = "Xtensa", }, + .feature_overrides = &.{ + .{ + .llvm_name = "forced-atomics", + .omit = true, + }, + }, + .model_overrides = &.{ + .{ + .llvm_name = "generic", + .zig_name = "xtensa", + }, + }, + }, + .{ + .zig_name = "z80", + .llvm = null, + .extra_features = &.{ + .{ + .zig_name = "epu", + .desc = "Enable Extended Processing Unit instructions", + .deps = &.{"z280"}, + }, + .{ + .zig_name = "ez80", + .desc = "Enable eZ80 instructions including ADL mode", + .deps = &.{ "xyhl", "z180" }, + }, + .{ + .zig_name = "infc", + .desc = "Enable flags-only port input instruction", + .deps = &.{}, + }, + .{ + .zig_name = "no_inirx", + .desc = "Disable block I/O instructions that address the port with DE and count with BC", + .deps = &.{}, + }, + .{ + .zig_name = "no_ld_i_hl", + .desc = "Disable 16-bit I register transfers", + .deps = &.{}, + }, + .{ + .zig_name = "r800", + .desc = "Enable R800 instructions", + .deps = &.{ "infc", "xyhl" }, + }, + .{ + .zig_name = "reliable_ld_a_i", + .desc = "LD A,I and LD A,R reliably report the interrupt enable state", + .deps = &.{}, + }, + .{ + .zig_name = "sli", + .desc = "Enable shift left inserting 1 instructions", + .deps = &.{}, + }, + .{ + .zig_name = "xdcb", + .desc = "Enable indexed rotate, shift, RES, and SET instructions that also store to a register", + .deps = &.{}, + }, + .{ + .zig_name = "xyhl", + .desc = "Enable index register halves (IXH, IXL, IYH, IYL)", + .deps = &.{}, + }, + .{ + .zig_name = "z180", + .desc = "Enable Z180 instructions", + .deps = &.{}, + }, + .{ + .zig_name = "z280", + .desc = "Enable Z280 instructions", + .deps = &.{ "infc", "xyhl" }, + }, + .{ + .zig_name = "z380", + .desc = "Enable Z380 instructions including long mode", + .deps = &.{ "xyhl", "z180" }, + }, + .{ + .zig_name = "z80n", + .desc = "Enable Z80N instructions", + .deps = &.{}, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "ez80", + .features = &.{ + "ez80", + "reliable_ld_a_i", + }, + }, + .{ + .llvm_name = null, + .zig_name = "ez80190", + .features = &.{ + "ez80", + "no_inirx", + "no_ld_i_hl", + "reliable_ld_a_i", + }, + }, + .{ + .llvm_name = null, + .zig_name = "ez80f92", + .features = &.{ + "ez80", + "no_ld_i_hl", + "reliable_ld_a_i", + }, + }, + .{ + .llvm_name = null, + .zig_name = "r800", + .features = &.{ + "r800", + }, + }, + .{ + .llvm_name = null, + .zig_name = "z180", + .features = &.{ + "z180", + }, + }, + .{ + .llvm_name = null, + .zig_name = "z280", + .features = &.{ + "reliable_ld_a_i", + "z280", + }, + }, + .{ + .llvm_name = null, + .zig_name = "z380", + .features = &.{ + "reliable_ld_a_i", + "z380", + }, + }, + .{ + .llvm_name = null, + .zig_name = "z80", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "z8400", + .features = &.{ + "infc", + "sli", + "xdcb", + "xyhl", + }, + }, + .{ + .llvm_name = null, + .zig_name = "z84c00", + .features = &.{ + "infc", + "reliable_ld_a_i", + "sli", + "xdcb", + "xyhl", + }, + }, + .{ + .llvm_name = null, + .zig_name = "z80n", + .features = &.{ + "infc", + "reliable_ld_a_i", + "sli", + "xdcb", + "xyhl", + "z80n", + }, + }, + }, }, };