diff --git a/lib/std/Target.zig b/lib/std/Target.zig
index 9c8296c14f..dfaa269901 100644
--- a/lib/std/Target.zig
+++ b/lib/std/Target.zig
@@ -768,7 +768,7 @@ pub const powerpc = @import("Target/powerpc.zig");
 pub const propeller = @import("Target/propeller.zig");
 pub const riscv = @import("Target/riscv.zig");
 pub const s390x = @import("Target/s390x.zig");
-pub const sh = @import("Target/generic.zig");
+pub const sh = @import("Target/sh.zig");
 pub const sparc = @import("Target/sparc.zig");
 pub const spirv = @import("Target/spirv.zig");
 pub const spork8 = @import("Target/generic.zig");
@@ -2075,6 +2075,7 @@ pub const Cpu = struct {
                 .riscv32, .riscv32be => &riscv.cpu.rv32i,
                 .riscv64, .riscv64be => &riscv.cpu.rv64i,
                 .s390x => &s390x.cpu.arch8,
+                .sh, .sheb => &sh.cpu.sh1,
                 .sparc => &sparc.cpu.v7,
                 .sparc64 => &sparc.cpu.v9, // SPARC can only be 64-bit from v9 and up.
                 .spirv32, .spirv64 => &spirv.cpu.v1_0,
@@ -2158,6 +2159,10 @@ pub const Cpu = struct {
                 .riscv32, .riscv32be => &riscv.cpu.rv32gc,
                 .riscv64, .riscv64be => &riscv.cpu.rv64gc,
                 .s390x => &s390x.cpu.arch11,
+                .sh, .sheb => switch (os.tag) {
+                    .netbsd => &sh.cpu.sh3,
+                    else => &sh.cpu.sh4,
+                },
                 .sparc => switch (os.tag) {
                     .linux => &sparc.cpu.v9, // glibc does not work with 'plain' v8.
                     else => &sparc.cpu.v8,
diff --git a/lib/std/Target/sh.zig b/lib/std/Target/sh.zig
new file mode 100644
index 0000000000..a542acb58c
--- /dev/null
+++ b/lib/std/Target/sh.zig
@@ -0,0 +1,236 @@
+//! This file is auto-generated by tools/update_cpu_features.zig.
+
+const std = @import("../std.zig");
+const CpuFeature = std.Target.Cpu.Feature;
+const CpuModel = std.Target.Cpu.Model;
+
+pub const Feature = enum {
+    cas,
+    dsp,
+    dynshift,
+    fpu,
+    fsca,
+    fsrra,
+    mmu,
+    sh2,
+    sh2a,
+    sh3,
+    sh4,
+    sh4a,
+};
+
+pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet;
+pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas;
+pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny;
+pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll;
+
+pub const all_features = blk: {
+    const len = @typeInfo(Feature).@"enum".field_names.len;
+    std.debug.assert(len <= CpuFeature.Set.needed_bit_count);
+    var result: [len]CpuFeature = undefined;
+    result[@backingInt(Feature.cas)] = .{
+        .llvm_name = null,
+        .description = "Enable cas.l instruction",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.dsp)] = .{
+        .llvm_name = null,
+        .description = "Enable DSP extension",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.dynshift)] = .{
+        .llvm_name = null,
+        .description = "Enable dynamic shift instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.fpu)] = .{
+        .llvm_name = null,
+        .description = "Enable floating point unit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.fsca)] = .{
+        .llvm_name = null,
+        .description = "Enable fsca instruction",
+        .dependencies = featureSet(&[_]Feature{
+            .fpu,
+        }),
+    };
+    result[@backingInt(Feature.fsrra)] = .{
+        .llvm_name = null,
+        .description = "Enable fsrra instruction",
+        .dependencies = featureSet(&[_]Feature{
+            .fpu,
+        }),
+    };
+    result[@backingInt(Feature.mmu)] = .{
+        .llvm_name = null,
+        .description = "Enable memory management unit",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sh2)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-2 instructions",
+        .dependencies = featureSet(&[_]Feature{}),
+    };
+    result[@backingInt(Feature.sh2a)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-2A instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .dynshift,
+            .sh2,
+        }),
+    };
+    result[@backingInt(Feature.sh3)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-3 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .dynshift,
+            .sh2,
+        }),
+    };
+    result[@backingInt(Feature.sh4)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-4 instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .sh3,
+        }),
+    };
+    result[@backingInt(Feature.sh4a)] = .{
+        .llvm_name = null,
+        .description = "Enable SH-4A instructions",
+        .dependencies = featureSet(&[_]Feature{
+            .sh4,
+        }),
+    };
+    const ti = @typeInfo(Feature);
+    for (&result, 0..) |*elem, i| {
+        elem.index = i;
+        elem.name = ti.@"enum".field_names[i];
+    }
+    break :blk result;
+};
+
+pub const cpu = struct {
+    pub const j2: CpuModel = .{
+        .name = "j2",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .cas,
+            .dynshift,
+            .sh2,
+        }),
+    };
+    pub const sh1: CpuModel = .{
+        .name = "sh1",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{}),
+    };
+    pub const sh2: CpuModel = .{
+        .name = "sh2",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sh2,
+        }),
+    };
+    pub const sh2_dsp: CpuModel = .{
+        .name = "sh2_dsp",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .dsp,
+            .sh2,
+        }),
+    };
+    pub const sh2a: CpuModel = .{
+        .name = "sh2a",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .sh2a,
+        }),
+    };
+    pub const sh2a_nofpu: CpuModel = .{
+        .name = "sh2a_nofpu",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .sh2a,
+        }),
+    };
+    pub const sh2e: CpuModel = .{
+        .name = "sh2e",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .sh2,
+        }),
+    };
+    pub const sh3: CpuModel = .{
+        .name = "sh3",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .mmu,
+            .sh3,
+        }),
+    };
+    pub const sh3_dsp: CpuModel = .{
+        .name = "sh3_dsp",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .dsp,
+            .mmu,
+            .sh3,
+        }),
+    };
+    pub const sh3e: CpuModel = .{
+        .name = "sh3e",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .mmu,
+            .sh3,
+        }),
+    };
+    pub const sh4: CpuModel = .{
+        .name = "sh4",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fpu,
+            .mmu,
+            .sh4,
+        }),
+    };
+    pub const sh4_nofpu: CpuModel = .{
+        .name = "sh4_nofpu",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .mmu,
+            .sh4,
+        }),
+    };
+    pub const sh4a: CpuModel = .{
+        .name = "sh4a",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .fsca,
+            .fsrra,
+            .mmu,
+            .sh4a,
+        }),
+    };
+    pub const sh4a_nofpu: CpuModel = .{
+        .name = "sh4a_nofpu",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .mmu,
+            .sh4a,
+        }),
+    };
+    pub const sh4al_dsp: CpuModel = .{
+        .name = "sh4al_dsp",
+        .llvm_name = null,
+        .features = featureSet(&[_]Feature{
+            .dsp,
+            .mmu,
+            .sh4a,
+        }),
+    };
+};
diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig
index b2f499a307..32d6bd8228 100644
--- a/tools/update_cpu_features.zig
+++ b/tools/update_cpu_features.zig
@@ -4060,6 +4060,197 @@ const targets = [_]ArchTarget{
             },
         },
     },
+    .{
+        .zig_name = "sh",
+        .llvm = null,
+        .extra_features = &.{
+            .{
+                .zig_name = "cas",
+                .desc = "Enable cas.l instruction",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "dsp",
+                .desc = "Enable DSP extension",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "dynshift",
+                .desc = "Enable dynamic shift instructions",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "fpu",
+                .desc = "Enable floating point unit",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "fsca",
+                .desc = "Enable fsca instruction",
+                .deps = &.{"fpu"},
+            },
+            .{
+                .zig_name = "fsrra",
+                .desc = "Enable fsrra instruction",
+                .deps = &.{"fpu"},
+            },
+            .{
+                .zig_name = "mmu",
+                .desc = "Enable memory management unit",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "sh2",
+                .desc = "Enable SH-2 instructions",
+                .deps = &.{},
+            },
+            .{
+                .zig_name = "sh2a",
+                .desc = "Enable SH-2A instructions",
+                .deps = &.{ "dynshift", "sh2" },
+            },
+            .{
+                .zig_name = "sh3",
+                .desc = "Enable SH-3 instructions",
+                .deps = &.{ "dynshift", "sh2" },
+            },
+            .{
+                .zig_name = "sh4",
+                .desc = "Enable SH-4 instructions",
+                .deps = &.{"sh3"},
+            },
+            .{
+                .zig_name = "sh4a",
+                .desc = "Enable SH-4A instructions",
+                .deps = &.{"sh4"},
+            },
+        },
+        .extra_models = &.{
+            .{
+                .llvm_name = null,
+                .zig_name = "j2",
+                .features = &.{
+                    "cas",
+                    "dynshift",
+                    "sh2",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh1",
+                .features = &.{},
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh2",
+                .features = &.{
+                    "sh2",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh2_dsp",
+                .features = &.{
+                    "dsp",
+                    "sh2",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh2a",
+                .features = &.{
+                    "fpu",
+                    "sh2a",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh2a_nofpu",
+                .features = &.{
+                    "sh2a",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh2e",
+                .features = &.{
+                    "fpu",
+                    "sh2",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh3",
+                .features = &.{
+                    "mmu",
+                    "sh3",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh3_dsp",
+                .features = &.{
+                    "dsp",
+                    "mmu",
+                    "sh3",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh3e",
+                .features = &.{
+                    "fpu",
+                    "mmu",
+                    "sh3",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh4",
+                .features = &.{
+                    "fpu",
+                    "mmu",
+                    "sh4",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh4_nofpu",
+                .features = &.{
+                    "mmu",
+                    "sh4",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh4a",
+                .features = &.{
+                    "fpu",
+                    "fsca",
+                    "fsrra",
+                    "mmu",
+                    "sh4a",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh4a_nofpu",
+                .features = &.{
+                    "mmu",
+                    "sh4a",
+                },
+            },
+            .{
+                .llvm_name = null,
+                .zig_name = "sh4al_dsp",
+                .features = &.{
+                    "dsp",
+                    "mmu",
+                    "sh4a",
+                },
+            },
+        },
+    },
     .{
         .zig_name = "sparc",
         .llvm = .{