 Chunan ZengandClaude Opus 5.5
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f2d3188925
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[Perf] moe: Fold the routed scaling factor into the mega MoE pre-dispatch (#46090)
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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2026-10-28 17:46:43 -07:00 |
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0fdc4e82ca
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[Feat] rust-server: Carry customized_info through the native /generate frontend (#46949)
Co-authored-by: metamergebot <metamergebot@users.noreply.github.com>
Co-authored-by: shodoco <shodoco@users.noreply.github.com>
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2026-10-28 17:41:46 -07:00 |
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Liangsheng YinandQiaolin-Yu
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c10e0e1773
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[Refactor] spec: Make ForwardBatch the single channel for the ragged-verify layout (#34031)
Co-authored-by: Qiaolin-Yu <liin1211@outlook.com>
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2026-10-28 16:37:36 -07:00 |
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f5c23b4769
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[Fix] rust_server: Record startup-time metrics in Rust mode (#47114)
Co-authored-by: metamergebot <324680979+metamergebot@users.noreply.github.com>
Co-authored-by: shodoco <shodoco@users.noreply.github.com>
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2026-10-28 16:24:23 -07:00 |
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Glen Liu
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6b697b9aad
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[Perf] LoRA: bound csgmv CUDA-graph segment grids by token count (#46743)
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2026-10-28 16:12:15 -07:00 |
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Liangsheng Yin
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76d5b3ce02
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[Perf] dsv41: Run MegaGate routing in prefill (#47148)
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2026-10-28 15:53:36 -07:00 |
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Liangsheng Yin
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88fea372d4
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[Fix] dsv4: Capture the replay tail thread-locally while serving (#47146)
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2026-10-28 15:01:55 -07:00 |
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Liangsheng Yin
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e105742296
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[Fix] linker: Order loads behind the forward that may still use the pages (#45580)
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2026-10-28 14:29:01 -07:00 |
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Liangsheng Yin
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54d2f65540
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[Perf] dsv41: Read Engram rows in place by default for GPU tables over NVLink (#47033)
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2026-10-28 13:28:47 -07:00 |
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Liangsheng Yin
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1825a09dbb
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[Perf] dsv41: Use the Engram all-to-all lookup for decode and CUDA graphs (#46955)
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2026-10-28 13:25:00 -07:00 |
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YAMYandOasis-Git
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e1b6d7581e
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[Feat] [NVIDIA] runtime: Add a master switch for megakernel runtime optimizations (#47105)
Co-authored-by: Oasis-Git <ayw.sirius19@gmail.com>
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2026-10-28 12:19:43 -07:00 |
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Michael
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5ac32ada54
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[Test] [AMD] diffusion: Compute the VAE blend test's fp16 reference in fp32 on ROCm (#46889)
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2026-10-28 10:23:39 -07:00 |
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Avaya Aggarwal
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4517a5ff1b
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[Fix] comfyui: Reject conditioning kwargs the SGLD adapters silently drop (#46286)
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2026-10-28 23:14:47 +08:00 |
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Avaya AggarwalandWenhaoZhang
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b1c6945659
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[Feat] comfyui: Add SGLDWorkerStatus diagnostics node (#43697)
Co-authored-by: WenhaoZhang <42087078+niehen6174@users.noreply.github.com>
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2026-10-28 23:14:35 +08:00 |
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Shangming CaiandClaude Opus 5.5
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ff96d43008
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[Fix] ci: Repair main after the #39728/#46990 merge race and RUSTSEC-2026-0414 (#47078)
Co-authored-by: Claude Opus 5.5 <noreply@anthropic.com>
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2026-10-28 23:11:21 +08:00 |
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Cheng Wan
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5cc9c933fc
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[Fix] mem_cache: support prefix commits in unified MHA views (#47071)
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2026-10-28 05:17:22 -07:00 |
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Cheng Wan
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e028ee40b0
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[Refactor] cache: Build prefix-tree components from storage slots (#46991)
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2026-10-28 05:04:43 -07:00 |
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Cheng Wan
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d5bc823ad5
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[Refactor] attention: Use typed KV views and shared layer routing (#46990)
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2026-10-28 05:04:16 -07:00 |
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Cheng Wan
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146378629d
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[Refactor] kv-cache: Share storage interfaces across runtime consumers (#46989)
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2026-10-28 05:03:48 -07:00 |
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Cheng Wan
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53592ea5ff
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[Refactor] kv-cache: Centralize request rows and allocation lifecycle (#46988)
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2026-10-28 05:03:23 -07:00 |
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Cheng Wan
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ca8184e13a
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[Refactor] kv-cache: Separate byte storage from allocation identities (#46987)
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2026-10-28 05:02:46 -07:00 |
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Cheng Wan
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240862923e
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[Refactor] mem-cache: Bind fused drafts to routed KV views (#46986)
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2026-10-28 05:02:08 -07:00 |
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Cheng Wan
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eb79ecca11
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[Refactor] mem-cache: Track transfer pins at allocator boundaries (#46985)
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2026-10-28 05:01:43 -07:00 |
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Cheng Wan
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f80cb3a2fd
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[Refactor] mem-cache: Replace unified pool variants with a routed cache (#46984)
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2026-10-28 05:01:17 -07:00 |
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Cheng Wan
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14fea75124
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[Fix] [AMD] attention: Avoid fused writes to translated window storage (#46983)
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2026-10-28 05:00:50 -07:00 |
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Cheng Wan
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298b563596
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[Refactor] mem-cache: Build cache transfers from storage plans (#46982)
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2026-10-28 05:00:25 -07:00 |
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Cheng Wan
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1721c099f9
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[Fix] hicache: Build hybrid recurrent host pools consistently (#46981)
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2026-10-28 04:59:59 -07:00 |
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Cheng Wan
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306a699a60
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[Refactor] mem-cache: Centralize recurrent state ownership and access (#46980)
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2026-10-28 04:59:34 -07:00 |
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Cheng Wan
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3b597cb76d
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[Refactor] mem-cache: Route layer access through KV subpool views (#46979)
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2026-10-28 04:59:08 -07:00 |
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Cheng Wan
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cf3d21b0c9
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[Refactor] mem-cache: Describe KV address translation with ID spaces (#46978)
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2026-10-28 04:58:30 -07:00 |
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Cheng Wan
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5f6075fa2f
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[Refactor] mem_cache: Centralize unified KV capacity pricing and admission (#46977)
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2026-10-28 04:58:06 -07:00 |
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Cheng Wan
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ccc71fa514
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[Refactor] mem_cache: Use one allocator for unified KV sub-pools (#46976)
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2026-10-28 04:57:40 -07:00 |
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Cheng Wan
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3355d668ce
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[Fix] mem_cache: Forward HiCache completion events to recurrent state (#46975)
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2026-10-28 04:57:00 -07:00 |
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Cheng Wan
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5433093d83
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[Refactor] mem_cache: Build unified KV pools from layer declarations (#46974)
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2026-10-28 04:54:43 -07:00 |
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Cheng Wan
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335682058a
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[Refactor] mem_cache: Separate unified KV layout specifications (#46973)
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2026-10-28 04:54:07 -07:00 |
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Rain Jiang
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69233a4622
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[Feat] rust-server: Fan control requests out to every DP rank (#46181)
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2026-10-28 04:53:40 -07:00 |
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Cheng Wan
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8044ed4e28
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[Fix] mem_cache: Reject unsupported int8 checkpoints with unified memory (#46972)
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2026-10-28 04:52:10 -07:00 |
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Cheng Wan
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77936f7b25
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[Fix] mem_cache: Preserve convolution slice axis in unified hybrid pools (#46971)
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2026-10-28 04:51:00 -07:00 |
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Cheng Wan
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ddf24c4d17
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[Test] mem_cache: Add unified KV layout and allocator regression coverage (#46970)
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2026-10-28 04:49:58 -07:00 |
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iridiumine
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f59cc7e45f
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[Perf] [NPU] dsv4: drop host-syncing ops from the decode scheduler chain (aclnnNonzeroV2 + D2H) (#46805)
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2026-10-28 19:28:23 +08:00 |
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MickandMick Qian
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e0df901d68
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[Fix] diffusion/ci: Keep final failure reasons at the end of shard logs (#46916)
Co-authored-by: Mick Qian <mickqian@users.noreply.github.com>
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2026-10-28 18:59:56 +08:00 |
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Monishver
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73fbf5ccd3
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[Perf] speculative: Rotate multi-layer EAGLE prefill input_ids 4096 ids per trip, not 8 (#46639)
Signed-off-by: Monishver Chandrasekaran <monishverchandrasekaran@gmail.com>
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2026-10-28 03:20:40 -07:00 |
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Olga Miroshnichenko
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86f72e5b5c
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[Fix] [AMD] memory_pool: Keep K and V in separate allocations on ROCm (#46861)
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2026-10-28 03:06:15 -07:00 |
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Eric.Chin.AMDandThomas Wang
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edd270fd69
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[Feat] [AMD] dsa: Enable DCP on the triton sparse-MLA backend (#44322)
Co-authored-by: Thomas Wang <thomawan@amd.com>
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2026-10-28 02:45:44 -07:00 |
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f65af1cd83
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[Feat] HiCache: Page unified e2e integration (#39728)
Co-authored-by: huangtingwei <141888744+huangtingwei9988@users.noreply.github.com>
Co-authored-by: Zhangheng <hzh0425@apache.org>
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2026-10-28 17:39:30 +08:00 |
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AMD-yanfeiwang
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b85d6a8893
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[Feat] [AMD] mori: Allow MoRI for DeepSeek-V4.1 DSpark PD (#42457)
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2026-10-28 02:25:59 -07:00 |
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aa8e0a9b6a
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[Fix] [AMD] dsa: Limit AITER decode metadata to the active batch (#41696)
Co-authored-by: Pawel Kowalski <pawel.kowalski@silo.ai>
Co-authored-by: Jacob0226 <Jacob.CHANG@amd.com>
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2026-10-28 02:15:49 -07:00 |
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Aarne Talman
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c6c7533957
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[Perf] batch-invariant: Fused residual add + RMSNorm kernel (#46159)
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2026-10-28 02:03:06 -07:00 |
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Aarne Talman
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1e7e19285d
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[Perf] [AMD] batch-invariant: Tune the bf16 matmul for gfx950 (#44045)
Signed-off-by: Aarne Talman <aarne.talman@amd.com>
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2026-10-28 01:51:49 -07:00 |
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Liangsheng Yin
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c240169265
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[Fix] custom-all-reduce: Keep integer all-reduces off the custom all-reduce kernels (#46994)
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2026-10-28 01:15:28 -07:00 |
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