mirror of
https://gitlab.com/qemu-project/qemu.git
synced 2026-10-28 14:04:39 +08:00
Zephyr Li
57b484e2d2
Since commitcfc96df65e, riscv_pmu_ctr_get_fixed_counters_val() returns the complete 64-bit fixed-counter value. The RV32 counter access paths, however, still perform parts of the offset calculation on separately extracted 32-bit halves. In particular, riscv_pmu_write_ctrh() deposits the low 32 bits of the complete fixed-counter value into the high half of mhpmcounter_prev. riscv_pmu_read_ctr() also subtracts a 32-bit half of the previous value from the complete 64-bit fixed-counter value. Consequently, writes to mcycleh can be lost and carries between the low and high halves are not handled correctly. Keep the fixed-counter offset calculation entirely in 64 bits. Before a running counter is partially written, materialize its current architectural value and reset the fixed-counter baseline. On reads, calculate the complete 64-bit counter value before extracting the half requested by RV32. Register RV32 system TCG tests with the Meson build. Add a test for high-half writes, low-to-high carry, and preserving the carried high half across a subsequent low-half write. Fixes:cfc96df65e("target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val") Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4219 Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com> Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Reviewed-by: Chao Liu <chao.liu@processmission.com> Message-ID: <20261008035150.2223-1-fritchleybohrer@gmail.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
37 lines
806 B
Meson
37 lines
806 B
Meson
# SPDX-License-Identifier: GPL-2.0-or-later
|
|
|
|
tests = []
|
|
|
|
link_script = files('../semihost.ld')[0]
|
|
cflags = ['-march=rv32im_zicsr',
|
|
'-mabi=ilp32',
|
|
'-nostdlib',
|
|
'-ffreestanding',
|
|
'-Wa,--noexecstack',
|
|
'-Wl,-T', link_script]
|
|
qemu_args = ['-M', 'virt',
|
|
'-display', 'none',
|
|
'-serial', 'stdio',
|
|
'-semihosting',
|
|
'-bios']
|
|
|
|
tests += {
|
|
'test-mcycle.S': {
|
|
'cflags': cflags,
|
|
'qemu_args': ['-icount', 'shift=1', qemu_args],
|
|
},
|
|
}
|
|
|
|
if 'qemu-system-riscv32' in emulators
|
|
tcg_tests += {
|
|
'riscv32-softmmu': {
|
|
'cc': cc,
|
|
'cc_dockerfile': cc_dockerfile,
|
|
'folder': 'riscv32',
|
|
'gdb_arch': 'riscv32',
|
|
'qemu': emulators['qemu-system-riscv32'],
|
|
'tests': tests,
|
|
}
|
|
}
|
|
endif
|