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target/riscv: Remove upper_half from riscv_pmu_ctr_get_fixed_counters_val

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Now that mhpmcounter is always a 64-bit value we can remove the
upper_half argument from riscv_pmu_ctr_get_fixed_counters_val() and
always return a 64-bit value.

Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Anton Johansson <anjo@rev.ng>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251103033713.904455-9-alistair.francis@wdc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
This commit is contained in:
Alistair Francis committed 2026-01-09 15:01:10 +10:00
1 parent 4fe8ae0906
commit cfc96df65e
1 file changed
+9 -31
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target/riscv/csr.c
+9 -31
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@@ -1235,14 +1235,12 @@ static RISCVException write_mhpmeventh(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
int counter_idx,
bool upper_half)
static uint64_t riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
int counter_idx)
{
int inst = riscv_pmu_ctr_monitor_instructions(env, counter_idx);
uint64_t *counter_arr_virt = env->pmu_fixed_ctrs[inst].counter_virt;
uint64_t *counter_arr = env->pmu_fixed_ctrs[inst].counter;
target_ulong result = 0;
uint64_t curr_val = 0;
uint64_t cfg_val = 0;
@@ -1262,7 +1260,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
curr_val = cpu_get_host_ticks();
}
goto done;
return curr_val;
}
/* Update counter before reading. */
@@ -1288,14 +1286,7 @@ static target_ulong riscv_pmu_ctr_get_fixed_counters_val(CPURISCVState *env,
curr_val += counter_arr_virt[PRV_U];
}
done:
if (riscv_cpu_mxl(env) == MXL_RV32) {
result = upper_half ? curr_val >> 32 : curr_val;
} else {
result = curr_val;
}
return result;
return curr_val;
}
static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong val,
@@ -1312,7 +1303,7 @@ static RISCVException riscv_pmu_write_ctr(CPURISCVState *env, target_ulong val,
if (!get_field(env->mcountinhibit, BIT(ctr_idx)) &&
(riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) {
ctr = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, false);
ctr = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx);
counter->mhpmcounter_prev = deposit64(counter->mhpmcounter_prev,
0, deposit_size, ctr);
if (ctr_idx > 2) {
@@ -1339,7 +1330,7 @@ static RISCVException riscv_pmu_write_ctrh(CPURISCVState *env, target_ulong val,
if (!get_field(env->mcountinhibit, BIT(ctr_idx)) &&
(riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
riscv_pmu_ctr_monitor_instructions(env, ctr_idx))) {
ctrh = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, true);
ctrh = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx);
counter->mhpmcounter_prev = deposit64(counter->mhpmcounter_prev,
32, 32, ctrh);
if (ctr_idx > 2) {
@@ -1399,7 +1390,7 @@ RISCVException riscv_pmu_read_ctr(CPURISCVState *env, target_ulong *val,
*/
if (riscv_pmu_ctr_monitor_cycles(env, ctr_idx) ||
riscv_pmu_ctr_monitor_instructions(env, ctr_idx)) {
*val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx, upper_half) -
*val = riscv_pmu_ctr_get_fixed_counters_val(env, ctr_idx) -
ctr_prev + ctr_val;
} else {
*val = ctr_val;
@@ -3006,7 +2997,6 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
uint32_t present_ctrs = cpu->pmu_avail_ctrs | COUNTEREN_CY | COUNTEREN_IR;
target_ulong updated_ctrs = (env->mcountinhibit ^ val) & present_ctrs;
uint64_t mhpmctr_val, prev_count, curr_count;
uint64_t ctrh;
/* WARL register - disable unavailable counters; TM bit is always 0 */
env->mcountinhibit = val & present_ctrs;
@@ -3022,28 +3012,16 @@ static RISCVException write_mcountinhibit(CPURISCVState *env, int csrno,
counter = &env->pmu_ctrs[cidx];
if (!get_field(env->mcountinhibit, BIT(cidx))) {
counter->mhpmcounter_prev =
riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false);
if (riscv_cpu_mxl(env) == MXL_RV32) {
ctrh = riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true);
counter->mhpmcounter_prev = deposit64(counter->mhpmcounter_prev,
32, 32, ctrh);
}
counter->mhpmcounter_prev = riscv_pmu_ctr_get_fixed_counters_val(env, cidx);
if (cidx > 2) {
riscv_pmu_setup_timer(env, counter->mhpmcounter_val, cidx);
}
} else {
curr_count = riscv_pmu_ctr_get_fixed_counters_val(env, cidx, false);
curr_count = riscv_pmu_ctr_get_fixed_counters_val(env, cidx);
mhpmctr_val = counter->mhpmcounter_val;
prev_count = counter->mhpmcounter_prev;
if (riscv_cpu_mxl(env) == MXL_RV32) {
uint64_t tmp =
riscv_pmu_ctr_get_fixed_counters_val(env, cidx, true);
curr_count = curr_count | (tmp << 32);
}
/* Adjust the counter for later reads. */
mhpmctr_val = curr_count - prev_count + mhpmctr_val;