RISC-V PR for 11.2
* Add experimental Zvabd extension support
* Mask vsepc according to IALIGN
* Reset vCPU on VM reset via MP_STATE_INIT_RECEIVED
* Improve modeling of the Atlantis UART
* Fix IOMMU entry leak with ioatc-limit=0
* Fix integer handling issues in k230_gsdma and k230_decomp_gzip
* Reclaim invalidated IOATC entries for IOMMU
* Duct tape fix for QMP and RV profiles introspection
* Move RISC-V 'Z' CPU properties section to removed features
* Use TSO barriers instead of full barriers for Ztso
* Make mnstatus.MNPELP writable with Zicfilp
* Gate envcfg CBO fields on extensions
* Fix stale PMP state across reset
* Use 1ULL for a value we're going to shift by 63
* Remove unused IMISC macro
* Encode debug translation ranges in IOMMU
* Allow regular mstatus MPV/GVA writes again
* Fix uninitialised upper half in pmu_timer_trigger_irq
* Fix CPU state access on big-endian hosts
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# gpg: Signature made Tue 27 Oct 2026 01:27:12 AM CDT
# gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013
* tag 'pull-riscv-to-apply-20261027' of https://github.com/alistair23/qemu: (29 commits)
target/riscv: Fix CPU state access on big-endian hosts
target/riscv: fix uninitialised upper half in pmu_timer_trigger_irq()
target/riscv/csr.c: allow regular mstatus MPV/GVA writes again
hw/riscv/riscv-iommu: encode debug translation ranges
include/hw/intc/riscv_imsic.h: remove unused macro
target/riscv: Use 1ULL for a value we're going to shift by 63
target/riscv: pmp: reset the derived PMP bounds and rule count
target/riscv: pmp: clear A and L on every implemented PMP entry at reset
target/riscv: gate envcfg CBO fields on extensions
target/riscv: make mnstatus.MNPELP writable with Zicfilp
target/riscv: Use TSO barriers instead of full barriers for Ztso
docs: Move RISC-V 'Z' CPU properties section to removed features
target/riscv/cpu.c: duct tape fix for QMP + RV profiles introspection
hw/riscv/riscv-iommu: reclaim invalidated IOATC entries
hw/riscv/riscv-iommu: serialize IOATC accesses
hw/dma: fix k230_gsdma integer handling issues
qtest: fix k230_decomp_gzip test integer handling issues
hw/misc: use hwaddr for the k230_decomp_gzip input address
hw/misc: fix calculating input address overflow in k230_decomp_gzip
hw/misc: fix calculating output address overflow in k230_decomp_gzip
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Download the firmware and run it on the corresponding DSP machine.
The images are third-party binaries, so the tests run only when untrusted
code is allowed.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Let the hexagon-sim-style machines their QDSP6 subsystem, and with it the
l2vic and QTimer.
The config table's subsystem base is updated to align with the chosen
address.
Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
Add tests for: vallocframe, atomics, trap2, CFI/restricted branches, and
scalar fp instructions.
New instructions not yet supported by the toolchain are manually encoded
with .word directives.
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
SSR.SS enables a single-step debug event after each packet executed in
user or guest mode.
Carry the state in a new SS_ACTIVE TB flag. When it is set, translate
one packet per TB and raise HEX_EVENT_DEBUG w/PC at the next packet (which
becomes ELR).
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
The architecture scrambles only the LR word of the {FP, LR} frame that
allocframe stores. With the idef parser enabled, fFRAME_SCRAMBLE built
the XOR key with FRAMEKEY in both halves of the 64-bit value, so the
stored FP was scrambled as well.
deallocframe is also parser-generated and applies the same incorrect
transform a second time, which masks the error. dealloc_return uses the
hand-written TCG implementation that correctly descrambles only LR, so
it leaves FP corrupt when returning from a frame allocated by the parser.
Add a regression test that sets a nonzero FRAMEKEY, allocates a frame,
and returns through dealloc_return to validate the restored FP.
Uncovered by testing some boot images using QuRT.
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
The debug translation response aligns the translated physical address to
the effective translation range, but always reports S=0. For a request
inside a superpage, the response therefore identifies the wrong 4 KiB
physical page.
For effective ranges larger than 4 KiB, set S and encode the range size
using trailing ones in the PPN field. Keep the existing response format
for 4 KiB translations.
The RISC-V IOMMU specification permits reporting a 4 KiB translation even
when the page tables use superpages. Reporting the effective range is an
implementation choice; this change does not claim that S=1 is mandatory
for every translation through a superpage mapping.
Add debug-response tests for S-stage-only 4 KiB, 64 KiB NAPOT, and 2 MiB
translations, G-stage-only 2 MiB translations, and nested S4K/G2M,
S2M/G4K, and S2M/G2M mappings. Check requests inside large ranges and at
both ends. The mixed nested cases verify that the response uses the
smaller effective translation granularity.
Fixes: a7aa525b93 ("hw/riscv/riscv-iommu: add DBG support")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3552
Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20261022065647.67150-1-fritchleybohrer@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
vsepc is the VS-mode counterpart of sepc and is a WARL register, but
unlike mepc and sepc its accessors do not mask the low address bits
according to IALIGN. As a result, values with invalid low bits can be
observed through vsepc.
Apply get_xepc_mask() to both vsepc reads and writes, matching the
existing mepc/sepc handling.
Add a TCG regression test covering both IALIGN=16 and IALIGN=32.
Fixes: 8747c9eeb2 ("target/riscv: Add Hypervisor virtual CSRs accesses")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4420
Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20260915024945.32329-1-fritchleybohrer@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Add a RV64 TCG test covering the masked and unmasked vector-vector
and vector-scalar forms of vabd, vabdu, vwabda, and vwabdau.
Assemblers do not yet support the version 0.9 instruction mnemonics,
so the instruction encodings are hardcoded for the time being.
GNU binutils 2.47 supports the incompatible version 0.7 instruction
encodings. Therefore, this test must not be built with that version,
even after it is converted to use instruction mnemonics.
Co-Author: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Signed-off-by: Mingliang Liu <liumingliang.dev@bytedance.com>
Tested-by: Chao Liu <chao.liu@processmission.com>
Message-ID: <20261015134337.3354723-4-liumingliang.dev@bytedance.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Currently, we are initializing QOM type after having set target to the
first one available. That's not enough to catch conflicts among types
within targets. Indeed, we'll miss some conflicts since some types are
registered conditionnally through .is_available.
To ensure full coverage, we detect all targets available, and generate a
sub test for each of them. Then, using g_test_trap_subprocess(), we can
recursively call only this test in a children process.
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Link: https://lore.kernel.org/qemu-devel/20261024061616.27381-4-pierrick.bouvier@oss.qualcomm.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Changes:
- [PATCH 0/3] tests/tcg/loongarch64: fix hang with softmmu-gdb-memory (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>)
Link: https://lore.kernel.org/qemu-devel/20261022201733.1941651-1-pierrick.bouvier@oss.qualcomm.com
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# gpg: Signature made Sat 24 Oct 2026 09:10:22 AM CEST
# gpg: using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
# gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 37C1 5694 D8BA 9764 B197 3FDB B444 37D1 9C28 62DF
* tag 'pbouvier/pr/tcg_tests-20261024' of https://gitlab.com/p-b-o/qemu:
tests/tcg: remove global meson variables
tests/tcg/loongarch64/system: reenable gdb-memory test on aarch64 hosts
tests/tcg/loongarch64: restrict gdb tests to gdb >= 16.1
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
testing updates (tcg, gdbstub):
- make sure we have TCG to run test_acpi_bits
- fix overflow in linux-sigrtminmax
- make .dir-locals aware of PYTHONPATH
- detect gdb in top-level meson
- fetch kernel assets with symbols for x86, aarch64 and s390 tuxruns
- use arrays in gdb run-test to make quoting less messy
- add support for --symbols and --kargs to gdbstub run-test.py
- restore old kvm gdb test script with a few fixes
- add tuxrun_kvm_gdb tests for x86,aarch64 and s390
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# gpg: Signature made Fri 23 Oct 2026 06:36:38 PM CEST
# gpg: using RSA key 6685AE99E75167BCAFC8DF35FBD0DB095A9E2A44
# gpg: Good signature from "Alex Bennée (Master Work Key) <alex.bennee@linaro.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6685 AE99 E751 67BC AFC8 DF35 FBD0 DB09 5A9E 2A44
* tag 'pull-11.2-gdbstub-kvm-231026-1' of https://gitlab.com/stsquad/qemu:
tests/functional: add tuxrun kvm gdb test for s390x
tests/functional: update s390x tuxrun images
tests/functional: split s390x tuxrun into tcg and kvm run
tests/functional: add tuxrun kvm gdb test for arm64
tests/functional: update arm64 tuxrun images
tests/functional: split aarch64 tuxrun into tcg and kvm run
tests/functional: add tuxrun kvm gdb test for x86_64
tests/functional: teach tuxrun about launching gdb tests
tests/guest-debug: add --symbols option to run-test
tests/guest-debug: add --kargs option to run-test
tests/guest-debug: convert cmd to an qemu_cmd array
tests/guest-debug: convert gdb_cmd to an array
tests/functional: update x86_64 tuxrun images
tests/functional: split x86_64 tuxrun into tcg and kvm run
tests/functional: allow tuxrun tests to be passed "accel"
meson: move gdb detection into the top level build file
.dir-locals: include QEMU code in PYTHONPATH
tests/tcg: fix buffer overflow in multiarch/linux/linux-sigrtminmax
tests/functional: test_acpi_bits requires TCG
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
When writing the conversion, I tried to factorize some definitions
between linux-user and softmmu and variants of a target. Unfortunately,
as meson has (sadly) no support for local variables, this required to
use global variables.
As a consequence, those variables are also exposed between targets, and
this resulted in some entries being wrongly set (cc_feat_cflags or
gdb_feat_version, for instance, wrongly set on target not defining
them).
Being bitten by this while writing the two previous patches, I decided
it was time to clean this up and not rely on global variables.
This patch inlines required entries directly in test suite definition.
Change is correct since all keys modified here are checked during meson
configuration, so we can't forget a definition.
Link: https://lore.kernel.org/qemu-devel/20261022201733.1941651-4-pierrick.bouvier@oss.qualcomm.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
As with x86_64 we now have the bits to add a KVM gdb test. A couple of
minor wrinkles need to be handled.
The first is applying an offset when loading the symbols to take into
account the relocation that happens.
The other minor wrinkle is the s390x only supports WP_WRITE watch
points so we skip the other watch point tests lest we get confusing
messages about failing to insert HW breakpoints.
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20261019192704.3220373-20-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
This resurrects the hand run test script from d84842be6c (tests:
remove test-gdbstub.py) and modernises it to use the shared test
infrastructure for run-test.
We then tweak the common tuxrun code to offer an alternative "launch
via gdbstub" helper which reuses the existing code but:
- needs a vmlinux with symbols
- drops kaslr because it doesn't play nice with symbols
- extend qargs with stuff normally added by vm.launch
- passes kargs directly
- runs with the gdb run-test script
- log the run-test output to the console log
- makes --binary not mandatory
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20261019192704.3220373-13-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
As with gdb_cmd passing a plain string to a subprocess involves making
sure the escaping is correct so the underlying shell doesn't get
confused. Do the same as gdb_cmd and make the whole thing an array.
There are a few minor wrinkles with when args.binary is expected so
add some comments for that.
Suggested-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20261019192704.3220373-10-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Passing a plain string to subprocess involves making sure the escaping
is correct so the underlying shell doesn't get confused. This can be
tricky to track across multiple processes. To simplify this build the
command as an array and execute gdb directly without involving the
shell.
We add a mini-helper to make the log output a bit more copy and paste
friendly.
Suggested-by: Ilya Leoshkevich <iii@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Message-ID: <20261019192704.3220373-9-alex.bennee@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
The original Allwinner GPIO implementation assumed pin had to be
configured as input (CFG 0x0) in order to be able to handle interrupts
on interrupt-capable pins.
However, libgpiod configures those pins in EINT mode (CFG 0x06) when
gpiomon is used, so this patch fixes interrupt path to expect pin
configuration to be set to EINT.
Also update interrupt handling tests for the correct functionality.
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Message-id: 20261017-allwinner-gpio-eint-v2-1-82906f440378@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Extend test_arm_raspi4_initrd to exercise the RNG200 and thermal
sensor devices added in this series: confirm the RNG200 driver probes
it ("hwrng registered" in the kernel log), then once at a shell
confirm the thermal zone reports the expected fixed reading and that
/dev/hwrng actually yields data rather than just existing.
These checks go into the existing initrd boot test rather than a new
test, to avoid spending test time booting the same kernel again.
Verified locally against this series with the exact kernel/initrd
assets this file already pins.
Signed-off-by: Marcelo Manzo <marcelomanzo@gmail.com>
Message-id: 20261015181111.60491-6-marcelomanzo@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
There is an oddity that turns up with the float_convd and float_convs
tests, when running from different toolchains. As one example, the
expectation at the start of tests/tcg/ppc64/float_conv*.ref is:
### Rounding to nearest
from double: f64(nan:0x007ff4000000000000)
to single: f32(nan:0x7fe00000) (INVALID)
to int32: -2147483648 (INVALID)
to int64: -9223372036854775808 (INVALID)
to uint32: 0 (INVALID)
to uint64: -9223372036854775808 (INVALID)
But, other hosts offer a different response, e.g., this debian guest
on my laptop:
### Rounding to nearest
from double: f64(nan:0x007ff4000000000000)
to single: f32(nan:0x7fe00000) (INVALID)
to int32: -2147483648 (INVALID)
to int64: -9223372036854775808 (INVALID)
to uint32: 0 (INVALID)
to uint64: 0 (INVALID)
The explanation seems to be a behavior change when compiling to different
versions of power hardware. When building the arguments from the multiarch
directory, let's ensure these float tests offer a deterministic response
to these NaN tests by explicitly binding them to a CPU architecture.
Chose power8 for no real reason. This behavior change appears between
power6 and power7, but other tests that rely on a specific architecture
today pick either power8 or power10.
Signed-off-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/20261019185600.2031729-3-farman@linux.ibm.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Check guest-visible state for OHCI transfers whose ED type disagrees with
the endpoint type. Successful control and isochronous transfers exercise
the same endpoint paths, ruling out inactive endpoints or an idle schedule.
Signed-off-by: Junjie Cao <junjie.cao@intel.com>
Message-ID: <20261017062048.610930-1-junjie.cao@linux.dev>
Signed-off-by: Thomas Huth <thuth@redhat.com>
Add "race/tread-dir" test, a test racing legacy (9p2000.u)
Tread requests against each other on the same directory FID.
This test guards the previous fix patch ("hw/9pfs: fix dirent
stream protection for legacy (9p2000.u) Tread").
In each round a configurable number (V9FS_RACE_NCONCURRENT) of
concurrent Tread requests are issued against each other, verifying
that every Tread response lists the same (leading) directory entries
as a reference directory entry list taken before the actual
concurrent Tread request sequence starts.
A vulnerable server would return directory entries either with
corrupted entry names, or entries in varying order, or even crash
the QEMU process due to garbage dirent seek targets.
This test is explicitly using a 9p2000.u session, as Tread on
directories is not a 9p2000.L feature (the latter uses Treaddir
instead).
This test is registered as slow test (i.e. skipped by default) and
therefore requires -m slow to run.
On my test machine a full run of 20000 rounds took around 5 minutes
to complete.
Link: https://lore.kernel.org/qemu-devel/39f9fb4e48dfd08ed6d05519be5a28898a3bf872.1791368962.git.qemu_oss@crudebyte.com
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
So far v9fs_tattach() always sent an implied Tversion request, which
was supposed to be a convenient mechanisms such that not every test
case code would need to call v9fs_tversion() prior to a
v9fs_tattach(). The problem however is that this implicit Tversion
defaults to 9p2000.L, and it would also be (re)sent if an explicit
v9fs_tversion() call had been issued with 9p2000.u before, which then
would reset the session to the unintended 9p2000.L protocol version.
Fix this by storing the initial Tversion request's (desired) protocol
version to the client object. And only issue the implicit Tversion
request inside of v9fs_tattach() if no protocol version had been
negotiated already.
This is a preparatory patch for the subsequently added race test,
which negotiates a 9p2000.u session.
It also allows request / response handling to later become more
protocol dialect aware (e.g. expecting specific request / response
types according to negotiated protocol version during a session).
Link: https://lore.kernel.org/qemu-devel/419b2b047c0f61b9e4a7e58f117c03ec6feea1ea.1791368962.git.qemu_oss@crudebyte.com
Signed-off-by: Christian Schoenebeck <qemu_oss@crudebyte.com>
Richard Henderson