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Zephyr Li
9b6fc2a751
vsepc is the VS-mode counterpart of sepc and is a WARL register, but
unlike mepc and sepc its accessors do not mask the low address bits
according to IALIGN. As a result, values with invalid low bits can be
observed through vsepc.
Apply get_xepc_mask() to both vsepc reads and writes, matching the
existing mepc/sepc handling.
Add a TCG regression test covering both IALIGN=16 and IALIGN=32.
Fixes: 8747c9eeb2 ("target/riscv: Add Hypervisor virtual CSRs accesses")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4420
Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20260915024945.32329-1-fritchleybohrer@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>