968 Commits
Author SHA1 Message Date
Richard Henderson d29412cca5 Merge tag 'pull-riscv-to-apply-20261027' of https://github.com/alistair23/qemu into staging
RISC-V PR for 11.2

* Add experimental Zvabd extension support
* Mask vsepc according to IALIGN
* Reset vCPU on VM reset via MP_STATE_INIT_RECEIVED
* Improve modeling of the Atlantis UART
* Fix IOMMU entry leak with ioatc-limit=0
* Fix integer handling issues in k230_gsdma and k230_decomp_gzip
* Reclaim invalidated IOATC entries for IOMMU
* Duct tape fix for QMP and RV profiles introspection
* Move RISC-V 'Z' CPU properties section to removed features
* Use TSO barriers instead of full barriers for Ztso
* Make mnstatus.MNPELP writable with Zicfilp
* Gate envcfg CBO fields on extensions
* Fix stale PMP state across reset
* Use 1ULL for a value we're going to shift by 63
* Remove unused IMISC macro
* Encode debug translation ranges in IOMMU
* Allow regular mstatus MPV/GVA writes again
* Fix uninitialised upper half in pmu_timer_trigger_irq
* Fix CPU state access on big-endian hosts

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# gpg: Signature made Tue 27 Oct 2026 01:27:12 AM CDT
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20261027' of https://github.com/alistair23/qemu: (29 commits)
  target/riscv: Fix CPU state access on big-endian hosts
  target/riscv: fix uninitialised upper half in pmu_timer_trigger_irq()
  target/riscv/csr.c: allow regular mstatus MPV/GVA writes again
  hw/riscv/riscv-iommu: encode debug translation ranges
  include/hw/intc/riscv_imsic.h: remove unused macro
  target/riscv: Use 1ULL for a value we're going to shift by 63
  target/riscv: pmp: reset the derived PMP bounds and rule count
  target/riscv: pmp: clear A and L on every implemented PMP entry at reset
  target/riscv: gate envcfg CBO fields on extensions
  target/riscv: make mnstatus.MNPELP writable with Zicfilp
  target/riscv: Use TSO barriers instead of full barriers for Ztso
  docs: Move RISC-V 'Z' CPU properties section to removed features
  target/riscv/cpu.c: duct tape fix for QMP + RV profiles introspection
  hw/riscv/riscv-iommu: reclaim invalidated IOATC entries
  hw/riscv/riscv-iommu: serialize IOATC accesses
  hw/dma: fix k230_gsdma integer handling issues
  qtest: fix k230_decomp_gzip test integer handling issues
  hw/misc: use hwaddr for the k230_decomp_gzip input address
  hw/misc: fix calculating input address overflow in k230_decomp_gzip
  hw/misc: fix calculating output address overflow in k230_decomp_gzip
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2026-10-27 14:27:13 -05:00
Brian Cain ef328b0c21 Hexagon: add v85 CPU model
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
2026-10-27 07:23:27 -07:00
Portia Stephens fd559e1273 docs/atlantis: Update Atlantis UART documentation
Update Atlantis documentation to describe the DesignWare UART used.

Signed-off-by: Portia Stephens <portias@oss.tenstorrent.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20261015002849.1640109-4-portias@oss.tenstorrent.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-10-26 11:15:06 +10:00
Luigi Leonardi edd5339a08 docs/system/igvm: document MADT, COMMAND_LINE and DEVICE_TREE directives
The MADT and DEVICE_TREE directives were added without updating the
list of supported directives. Document them, together with the
COMMAND_LINE directive added in the previous patch.

Suggested-by: Stefano Garzarella <sgarzare@redhat.com>
Signed-off-by: Luigi Leonardi <leonardi@redhat.com>
Reviewed-by: Stefano Garzarella <sgarzare@redhat.com>
Message-ID: <20261019-igvm_command_line-v3-2-29aeacbd6cd7@redhat.com>
Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
2026-10-21 18:26:46 +02:00
Richard Henderson 62c31d1b6a Merge tag 'pull-riscv-to-apply-20261016' of https://github.com/alistair23/qemu into staging
RISC-V PR for 11.2

* Check G-stage write permission for VS-stage A/D updates
* Restore LCOFI handling in interrupt CSRs
* Fix csrrs disasembly decoding
* Stop translating after WFI
* Raise virtual instruction exception on svinval instructions
* Fix some KVM migration issues
* Add support for Milk-V Duo board
* Make MIP accesses atomic and BQL-safe
* Add initial sdext support
* Add SiFive Xsfvqmaccdod/Xsfvqmaccqoq int8 matmul extensions
* Add the Server Platform Reference Board
* Revert invalidate reservations after stores for linux user
* Fix the UART register width in SPCR
* Check Svnapot PTE before updating A/D bits
* Add Tenstorrent Atlantis PRCM model
* Fix RV32 fixed counter accesses
* Write back fsgnjn.h and fsgnjx.h results
* Ensure Zcmt jvt.mode is WARL

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# gpg: Signature made Fri 16 Oct 2026 03:02:07 AM CEST
# gpg:                using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65  9296 AF7C 9513 0C53 8013

* tag 'pull-riscv-to-apply-20261016' of https://github.com/alistair23/qemu: (50 commits)
  target/riscv: normalize Zcmt jvt.mode on writes
  target/riscv: write back fsgnjn.h and fsgnjx.h results
  target/riscv: fix RV32 fixed counter accesses
  hw/riscv/tt-atlantis: Update UART and I2C to use clk from PRCM
  hw/riscv/tt-atlantis: Add PRCMs to tt-atlantis model
  hw/misc: Add Tenstorrent Atlantis PRCM model
  target/riscv: Check Svnapot PTE before updating A/D bits
  tests/qtest/bios-tables-test: Update riscv64 virt SPCR golden reference
  hw/riscv/virt-acpi-build: Fix the UART register width in SPCR
  tests/qtest/bios-tables-test: Allow changes to riscv64 virt SPCR
  Revert "linux-user/riscv: invalidate reservations after stores"
  docs: add riscv-server-ref.rst
  tests/functional/riscv64: add riscv-server-ref tests
  hw/riscv: server platform reference machine
  target/riscv: add riscv-server-ref CPU
  target/riscv/cpu.c: remove 'bare' condition for .profile
  tests/tcg/riscv64: Add tests for SiFive int8 matmul extensions
  disas/riscv: Add disassembler support for Xsfvqmaccdod/Xsfvqmaccqoq
  target/riscv: rvv: Add SiFive custom int8 matmul instructions
  target/riscv/cpu: Add SiFive custom int8 matmul extension implied rules
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2026-10-16 06:09:05 +02:00
Anirudh Srinivasan 5fa42544d8 hw/riscv/tt-atlantis: Add PRCMs to tt-atlantis model
Atlantis has 4 PRCMs that are visible from S mode by the Ascalon Core
(RCPU, HSIO, PCIe and MM). The remaining 2 are only accessed by the
boot cpu which isn't modelled yet.

This commit adds these 4 PRCM blocks to the tt-atlantis model, along
with necessary device tree nodes for them.

Reviewed-by: Chao Liu <chao.liu@processmission.com>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Anirudh Srinivasan <asrinivasan@oss.tenstorrent.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20261001-atlantis_prcm-v4-2-95d33c470eeb@oss.tenstorrent.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-10-16 10:40:39 +10:00
Daniel Henrique Barboza bde97423bb docs: add riscv-server-ref.rst
Add documentation for the new riscv-server-ref board.

Signed-off-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Chao Liu <chao.liu@processmission.com>
Reviewed-by: Sunil V L <sunilvl@oss.qualcomm.com>
Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Message-ID: <20260928201107.2049458-6-daniel.barboza@oss.qualcomm.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-10-16 10:40:38 +10:00
Kuan-Wei Chiu 14812062ac docs/system/riscv: Add Milk-V Duo board documentation
Add documentation for the Milk-V Duo board. This includes a brief
overview of the hardware, a list of supported devices, and practical
instructions on how to boot the machine using OpenSBI and a Linux
kernel with an emulated SD card.

Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20260927201326.650943-8-visitorckw@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-10-16 10:40:38 +10:00
Richard Henderson 44a4915203 target/arm: Enable FEAT_IDTE3 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20261010070952.323466-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-10-15 17:38:38 +01:00
Richard Henderson 8ee6c77176 Merge tag 'pull-ufs-20261012' of https://gitlab.com/jeuk20.kim/qemu into staging
ufs queue

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# gpg: Signature made Mon 12 Oct 2026 12:51:45 PM CEST
# gpg:                using RSA key 5017D831597C78A3D907EEF712E2204C0E5DB602
# gpg: Good signature from "Jeuk Kim <jeuk20.kim@samsung.com>" [unknown]
# gpg:                 aka "Jeuk Kim <jeuk20.kim@gmail.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 5017 D831 597C 78A3 D907  EEF7 12E2 204C 0E5D B602

* tag 'pull-ufs-20261012' of https://gitlab.com/jeuk20.kim/qemu:
  docs/system: Add UFS emulation page
  hw/ufs: Skip nullified MCQ submission queue entries with OCS_ABORTED
  hw/ufs: Implement Task Management Request (TMR) handling
  hw/ufs: Support MCQ runtime interrupt and queue status registers
  hw/ufs: Track SCSIRequest and cancel pending requests in ufs_clear_req

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2026-10-13 22:01:07 +02:00
Stanley Jhu c44c626e28 docs/system: Add UFS emulation page
The UFS host controller and logical unit devices have no user
documentation. Their properties and the way the two devices fit
together can only be found by reading hw/ufs/.

Add docs/system/devices/ufs.rst with an example command line, the
device properties, and current limitations, and list it under the UFS
entry in MAINTAINERS.

Signed-off-by: Stanley Jhu <stanleyjhu@google.com>
Reviewed-by: Jeuk Kim <jeuk20.kim@samsung.com>
Signed-off-by: Jeuk Kim <jeuk20.kim@samsung.com>
2026-10-12 19:50:56 +09:00
Brian Cain 2633da1e12 target/hexagon: add the QFloat logic
Add routines to handle QFloat/HVX floating point values.

Also: add documentation to describe the feature.

Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
2026-10-11 21:09:30 -07:00
Richard Henderson f7ada39eda Merge tag 's390x-20260930' of https://gitlab.com/efarman/qemu into staging
New s390x features for 11.2
 - enable boot via virtio-net-pci
 - PCI and SCLP fixes
 - hardening fixes throughout
 - regenerate s390-ccw.img

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# gpg: Signature made Wed 30 Sep 2026 04:17:36 PM BST
# gpg:                using EDDSA key 01DC385BC24E19137B9437A2A64F1E11E05C77B4
# gpg:                issuer "farman@linux.ibm.com"
# gpg: Good signature from "Eric Farman <farman@linux.ibm.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: D2C6 0504 C9E8 F568 CFE5  87B5 3827 B212 71BF 9562
#      Subkey fingerprint: 01DC 385B C24E 1913 7B94  37A2 A64F 1E11 E05C 77B4

* tag 's390x-20260930' of https://gitlab.com/efarman/qemu: (23 commits)
  pc-bios/s390-ccw.img: update s390x bios
  s390x/pci: Reject apertures beyond IOAT capacity in translation mode
  s390x/pci: Use qemu_log_mask() for guest-triggered errors in reg_ioat()
  s390x/pci: Fix frame stepping in rpcit_service_call()
  s390x/sclpconsole: fix indentation for console_reset
  tests/functional/s390x: Add tests for virtio net PCI in test_pxelinux.py
  tests/qtest: Add s390x virtio net PCI test to pxe-test.c
  tests/qtest: Check s390x boot device support in pxe-test.c
  hw/virtio: Add "loadparm" property to virtio net PCI devices booting on s390x
  pc-bios/s390-ccw: Add support for virtio-net-pci IPL
  pc-bios/s390-ccw: Introduce virtio_tswap helpers
  pc-bios/s390-ccw: Add dynamic net header size handling
  pc-bios/s390-ccw: Move CCW net setup to virtio-ccw
  s390x: Expose pv attribute in QOM
  s390x/sclp: Reject short headers in PV case
  s390x/css: Use datastream pointer for checking no-data CCWs
  hw/intc/s390x: Fix check after g_try_realloc
  hw/intc/s390x: Fix payload to KVM_HAS_DEVICE_ATTR ioctl
  vfio/ccw: Clear error object pointer after non-fatal errors
  vfio/ap: Clear error object pointer after non-fatal errors
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2026-09-30 16:44:59 +01:00
Peter Xu 7ca43d7ad0 hostmem: Support fully shared guest memfd to back a VM
Host backends supports guest-memfd now by detecting whether it's a
confidential VM.  There's no way to choose it yet from the memory level to
use it fully shared.  If we use guest-memfd, it so far always implies we
need two layers of memory backends, while the guest-memfd only provides the
private set of pages.

This patch introduces a way so that QEMU can consume guest memfd as the
only source of memory to back the object (aka, fully shared).

To use the fully shared guest-memfd, one can add a memfd object with:

  -object memory-backend-memfd,x-guest-memfd=on,share=on

Note that share=on is required with fully shared guest_memfd.

Since guest-memfd is not yet a drop-in replacement for memfd (e.g. lack
of hugepage support), the option is tagged as experimental for now so
that it can be made available for early enablement/testing without
causing any surprises for other users.

PS: there's a trivial touch-up on fd<0 check, because the stub to create
guest-memfd may return negative but not -1.

Reviewed-by: Xiaoyao Li <xiaoyao.li@intel.com>
Reviewed-by: Fabiano Rosas <farosas@suse.de>
Reviewed-by: David Hildenbrand <david@kernel.org>
Co-developed-by: Michael Roth <michael.roth@amd.com>
Signed-off-by: Michael Roth <michael.roth@amd.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Link: https://lore.kernel.org/r/20260929235109.1398509-11-michael.roth@amd.com
Signed-off-by: Peter Xu <peterx@redhat.com>
2026-09-30 08:51:04 -04:00
Richard Henderson 041db76ebb target/arm: Enable FEAT_UINJ for -cpu max-v9
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-id: 20260925215004.456336-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-29 10:58:40 +01:00
Strahinja Jankovic cc69b73a70 hw/arm: Add GPIO to Allwinner A10 model
The Allwinner A10 GPIO is added to the Allwinner A10
description, so it is available when Cubieboard is emulated.

Update the documentation for Cubieboard to indicate GPIO availability.

Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260915-allwinner-gpio-v4-2-b1ee1d09c9fd@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-28 13:39:51 +01:00
Janosch Frank 964a49b6b7 s390x: Expose pv attribute in QOM
People doing VM management requested a way to query if a VM is in PV
or not. So this patch exposes the runtime PV attribute which is true
once the VM successfully made the switch into PV mode (according to
KVM) and did not yet reboot to drop out of it.

This of course does never replace attestation, it's merely QEMU's view
of the situation.

Signed-off-by: Janosch Frank <frankja@linux.ibm.com>
CC: Hendrik Brueckner <brueckner@linux.ibm.com>
Reviewed-by: Christian Borntraeger <borntraeger@linux.ibm.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Reviewed-by: Hendrik Brueckner <brueckner@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260924142846.157848-1-frankja@linux.ibm.com
Signed-off-by: Eric Farman <farman@linux.ibm.com>
2026-09-25 08:28:56 -04:00
Harald Freudenberger 33581dc492 docs/s390: Document CPACF instructions support
Add a first document covering the Qemu s390 CPACF instructions
and functions supported.

Signed-off-by: Harald Freudenberger <freude@linux.ibm.com>
Reviewed-by: Finn Callies <fcallies@linux.ibm.com>
Reviewed-by: Ilya Leoshkevich <iii@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260824083204.40877-20-freude@linux.ibm.com
[farman@linux.ibm.com: Resolve merge conflict in target-s390x.rst]
Signed-off-by: Eric Farman <farman@linux.ibm.com>
2026-09-21 05:58:38 -04:00
Daniel P. Berrangé 769ccabcd3 docs: expand security docs with info about security status
The description of virtualization vs non-virtualization use
cases is a crude approximation of the security characteristics
of QEMU devices.

Document how QEMU can be probed to obtain information on the
security status of type classes, and how policies can be set
to inform or control their usage.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2026-09-17 17:00:44 +01:00
Richard Henderson d43c2d5f89 Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging
pci, vhost, virtio, iommu, apci: features, fixes

new vhost-user-media device
virtio-net now supports live-TAP local migration
cxl now supports CFMW restrictions and per-window options
intel_iommu now supports concurrent page fault handling with PRI
pci now batches memory transactions around mapping updates
vhost-user-blk now allows toggling inflight-migration at runtime
virtio-rtc now supports smeared UTC clock type
intel_iommu now exposes SMPWC when SVM is enabled
new reviewer for CXL patches

Fixes, cleanups all over the place

Signed-off-by: Michael S. Tsirkin <mst@redhat.com>

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# gpg: Signature made Fri 11 Sep 2026 09:57:09 AM HST
# gpg:                using RSA key 5D09FD0871C8F85B94CA8A0D281F0DB8D28D5469
# gpg:                issuer "mst@redhat.com"
# gpg: Good signature from "Michael S. Tsirkin <mst@kernel.org>" [unknown]
# gpg:                 aka "Michael S. Tsirkin <mst@redhat.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 0270 606B 6F3C DF3D 0B17  0970 C350 3912 AFBE 8E67
#      Subkey fingerprint: 5D09 FD08 71C8 F85B 94CA  8A0D 281F 0DB8 D28D 5469

* tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu: (74 commits)
  MAINTAINERS: add Junjie Cao as CXL reviewer
  vhost-user-blk: use GET_VRING_BASE_SKIP_DRAIN when inflight-migration is on
  vhost-user-blk: move inflight_needed higher
  vhost-user-blk: make inflight-migration prop mutable on running vm
  vhost-user: use skip_drain with GET_VRING_BASE_SKIP_DRAIN message
  vhost-user: add GET_VRING_BASE_SKIP_DRAIN message
  vhost-user: add skip_drain param to do_vhost_virtqueue_stop
  intel_iommu: Expose SMPWC when SVM is enabled
  virtio-net: validate IHL in virtio_net_rsc_extract_unit4 before use
  net/tap-solaris: Fix resource leaks on error paths
  hw/hotplug: Constify HotplugHandler
  hw/hotplug: Reduce some HotplugHandler variables scope
  hw/hotplug: Mark various HotplugHandlerClass variables as const
  hw/acpi: Make AcpiGedState const in build_ged_aml()
  pci: load a device's config inside one memory transaction
  pci: batch BAR remapping into one memory transaction
  intel_iommu: Always write all the flags passed to vtd_set_flag_in_pte
  intel_iommu: Only set dirty bit when PTE exposes write permission
  intel_iommu: Support concurrent page fault handling with PRI
  virtio-rtc: Report smeared UTC clock type
  ...

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2026-09-11 12:04:42 -10:00
Davidlohr Bueso cb52f088f2 hw/cxl: Add configurable CXL Fixed Memory Window restriction flags
Expose the CFMWS "Window Restrictions" (CXL r4.0 9.18.1.3) as named
per-window machine properties -- device-coherent, host-only, volatile,
persistent, fixed-config and back-invalidate -- so the advertised
restrictions can be configured per window rather than left at the
default.

No changes in default options.  HDM-D and HDM-H are advertised by default;
disabling one (device-coherent=off or host-only=off) narrows the window to
the other.  back-invalidate implies device-coherent (HDM-DB) and suppresses
the host-only default.  host-only coherent combined with back-invalidate is
rejected as undefined behavior per the spec.

Signed-off-by: Davidlohr Bueso <dave@stgolabs.net>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20260720233242.901544-5-dave@stgolabs.net>
2026-09-11 15:54:46 -04:00
Brian Cain 8acc03787b docs: Correct semihost spec URL
The previous URL worked at the time of submission but it appears that it
was not a portable, durable reference.

This one should work better.

Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com>
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
2026-09-11 07:29:10 -07:00
Vladimir Sementsov-Ogievskiy 3e4c54739a net/tap: deprecate "no" as special value for script/downscript
The interface is ambiguous, as "no" is valid file name. So,
using "no" as a special value to disable script is deprecated.
Use an empty string ("script=" / "downscript=") instead.

In a future version, "no" will be treated as a plain file name, just
like any other non-empty value.

Document the deprecation in docs/about/deprecated.rst, qapi/net.json,
and qemu-options.hx. Update other docs to use empty string instead of
"no". Add a warning.

Signed-off-by: Vladimir Sementsov-Ogievskiy <vsementsov@yandex-team.ru>
Reviewed-by: Ben Chaney <bchaney@akamai.com>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Message-ID: <20260819180201.1970193-4-vsementsov@yandex-team.ru>
2026-09-11 04:07:17 -04:00
Daniel P. Berrangé 0766e83d2f docs/system/security: exclude uninitialized stack variables as bugs
The -ftrivial-auto-var-init=zero usage guarantees implicit zero
initializers for all stack variables. Thus most bug reports relying
on undefined behaviour from lack of variable initialization will
not be security issues, or even bugs.

Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
2026-09-07 11:31:03 +01:00
Peter Maydell c513597761 Merge tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu into staging
semihosting, fix exc/int, icinva, TLB, htid

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# gpg:                 aka "Brian Cain <bcain@kernel.org>" [full]
# gpg:                 aka "Brian Cain (QuIC) <bcain@quicinc.com>" [full]
# gpg:                 aka "Brian Cain (CAF) <bcain@codeaurora.org>" [full]
# gpg:                 aka "bcain" [full]
# gpg:                 aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF  49E0 175C 464E 541B 6D47
#      Subkey fingerprint: 3D66 AAE4 7459 4824 C88C  E0F8 1A54 AFB8 E564 6C32

* tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu: (28 commits)
  hw/hexagon: decode an empty TLB size field as 4KB
  hw/hexagon: assign a distinct htid to each DSP machine CPU
  tests/tcg/hexagon: add icinva test
  target/hexagon: invalidate translated code for user icinva
  tests/functional/hexagon: update to v0.2.12, +test_{interrupts, sys_regs}
  target/hexagon: fix iassign{r, w} to cover all threads
  target/hexagon: implement direct-to-guest interrupt delivery
  target/hexagon: raise imprecise exception on multi-TLB match
  target/hexagon: read UTIMERLO/UTIMERHI from the global timer
  target/hexagon: gate GPCYCLE guest register reads on SSR:CE
  target/hexagon: take BQL when reading the system pcycle count
  target/hexagon: guard writes to unimplemented guest registers
  hw/intc: clear pending bit on l2vic de-assertion
  tests/tcg/hexagon: check priv instructions raise SIGILL
  target/hexagon: align exceptions for user/sysemu
  tests/functional: Add hexagon semihosting systests
  python/machine: support routing semihosting output to the test console
  target/hexagon: Add an errno mapping
  target/hexagon: add COREDUMP semihosting operation
  target/hexagon: add main arch-specific semihosting operations
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	hw/hexagon/hexagon_tlb.c
2026-09-02 17:59:30 +01:00
Matheus Tavares Bernardino d3cf03b93e target/hexagon: add semihosting support
Baremetal Hexagon programs use trap0 #0 to invoke
semihosting calls for I/O and process control.  Wire up the
arm-compatible semihosting framework for softmmu by enabling
CONFIG_ARM_COMPATIBLE_SEMIHOSTING and routing trap0 to the
semihosting handler.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Signed-off-by: Matheus Tavares Bernardino <matheus.bernardino@oss.qualcomm.com>
checkpatch: style fixes.
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
2026-09-01 18:20:10 -07:00
Richard Henderson 90789a83fb target/arm: Enable FEAT_SVE_AES2 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260826174213.614571-26-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-01 13:44:13 +01:00
Richard Henderson cbdbd91771 target/arm: Implement and enable FEAT_SSVE_BitPerm for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260826174213.614571-20-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-01 13:44:13 +01:00
Richard Henderson 44230b9fc5 target/arm: Enable FEAT_SVE_BFSCALE for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260826174213.614571-15-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-01 13:44:13 +01:00
Richard Henderson 85d508c1fc target/arm: Enable FEAT_SVE2p2 and FEAT_SME2p2 for -cpu max
These features are tied together if both SVE and SME are enabled.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260826174213.614571-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-01 13:44:12 +01:00
Richard Henderson 9b3e7f881b target/arm: Enable FEAT_FGWTE3 for -cpu max
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260806172709.333300-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-01 13:44:12 +01:00
Richard Henderson 29a92d9861 target/arm: Separate cpu types max-v8 and max-v9
Do not include v9-only features in "max-v8".
Do not include the prohibited v8 features in "max-v9".
In aarch64 tcg mode, define "max" as "max-v9".

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260827041557.775080-7-richard.henderson@linaro.org
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-01 11:15:20 +01:00
Simon Xu 48ed36e055 hw/arm/mps2-tz.c add Arm mps3-an555 board
Add mps3-an555 board modeled after the existing mps3-an547 board.
Add UnimplementedDeivceState for timing adapters and qspi controllers
in MPS2TZMachineState.

Changes in AN555:
Timing adapters in APB PPC EX0 instead of MPC.
Additional QSPI controllers in AHB PPC EX0.
Additional AHB PPC EX1 with DMA.
Create standalone unimplemented devices for MPC instead of timing adapters.
Set fpgaio_has_gpioalt2 to true.

Include documentation for SSE-310 and mps3-an555.

Arm mps3-an555 TRM: https://developer.arm.com/documentation/107642/latest/

As our M85 model doesn't yet have PACBTI, note this omission
in the documentation of where we deviate from the real AN555.

Reviewed-by: Owen Giles <owen.giles@hpe.com>
Reviewed-by: Robert Elliott <elliott@hpe.com>
Signed-off-by: Simon Xu <simonxhy0404@gmail.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-Id: <20260805153005.9989-9-simonxhy0404@gmail.com>
[PMM: added doc note about PACBTI]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-09-01 11:15:20 +01:00
Peter Maydell ad64baf49d hw/arm: Remove the 'musicpal' machine
The 'musicpal' machine emulates the Freecom MusicPal, which was an
"internet radio" released in the mid-2000s.  The stock system used a
2.6.16 Linux kernel, but as far as I'm aware, support for the
hardware was never upstreamed to the mainline kernel.

There are a number of reasons for deprecating this board:
 * The hardware is now solidly obsolete
 * It was never supported in mainline Linux
 * The SoC is a Marvell one with no public datasheet
 * The only QEMU changes to it have been the usual tree wide
   updates and refactoring work
 * The only bug report we've ever had about it has been one of
   the usual "bug found by static analysis" kind

But in fact we can just drop it immediately, because in commit
59754f85ed ("target/arm: Do memory type alignment check when
translation disabled") in 2024 we broke the boot of the standard
firmware image for this board.  (The image's u-boot does a LDRH to an
unaligned address, which is UNPREDICTABLE; we used to let it through,
but that commit makes it take a Data Abort, so the image crashes
before it boots the kernel.) Since nobody complained, we can deduce
that nobody's actually using this machine.

Remove the machine proper, and note this in the docs.  Devices used
only by this board will be removed in subsequent commits.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Acked-by: Jan Kiszka <jan.kiszka@web.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-id: 20260819185430.3467629-4-peter.maydell@linaro.org
2026-09-01 11:15:20 +01:00
Zhuoying Cai 18916df8b6 docs/system/s390x: Add secure IPL documentation
Add documentation for secure IPL

Signed-off-by: Collin Walling <walling@linux.ibm.com>
Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Joshua Daley <jdaley@linux.ibm.com>
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260730214624.2328883-34-zycai@linux.ibm.com
Signed-off-by: Eric Farman <farman@linux.ibm.com>
2026-08-26 06:52:20 -04:00
Zhuoying Cai fd76419574 pc-bios/s390-ccw: Handle true secure IPL mode
When secure boot is enabled (-secure-boot on) and certificate(s) are
provided, the boot operates in True Secure IPL mode.

Any verification error during True Secure IPL mode will cause the
entire boot process to terminate.

Secure IPL in audit mode requires at least one certificate provided in
the key store along with necessary facilities. If secure boot is enabled
but no certificate is provided, the boot process will also terminate, as
this is not a valid secure boot configuration.

Note: True Secure IPL mode is implemented for the SCSI scheme of
virtio-blk/virtio-scsi devices.

Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Collin Walling <walling@linux.ibm.com>
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260730214624.2328883-30-zycai@linux.ibm.com
Signed-off-by: Eric Farman <farman@linux.ibm.com>
2026-08-26 06:52:20 -04:00
Zhuoying Cai d3f59e1f8f Add secure-boot to s390-ccw-virtio machine type option
Add secure-boot as a parameter of s390-ccw-virtio machine type option.

The `secure-boot=on|off` parameter is implemented to enable secure IPL.

By default, secure-boot is set to false if not specified in
the command line.

Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Collin Walling <walling@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260730214624.2328883-28-zycai@linux.ibm.com
Signed-off-by: Eric Farman <farman@linux.ibm.com>
2026-08-26 06:52:20 -04:00
Zhuoying Cai 1988a7f8ed pc-bios/s390-ccw: Add signature verification for secure IPL in audit mode
Enable secure IPL in audit mode, which performs signature verification,
but any error does not terminate the boot process. Only warnings will be
logged to the console instead.

Secure IPL in audit mode requires at least one certificate provided in
the key store along with necessary facilities (Secure IPL Facility,
Certificate Store Facility and secure IPL extension support).

Note: Secure IPL in audit mode is implemented for the SCSI scheme of
virtio-blk/virtio-scsi devices.

Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Eric Farman <farman@linux.ibm.com>
Reviewed-by: Jared Rossi <jrossi@linux.ibm.com>
Reviewed-by: Collin Walling <walling@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260730214624.2328883-24-zycai@linux.ibm.com
Signed-off-by: Eric Farman <farman@linux.ibm.com>
2026-08-26 06:52:20 -04:00
Zhuoying Cai a8fe09be7c pc-bios/s390-ccw: Introduce ZiplBootMode enum for IPL mode selection
Add ZiplBootMode enumeration to support multiple IPL boot configurations.
Boot modes differentiate between normal boot and secure IPL operations,
enabled based on boot certificates specified via the boot-certs option.

Normal Mode: IPL when no certificates are provided. No signature
verification is performed.

This prepares for future secure IPL modes requiring signature
verification.

Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Reviewed-by: Collin Walling <walling@linux.ibm.com>
Reviewed-by: Jared Rossi <jrossi@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260730214624.2328883-23-zycai@linux.ibm.com
Signed-off-by: Eric Farman <farman@linux.ibm.com>
2026-08-26 06:52:20 -04:00
Zhuoying Cai 21efab616e Add boot-certs to s390-ccw-virtio machine type option
Introduce a new `boot-certs` machine type option for the s390-ccw-virtio
machine. This allows users to specify one or more certificate file paths
or directories to be used during secure boot.

Each entry is specified using the syntax:
	boot-certs.<index>.path=/path/to/cert.pem

Multiple paths can be specify using array properties:
	boot-certs.0.path=/path/to/cert.pem,
	boot-certs.1.path=/path/to/cert-dir,
	boot-certs.2.path=/path/to/another-dir...

Signed-off-by: Zhuoying Cai <zycai@linux.ibm.com>
Acked-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Matthew Rosato <mjrosato@linux.ibm.com>
Link: https://lore.kernel.org/qemu-devel/20260730214624.2328883-2-zycai@linux.ibm.com
Signed-off-by: Eric Farman <farman@linux.ibm.com>
2026-08-26 06:52:20 -04:00
Tao Ding 8041d17308 tests/qtest: add test for K230 gsdma
This commit adds test cases for GSDMA.
Imitate the behavior of the driver, set LLT and sdma registers.
After the data transmission is completed, check the destination address data.

Update MAINTAINERS for this test.

Run this qtest:
    $ mkdir build && cd build && ../configure --target-list="riscv64-softmmu"
    $ QTEST_QEMU_BINARY=./qemu-system-riscv64   tests/qtest/k230-gsdma-test

Signed-off-by: Tao Ding <dingtao0430@163.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Reviewed-by: Junze Cao <caojunze424@gmail.com>
Message-ID: <20260808062227.66961-4-dingtao0430@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-08-24 11:12:52 +10:00
Tao Ding dde8fbba19 hw/riscv: k230: add gsdma in K230 board
This commit replaces the unimplemented part of GSDMA in K230. And connect the interrupt to plic.

Update K230.rst.

Signed-off-by: Tao Ding <dingtao0430@163.com>
Reviewed-by: Junze Cao <caojunze424@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20260808062227.66961-3-dingtao0430@163.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-08-24 11:10:49 +10:00
Yanfeng Liu 2a99140258 riscv/virt: Add optional UART1
This adds optional UART1 to RiscV virt board if required at
runtime to simplify multicore development.

Note that UART0 remains default serial_hd(0) and it is:

- the lowest address UART
- first serial in DTB
- behind /aliases/serial0 in DTB
- the /chosen/stdout-path in DTB

Note that UART1 is placed at different page from UART0 to
support page level isolation.

Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Message-ID: <tencent_4EEBFC805F3E59863BEDC38094EF5A109206@qq.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-08-24 11:06:23 +10:00
Junze Cao 4309ee8e91 hw/riscv: Connect K230 DDR controller and PHY models
Replace the unimplemented K230 DDR configuration region with the DDRC
model and map the PHY model at 0x9a000000.

Connect the controller to the PHY so DFI status reflects PHY training and
initialization state.

Suggested-by: Chao Liu <chao.liu@processmission.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Signed-off-by: Junze Cao <caojunze424@gmail.com>
Message-ID: <20260807-k230-ddr-v2-v2-2-c531308ae819@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2026-08-24 10:47:13 +10:00
Richard Henderson 42f8118926 Merge tag 'next-pull-request' of https://gitlab.com/peterx/qemu into staging
migration/mem pull for 11.2

v2: fixes macos build error

- Dongli's patch to add cpr-transfer support for HMP
- Fabiano's doc update for migration on security issues
- Gavin's fix for MMIO access support for memory APIs, reverting ram_device ops
- Sam's migration test build fix for !ASN1
- Peter's a few migration hardening fixes

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# gpg: Good signature from "Peter Xu <xzpeter@gmail.com>" [unknown]
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* tag 'next-pull-request' of https://gitlab.com/peterx/qemu:
  migration: Fix rare hang of migration_channel_read_peek()
  migration/ram: Check for RAMBlock size mismatch when parsing
  migration/multifd: Replace assert() with error_setg() in recv paths
  migration/multifd: Validate next_packet_size in zlib/zstd recv
  tests/qtest/migration: Only build tls_no_hostname test with TASN1
  system/memory: Make ram device region directly accessible
  system/memory: Use qemu_ram_move() for directly accessible regions
  system/memory: Use memmove() for directly accessible regions
  migration/cpr: Add HMP support for cpr-transfer
  docs: Add security considerations for migration

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2026-08-13 07:14:33 -07:00
Richard Henderson 8ae365bdc8 target/arm: Enable FEAT_SME_TMOP for -cpu max
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20260713230244.70174-11-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-08-12 11:20:34 +01:00
Fabiano Rosas 8b6405a493 docs: Add security considerations for migration
Add the security considerations that are unique to migration and that
do not already fall into one of the other categories. Some aspects are
better framed as security architecture considerations, so extend that
section to mention TLS and clarify that disk images and guest network
also need to be isolated from other processes, not just other guests.

Reviewed-by: Peter Xu <peterx@redhat.com>
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com>
Signed-off-by: Fabiano Rosas <farosas@suse.de>
Link: https://lore.kernel.org/r/20260721131457.3062767-1-farosas@suse.de
Signed-off-by: Peter Xu <peterx@redhat.com>
2026-08-11 15:34:38 -04:00
Bin Meng 24506d7709 docs/system/arm: Update Nuvoton OpenBMC image guidance
Describe the current OpenBMC target naming and release status for
Nuvoton machines. The latest 2.18.0 release no longer includes GSJ,
so point users at older 2.14.0 sources and explain how to find
Jenkins MTD artifacts.

Signed-off-by: Bin Meng <bin.meng@processmission.com>
Message-id: 20260627063208.33642-1-bin.meng@processmission.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-07-28 11:36:49 +01:00
Marc-André Lureau 521500bd80 docs/hyperv: fix misleading hv-crash shutdown description
The documentation stated that writing to HV_X64_MSR_CRASH_CTL
unconditionally causes the guest to shutdown. In reality, it triggers
qemu_system_guest_panicked() via KVM_SYSTEM_EVENT_CRASH and the
resulting action depends on the generic panic action policy
(-action panic=...), which defaults to shutdown.

Reviewed-by: Vitaly Kuznetsov <vkuznets@redhat.com>
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-ID: <20260701122135.3168729-1-marcandre.lureau@redhat.com>
2026-07-27 15:51:03 +04:00
Alex Bennée 7c99e7b302 docs/system: add FEAT_HAF
This is a subset of FEAT_HAFDBS which we have already implemented.

Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260708145841.3032079-9-alex.bennee@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2026-07-13 12:34:17 +01:00