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target/arm: Enable FEAT_IDTE3 for -cpu max

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Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20261010070952.323466-7-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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Richard Henderson authored and Peter Maydell committed 2026-10-15 17:38:38 +01:00
1 parent a99031fe7b
commit 44a4915203
2 files changed
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docs/system/arm/emulation.rst
+1
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@@ -105,6 +105,7 @@ the following architecture extensions:
- FEAT_HPMN0 (Setting of MDCR_EL2.HPMN to zero)
- FEAT_I8MM (AArch64 Int8 matrix multiplication instructions)
- FEAT_IDST (ID space trap handling)
- FEAT_IDTE3 (Trapping ID register accesses to EL3)
- FEAT_IESB (Implicit error synchronization event)
- FEAT_IVIPT (The IVIPT Extension)
- FEAT_JSCVT (JavaScript conversion instructions)
target/arm/tcg/cpu64.c
+4
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@@ -1461,6 +1461,10 @@ void aarch64_max_v9_tcg_initfn(Object *obj)
t = FIELD_DP64(t, ID_AA64PFR2, FPMR, 1); /* v9.2: FEAT_FPMR */
SET_IDREG(isar, ID_AA64PFR2, t);
t = GET_IDREG(isar, ID_AA64MMFR2);
t = FIELD_DP64(t, ID_AA64MMFR2, IDS, 2); /* v9.0: FEAT_IDTE3 */
SET_IDREG(isar, ID_AA64MMFR2, t);
t = GET_IDREG(isar, ID_AA64MMFR3);
t = FIELD_DP64(t, ID_AA64MMFR3, MEC, 1); /* v9.2: FEAT_MEC */
SET_IDREG(isar, ID_AA64MMFR3, t);