tcg: Generic expansion of tcg_gen_st_*

Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson committed 2026-10-24 17:14:50 +02:00
1 parent 3fd20a9abe
commit ef2cdac07e
3 files changed
+12 -30

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+1 -19
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@@ -142,7 +142,6 @@ void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in);
void tcg_gen_st8_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset);
void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset);
void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset);
/* 64 bit ops */
@@ -166,7 +165,6 @@ void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
void tcg_gen_ld32s_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
/* Size changing operations. */
@@ -352,24 +350,11 @@ void tcg_gen_stl_vec(TCGv_vec r, TCGv_ptr base, TCGArg offset, TCGType t);
/* Host pointer ops */
#if UINTPTR_MAX == UINT32_MAX
# define PTR i32
# define NAT TCGv_i32
#else
# define PTR i64
# define NAT TCGv_i64
#endif
TCGv_ptr tcg_constant_ptr_int(intptr_t x);
#define tcg_constant_ptr(X) tcg_constant_ptr_int((intptr_t)(X))
QEMU_ARG_NONNULL void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o);
static inline void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
{
glue(tcg_gen_st_, PTR)((NAT)r, a, o);
}
QEMU_ARG_NONNULL void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o);
QEMU_ARG_NONNULL void tcg_gen_discard_ptr(TCGv_ptr a);
QEMU_ARG_NONNULL void tcg_gen_add_ptr(TCGv_ptr r, TCGv_ptr a, TCGv_ptr b);
QEMU_ARG_NONNULL void tcg_gen_addi_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t b);
@@ -382,7 +367,4 @@ QEMU_ARG_NONNULL void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a);
QEMU_ARG_NONNULL void tcg_gen_extu_ptr_i64(TCGv_i64 r, TCGv_ptr a);
QEMU_ARG_NONNULL void tcg_gen_trunc_ptr_i32(TCGv_i32 r, TCGv_ptr a);
#undef PTR
#undef NAT
#endif /* TCG_TCG_OP_COMMON_H */
+1
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@@ -70,6 +70,7 @@ DEF3(shr, TCGV, TCGV, TCGV)
DEF3(shri, TCGV, TCGV, TINT)
DEF3(smax, TCGV, TCGV, TCGV)
DEF3(smin, TCGV, TCGV, TCGV)
DEF3(st, TCGV, TCGv_ptr, tcg_target_long)
DEF3(sub, TCGV, TCGV, TCGV)
DEF3(subi, TCGV, TCGV, TINT)
DEF6(sub2, TCGV, TCGV, TCGV, TCGV, TCGV, TCGV)
+10 -11
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@@ -1252,6 +1252,11 @@ void tcg_gen_smin(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2)
}
}
void tcg_gen_st(TCGType type, TCGTemp *val, TCGTemp *base, tcg_target_long ofs)
{
tcg_gen_op_tti(INDEX_op_st, type, val, base, ofs);
}
void tcg_gen_sub(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2)
{
tcg_gen_op_ttt(INDEX_op_sub, type, dst, src1, src2);
@@ -1413,12 +1418,6 @@ void tcg_gen_st16_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
tcg_gen_ldst_op_i32(INDEX_op_st16, arg1, arg2, offset);
}
void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset)
{
tcg_gen_ldst_op_i32(INDEX_op_st, arg1, arg2, offset);
}
/* 64-bit ops */
void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset)
@@ -1446,11 +1445,6 @@ void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
tcg_gen_ldst_op_i64(INDEX_op_st32, arg1, arg2, offset);
}
void tcg_gen_st_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset)
{
tcg_gen_ldst_op_i64(INDEX_op_st, arg1, arg2, offset);
}
void tcg_gen_ext32s_i64(TCGv_i64 ret, TCGv_i64 arg)
{
tcg_gen_sextract_i64(ret, arg, 0, 32);
@@ -1853,6 +1847,11 @@ void tcg_gen_ld_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
tcg_gen_ld(TCG_TYPE_PTR, tcgv_ptr_temp(r), tcgv_ptr_temp(a), o);
}
void tcg_gen_st_ptr(TCGv_ptr r, TCGv_ptr a, intptr_t o)
{
tcg_gen_st(TCG_TYPE_PTR, tcgv_ptr_temp(r), tcgv_ptr_temp(a), o);
}
void tcg_gen_trunc_i64_ptr(TCGv_ptr r, TCGv_i64 a)
{
tcg_gen_mov(TCG_TYPE_PTR, tcgv_ptr_temp(r), tcgv_i64_temp(a));