mirrors/qemu
0
0 Fork 0
mirror of https://gitlab.com/qemu-project/qemu.git synced 2026-10-28 14:04:39 +08:00
Code Activity

tcg: Generic expansion of tcg_gen_dup_*

Browse Source 
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson committed 2026-10-24 17:14:50 +02:00
1 parent b89a08121b
commit ca022e34bf
4 files changed
+17 -47
Download Patch File Download Diff File Expand all files Collapse all files

No files matched your search

include/tcg/tcg-op-common.h
-6
View File
@@ -137,9 +137,6 @@ void tcg_gen_bswap32_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_hswap_i32(TCGv_i32 ret, TCGv_i32 arg);
void tcg_gen_revbit32_i32(TCGv_i32 ret, TCGv_i32 arg);
/* Replicate a value of size @vece from @in to all the lanes in @out */
void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in);
/* 64 bit ops */
void tcg_gen_addN_i64(int n, TCGv_i64 *r, TCGv_i64 *a, TCGv_i64 *b);
@@ -153,9 +150,6 @@ void tcg_gen_wswap_i64(TCGv_i64 ret, TCGv_i64 arg);
void tcg_gen_revbit32_i64(TCGv_i64 ret, TCGv_i64 arg, unsigned flags);
void tcg_gen_revbit64_i64(TCGv_i64 ret, TCGv_i64 arg);
/* Replicate a value of size @vece from @in to all the lanes in @out */
void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in);
void tcg_gen_st32_i64(TCGv_i64 arg1, TCGv_ptr arg2, tcg_target_long offset);
void tcg_gen_ld32u_i64(TCGv_i64 ret, TCGv_ptr arg2, tcg_target_long offset);
include/tcg/tcg-op-def.h.inc
+1
View File
@@ -23,6 +23,7 @@ DEF4(deposit_z, TCGV, TCGV, unsigned, unsigned)
DEF1(discard, TCGV)
DEF3(div, TCGV, TCGV, TCGV)
DEF3(divu, TCGV, TCGV, TCGV)
DEF3(dup, unsigned, TCGV, TCGV)
DEF3(ext, TCGV, TCGV, MemOp)
DEF2(ext8s, TCGV, TCGV)
DEF2(ext8u, TCGV, TCGV)
tcg/tcg-op-gvec.c
-41
View File
@@ -434,47 +434,6 @@ uint64_t (dup_const)(unsigned vece, uint64_t c)
}
}
/* Duplicate IN into OUT as per VECE. */
void tcg_gen_dup_i32(unsigned vece, TCGv_i32 out, TCGv_i32 in)
{
switch (vece) {
case MO_8:
tcg_gen_ext8u_i32(out, in);
tcg_gen_muli_i32(out, out, 0x01010101);
break;
case MO_16:
tcg_gen_deposit_i32(out, in, in, 16, 16);
break;
case MO_32:
tcg_gen_mov_i32(out, in);
break;
default:
g_assert_not_reached();
}
}
void tcg_gen_dup_i64(unsigned vece, TCGv_i64 out, TCGv_i64 in)
{
switch (vece) {
case MO_8:
tcg_gen_ext8u_i64(out, in);
tcg_gen_muli_i64(out, out, 0x0101010101010101ull);
break;
case MO_16:
tcg_gen_ext16u_i64(out, in);
tcg_gen_muli_i64(out, out, 0x0001000100010001ull);
break;
case MO_32:
tcg_gen_deposit_i64(out, in, in, 32, 32);
break;
case MO_64:
tcg_gen_mov_i64(out, in);
break;
default:
g_assert_not_reached();
}
}
/* Select a supported vector type for implementing an operation on SIZE
* bytes. If OP is 0, assume that the real operation to be performed is
* required by all backends. Otherwise, make sure than OP can be performed
tcg/tcg-op.c
+16
View File
@@ -659,6 +659,22 @@ void tcg_gen_divu(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2)
}
}
void tcg_gen_dup(TCGType type, unsigned vece, TCGTemp *dst, TCGTemp *src)
{
unsigned t_width = tcg_type_bits(type);
unsigned e_width = memop_size(vece) * 8;
tcg_debug_assert(e_width <= t_width);
if (t_width == e_width) {
tcg_gen_mov(type, dst, src);
} else if (t_width == e_width * 2) {
tcg_gen_deposit(type, dst, src, src, e_width, e_width);
} else {
tcg_gen_extract(type, dst, src, 0, e_width);
tcg_gen_muli(type, dst, dst, dup_const(vece, 1));
}
}
void tcg_gen_eqv(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2)
{
if (tcg_op_supported(INDEX_op_eqv, type, 0)) {