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semihosting: remove common_* functions

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Now that both targets and semihosting implementation both use the
semihosting ops interface, we can remove all common_* functions.
This allows us to link together the three targets concerned: arm,
hexagon and riscv.

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/20261014210526.104215-12-pierrick.bouvier@oss.qualcomm.com
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
This commit is contained in:
Pierrick Bouvier committed 2026-10-15 19:30:24 +00:00
1 parent 3a076f7a70
commit c76758671f
4 files changed
-112
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include/semihosting/common-semi.h
-7
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@@ -53,12 +53,5 @@ typedef struct SemihostingCPUOps {
void common_semi_cb(CPUState *cs, uint64_t ret, int err);
void do_common_semihosting(CPUState *cs);
uint64_t common_semi_arg(CPUState *cs, int argno);
void common_semi_set_ret(CPUState *cs, uint64_t ret);
void common_semi_set_err(CPUState *cs, int err);
bool is_64bit_semihosting(CPUArchState *env);
bool common_semi_sys_exit_is_extended(CPUState *cs);
uint64_t common_semi_stack_bottom(CPUState *cs);
bool common_semi_has_synccache(CPUArchState *env);
#endif /* COMMON_SEMI_H */
target/arm/common-semi-target.c
-35
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@@ -71,38 +71,3 @@ const SemihostingCPUOps arm_semihosting_ops = {
.stack_bottom = arm_semi_stack_bottom,
.has_synccache = arm_semi_has_synccache,
};
uint64_t common_semi_arg(CPUState *cs, int argno)
{
return arm_semi_arg(cs, argno);
}
void common_semi_set_ret(CPUState *cs, uint64_t ret)
{
arm_semi_set_ret(cs, ret);
}
void common_semi_set_err(CPUState *cs, int err)
{
arm_semi_set_err(cs, err);
}
bool is_64bit_semihosting(CPUArchState *env)
{
return arm_semi_is_64bit(env_cpu(env));
}
bool common_semi_sys_exit_is_extended(CPUState *cs)
{
return arm_semi_sys_exit_is_extended(cs);
}
uint64_t common_semi_stack_bottom(CPUState *cs)
{
return arm_semi_stack_bottom(cs);
}
bool common_semi_has_synccache(CPUArchState *env)
{
return arm_semi_has_synccache(env_cpu(env));
}
target/hexagon/common-semi-target.c
-35
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@@ -59,38 +59,3 @@ const SemihostingCPUOps hexagon_semihosting_ops = {
.stack_bottom = hexagon_semi_stack_bottom,
.has_synccache = hexagon_semi_has_synccache,
};
uint64_t common_semi_arg(CPUState *cs, int argno)
{
return hexagon_semi_arg(cs, argno);
}
void common_semi_set_ret(CPUState *cs, uint64_t ret)
{
hexagon_semi_set_ret(cs, ret);
}
void common_semi_set_err(CPUState *cs, int err)
{
hexagon_semi_set_err(cs, err);
}
bool is_64bit_semihosting(CPUArchState *env)
{
return hexagon_semi_is_64bit(env_cpu(env));
}
bool common_semi_sys_exit_is_extended(CPUState *cs)
{
return hexagon_semi_sys_exit_is_extended(cs);
}
uint64_t common_semi_stack_bottom(CPUState *cs)
{
return hexagon_semi_stack_bottom(cs);
}
bool common_semi_has_synccache(CPUArchState *env)
{
return hexagon_semi_has_synccache(env_cpu(env));
}
target/riscv/common-semi-target.c
-35
View File
@@ -62,38 +62,3 @@ const SemihostingCPUOps riscv_semihosting_ops = {
.stack_bottom = riscv_semi_stack_bottom,
.has_synccache = riscv_semi_has_synccache,
};
uint64_t common_semi_arg(CPUState *cs, int argno)
{
return riscv_semi_arg(cs, argno);
}
void common_semi_set_ret(CPUState *cs, uint64_t ret)
{
riscv_semi_set_ret(cs, ret);
}
void common_semi_set_err(CPUState *cs, int err)
{
riscv_semi_set_err(cs, err);
}
bool is_64bit_semihosting(CPUArchState *env)
{
return riscv_semi_is_64bit(env_cpu(env));
}
bool common_semi_sys_exit_is_extended(CPUState *cs)
{
return riscv_semi_sys_exit_is_extended(cs);
}
uint64_t common_semi_stack_bottom(CPUState *cs)
{
return riscv_semi_stack_bottom(cs);
}
bool common_semi_has_synccache(CPUArchState *env)
{
return riscv_semi_has_synccache(env_cpu(env));
}