docs/system/or1k: Rename from openrisc

Also rename docs/system/target-or1k.rst from target-openrisc.rst,
and update all toctree entries to match.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Stafford Horne <shorne@gmail.com>
Message-ID: <20260205030244.266447-6-richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

MAINTAINERS

@@ -302,7 +302,7 @@ F: tests/tcg/mips/
 OpenRISC TCG CPUs
 M: Stafford Horne <shorne@gmail.com>
 S: Odd Fixes
-F: docs/system/openrisc/cpu-features.rst
+F: docs/system/or1k/cpu-features.rst
 F: target/or1k/
 F: hw/or1k/
 F: include/hw/or1k/
@@ -1493,7 +1493,7 @@ OpenRISC Machines
 or1k-sim
 M: Jia Liu <proljc@gmail.com>
 S: Maintained
-F: docs/system/openrisc/or1k-sim.rst
+F: docs/system/or1k/or1k-sim.rst
 F: hw/intc/ompic.c
 F: hw/or1k/openrisc_sim.c
 F: tests/functional/or1k/test_sim.py

docs/system/target-or1k.rst

@@ -55,17 +55,17 @@ Board-specific documentation
 .. toctree::
    :maxdepth: 1
 
-   openrisc/or1k-sim
-   openrisc/virt
+   or1k/or1k-sim
+   or1k/virt
 
 Emulated CPU architecture support
 =================================
 
 .. toctree::
-   openrisc/emulation
+   or1k/emulation
 
 OpenRISC CPU features
 =====================
 
 .. toctree::
-   openrisc/cpu-features
+   or1k/cpu-features

docs/system/targets.rst

@@ -21,8 +21,8 @@ Contents:
    target-loongarch
    target-m68k
    target-mips
+   target-or1k
    target-ppc
-   target-openrisc
    target-riscv
    target-rx
    target-s390x