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Merge tag 'pbouvier/pr/multi_target-20261024' of https://gitlab.com/p-b-o/qemu into staging

Browse Source 
Changes:
- [PATCH v2 00/11] multi-target: prefix helpers with target prefix (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>)
  Link: https://lore.kernel.org/qemu-devel/20261024163249.77855-1-pierrick.bouvier@oss.qualcomm.com
- [PATCH v3 0/9] multi-target: add riscv64-softmmu (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>)
  Link: https://lore.kernel.org/qemu-devel/20261024061616.27381-1-pierrick.bouvier@oss.qualcomm.com

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# gpg: Signature made Sat 24 Oct 2026 12:36:42 PM CDT
# gpg:                using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
# gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 37C1 5694 D8BA 9764 B197  3FDB B444 37D1 9C28 62DF

* tag 'pbouvier/pr/multi_target-20261024' of https://gitlab.com/p-b-o/qemu:
  meson.build: list all remaining softmmu targets as comments
  meson.build: add riscv64-softmmu to multi-target
  target/riscv/kvm: restrict kvm-accel-riscv-cpu to riscv targets
  target/riscv/tcg: restrict tcg-accel-riscv-cpu to riscv targets
  target/riscv: rename virt_acpi_setup to riscv_virt_acpi_setup
  hw/riscv/virt: restrict scope of virt_is_acpi_enabled to this file
  test/unit/multi-target: check QOM types can be initialized with any target
  hw/riscv/virt: make machine available for riscv targets only
  target-info: add target_base_riscv
  target/tricore: remove explicit target specific prefix
  target/rx: remove explicit target specific prefix
  target/or1k: remove explicit target specific prefix
  target/microblaze: remove explicit target specific prefix
  target/hppa: remove explicit target specific prefix
  target/hexagon: remove explicit target specific prefix
  target/alpha: remove explicit target specific prefix
  tcg: prefix helpers with target base architecture
  target/sparc: define crypto helpers using HELPER macro
  tcg: introduce HELPER_INFO macro
  target/rx: define and call helpers using HELPER macro

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson committed 2026-10-27 06:08:01 -05:00
2 parents d731492832 59f954f827
commit 2c0584588c
39 files changed
+250 -170
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hw/riscv/virt-acpi-build.c
+1 -1
View File
@@ -1021,7 +1021,7 @@ static const VMStateDescription vmstate_virt_acpi_build = {
},
};
void virt_acpi_setup(RISCVVirtState *s)
void riscv_virt_acpi_setup(RISCVVirtState *s)
{
AcpiBuildTables tables;
AcpiBuildState *build_state;
hw/riscv/virt.c
+8 -6
View File
@@ -22,6 +22,7 @@
#include "qemu/units.h"
#include "qemu/error-report.h"
#include "qemu/guest-random.h"
#include "qemu/target-info.h"
#include "qapi/error.h"
#include "hw/core/boards.h"
#include "hw/core/loader.h"
@@ -71,6 +72,11 @@ static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type)
return riscv_is_kvm_aia_aplic_imsic(msimode);
}
static bool virt_is_acpi_enabled(RISCVVirtState *s)
{
return s->acpi != ON_OFF_AUTO_OFF;
}
static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type)
{
bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC;
@@ -706,7 +712,7 @@ static void virt_machine_done(Notifier *notifier, void *data)
virt_build_smbios(s);
if (virt_is_acpi_enabled(s)) {
virt_acpi_setup(s);
riscv_virt_acpi_setup(s);
}
}
@@ -1066,11 +1072,6 @@ static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name,
visit_type_OnOffAuto(v, name, &s->iommu_sys, errp);
}
bool virt_is_acpi_enabled(RISCVVirtState *s)
{
return s->acpi != ON_OFF_AUTO_OFF;
}
static void virt_get_acpi(Object *obj, Visitor *v, const char *name,
void *opaque, Error **errp)
{
@@ -1203,6 +1204,7 @@ static const TypeInfo virt_machine_typeinfo = {
.instance_init = virt_machine_instance_init,
.instance_finalize = virt_machine_instance_finalize,
.instance_size = sizeof(RISCVVirtState),
.is_available = target_base_riscv,
.interfaces = (const InterfaceInfo[]) {
{ TYPE_HOTPLUG_HANDLER },
{ }
include/exec/helper-gen-common.h
+7
View File
@@ -7,8 +7,15 @@
#ifndef HELPER_GEN_COMMON_H
#define HELPER_GEN_COMMON_H
#include "exec/helper-head.h.inc"
/* Common helpers are built once, without a target prefix. */
#pragma push_macro("HELPER_PREFIX")
#undef HELPER_PREFIX
#define HELPER_PREFIX
#define HELPER_H "accel/tcg/tcg-runtime.h"
#include "exec/helper-gen.h.inc"
#undef HELPER_H
#pragma pop_macro("HELPER_PREFIX")
#endif /* HELPER_GEN_COMMON_H */
include/exec/helper-gen.h.inc
+24 -24
View File
@@ -11,88 +11,88 @@
#include "exec/helper-head.h.inc"
#define DEF_HELPER_FLAGS_0(name, flags, ret) \
extern TCGHelperInfo glue(helper_info_, name); \
extern TCGHelperInfo HELPER_INFO(name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl0(ret)) \
{ \
tcg_gen_call0(glue(helper_info_,name).func, \
&glue(helper_info_,name), dh_retvar(ret)); \
tcg_gen_call0(HELPER_INFO(name).func, \
&HELPER_INFO(name), dh_retvar(ret)); \
}
#define DEF_HELPER_FLAGS_1(name, flags, ret, t1) \
extern TCGHelperInfo glue(helper_info_, name); \
extern TCGHelperInfo HELPER_INFO(name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1)) \
{ \
tcg_gen_call1(glue(helper_info_,name).func, \
&glue(helper_info_,name), dh_retvar(ret), \
tcg_gen_call1(HELPER_INFO(name).func, \
&HELPER_INFO(name), dh_retvar(ret), \
dh_arg(t1, 1)); \
}
#define DEF_HELPER_FLAGS_2(name, flags, ret, t1, t2) \
extern TCGHelperInfo glue(helper_info_, name); \
extern TCGHelperInfo HELPER_INFO(name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2)) \
{ \
tcg_gen_call2(glue(helper_info_,name).func, \
&glue(helper_info_,name), dh_retvar(ret), \
tcg_gen_call2(HELPER_INFO(name).func, \
&HELPER_INFO(name), dh_retvar(ret), \
dh_arg(t1, 1), dh_arg(t2, 2)); \
}
#define DEF_HELPER_FLAGS_3(name, flags, ret, t1, t2, t3) \
extern TCGHelperInfo glue(helper_info_, name); \
extern TCGHelperInfo HELPER_INFO(name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3)) \
{ \
tcg_gen_call3(glue(helper_info_,name).func, \
&glue(helper_info_,name), dh_retvar(ret), \
tcg_gen_call3(HELPER_INFO(name).func, \
&HELPER_INFO(name), dh_retvar(ret), \
dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3)); \
}
#define DEF_HELPER_FLAGS_4(name, flags, ret, t1, t2, t3, t4) \
extern TCGHelperInfo glue(helper_info_, name); \
extern TCGHelperInfo HELPER_INFO(name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), \
dh_arg_decl(t3, 3), dh_arg_decl(t4, 4)) \
{ \
tcg_gen_call4(glue(helper_info_,name).func, \
&glue(helper_info_,name), dh_retvar(ret), \
tcg_gen_call4(HELPER_INFO(name).func, \
&HELPER_INFO(name), dh_retvar(ret), \
dh_arg(t1, 1), dh_arg(t2, 2), \
dh_arg(t3, 3), dh_arg(t4, 4)); \
}
#define DEF_HELPER_FLAGS_5(name, flags, ret, t1, t2, t3, t4, t5) \
extern TCGHelperInfo glue(helper_info_, name); \
extern TCGHelperInfo HELPER_INFO(name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
dh_arg_decl(t4, 4), dh_arg_decl(t5, 5)) \
{ \
tcg_gen_call5(glue(helper_info_,name).func, \
&glue(helper_info_,name), dh_retvar(ret), \
tcg_gen_call5(HELPER_INFO(name).func, \
&HELPER_INFO(name), dh_retvar(ret), \
dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
dh_arg(t4, 4), dh_arg(t5, 5)); \
}
#define DEF_HELPER_FLAGS_6(name, flags, ret, t1, t2, t3, t4, t5, t6) \
extern TCGHelperInfo glue(helper_info_, name); \
extern TCGHelperInfo HELPER_INFO(name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6)) \
{ \
tcg_gen_call6(glue(helper_info_,name).func, \
&glue(helper_info_,name), dh_retvar(ret), \
tcg_gen_call6(HELPER_INFO(name).func, \
&HELPER_INFO(name), dh_retvar(ret), \
dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6)); \
}
#define DEF_HELPER_FLAGS_7(name, flags, ret, t1, t2, t3, t4, t5, t6, t7)\
extern TCGHelperInfo glue(helper_info_, name); \
extern TCGHelperInfo HELPER_INFO(name); \
static inline void glue(gen_helper_, name)(dh_retvar_decl(ret) \
dh_arg_decl(t1, 1), dh_arg_decl(t2, 2), dh_arg_decl(t3, 3), \
dh_arg_decl(t4, 4), dh_arg_decl(t5, 5), dh_arg_decl(t6, 6), \
dh_arg_decl(t7, 7)) \
{ \
tcg_gen_call7(glue(helper_info_,name).func, \
&glue(helper_info_,name), dh_retvar(ret), \
tcg_gen_call7(HELPER_INFO(name).func, \
&HELPER_INFO(name), dh_retvar(ret), \
dh_arg(t1, 1), dh_arg(t2, 2), dh_arg(t3, 3), \
dh_arg(t4, 4), dh_arg(t5, 5), dh_arg(t6, 6), \
dh_arg(t7, 7)); \
include/exec/helper-head.h.inc
+7 -1
View File
@@ -8,7 +8,13 @@
#include "fpu/softfloat-types.h"
#define HELPER(name) glue(helper_, name)
#ifdef TARGET_ARCH_PREFIX
#define HELPER_PREFIX glue(TARGET_ARCH_PREFIX, _)
#else
#define HELPER_PREFIX
#endif
#define HELPER(name) glue(HELPER_PREFIX, glue(helper_, name))
#define HELPER_INFO(name) glue(HELPER_PREFIX, glue(helper_info_, name))
/* Some types that make sense in C, but not for TCG. */
#define dh_alias_i32 i32
include/exec/helper-info.c.inc
+8 -8
View File
@@ -16,21 +16,21 @@
#define str(s) #s
#define DEF_HELPER_FLAGS_0(NAME, FLAGS, RET) \
TCGHelperInfo glue(helper_info_, NAME) = { \
TCGHelperInfo HELPER_INFO(NAME) = { \
.func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(RET), \
.typemask = dh_typemask(RET, 0) \
};
#define DEF_HELPER_FLAGS_1(NAME, FLAGS, RET, T1) \
TCGHelperInfo glue(helper_info_, NAME) = { \
TCGHelperInfo HELPER_INFO(NAME) = { \
.func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(RET), \
.typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
};
#define DEF_HELPER_FLAGS_2(NAME, FLAGS, RET, T1, T2) \
TCGHelperInfo glue(helper_info_, NAME) = { \
TCGHelperInfo HELPER_INFO(NAME) = { \
.func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(RET), \
.typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
@@ -38,7 +38,7 @@
};
#define DEF_HELPER_FLAGS_3(NAME, FLAGS, RET, T1, T2, T3) \
TCGHelperInfo glue(helper_info_, NAME) = { \
TCGHelperInfo HELPER_INFO(NAME) = { \
.func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(RET), \
.typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
@@ -46,7 +46,7 @@
};
#define DEF_HELPER_FLAGS_4(NAME, FLAGS, RET, T1, T2, T3, T4) \
TCGHelperInfo glue(helper_info_, NAME) = { \
TCGHelperInfo HELPER_INFO(NAME) = { \
.func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(RET), \
.typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
@@ -55,7 +55,7 @@
};
#define DEF_HELPER_FLAGS_5(NAME, FLAGS, RET, T1, T2, T3, T4, T5) \
TCGHelperInfo glue(helper_info_, NAME) = { \
TCGHelperInfo HELPER_INFO(NAME) = { \
.func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(RET), \
.typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
@@ -64,7 +64,7 @@
};
#define DEF_HELPER_FLAGS_6(NAME, FLAGS, RET, T1, T2, T3, T4, T5, T6) \
TCGHelperInfo glue(helper_info_, NAME) = { \
TCGHelperInfo HELPER_INFO(NAME) = { \
.func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(RET), \
.typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
@@ -74,7 +74,7 @@
};
#define DEF_HELPER_FLAGS_7(NAME, FLAGS, RET, T1, T2, T3, T4, T5, T6, T7) \
TCGHelperInfo glue(helper_info_, NAME) = { \
TCGHelperInfo HELPER_INFO(NAME) = { \
.func = HELPER(NAME), .name = str(NAME), \
.flags = FLAGS | dh_callflag(RET), \
.typemask = dh_typemask(RET, 0) | dh_typemask(T1, 1) \
include/exec/helper-proto-common.h
+7
View File
@@ -9,9 +9,16 @@
#include "qemu/atomic128.h" /* for HAVE_CMPXCHG128 */
#include "exec/helper-head.h.inc"
/* Common helpers are built once, without a target prefix. */
#pragma push_macro("HELPER_PREFIX")
#undef HELPER_PREFIX
#define HELPER_PREFIX
#define HELPER_H "accel/tcg/tcg-runtime.h"
#include "exec/helper-proto.h.inc"
#undef HELPER_H
#pragma pop_macro("HELPER_PREFIX")
#include "accel/tcg/getpc.h"
include/hw/riscv/virt.h
+1 -2
View File
@@ -121,9 +121,8 @@ enum {
#define VIRT_PLIC_SIZE(__num_context) \
(VIRT_PLIC_CONTEXT_BASE + (__num_context) * VIRT_PLIC_CONTEXT_STRIDE)
bool virt_is_acpi_enabled(RISCVVirtState *s);
bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
void virt_acpi_setup(RISCVVirtState *vms);
void riscv_virt_acpi_setup(RISCVVirtState *vms);
/*
* The virt machine physical address space used by some of the devices
include/qemu/target-info.h
+7
View File
@@ -120,6 +120,13 @@ bool target_ppc64(void);
*/
bool target_s390x(void);
/**
* target_base_riscv:
*
* Returns whether the target architecture is RISC-V 32-bit or 64-bit.
*/
bool target_base_riscv(void);
/**
* target_riscv64:
*
meson.build
+20
View File
@@ -4167,6 +4167,7 @@ foreach target_base_arch, config_base_arch : config_base_arch_mak
# prevent common code to access cpu compile time definition,
# but still allow access to cpu.h
target_c_args = ['-DCPU_DEFS_H']
target_c_args += ['-DTARGET_ARCH_PREFIX=target_' + target_base_arch.to_lower()]
target_system_c_args = target_c_args + ['-DCOMPILING_SYSTEM_VS_USER', '-DCONFIG_SOFTMMU']
if target_base_arch in target_common_arch
@@ -4274,11 +4275,29 @@ multi_target_supported_targets = [
'avr-softmmu',
'hexagon-softmmu',
'hppa-softmmu',
# 'i386-softmmu',
# 'loongarch64-softmmu',
'm68k-softmmu',
'microblaze-softmmu',
# 'mips-softmmu',
# 'mips64-softmmu',
# 'mips64el-softmmu',
# 'mipsel-softmmu',
'or1k-softmmu',
# 'ppc-softmmu',
# 'ppc64-softmmu',
# 'riscv32-softmmu',
'riscv64-softmmu',
'rx-softmmu',
# 's390x-softmmu',
# 'sh4-softmmu',
# 'sh4eb-softmmu',
# 'sparc-softmmu',
# 'sparc64-softmmu',
'tricore-softmmu',
# 'x86_64-softmmu',
# 'xtensa-softmmu',
# 'xtensaeb-softmmu',
]
emulators = {}
@@ -4290,6 +4309,7 @@ foreach target : target_dirs
arch_deps = []
c_args = ['-DCOMPILING_PER_TARGET',
'-DCONFIG_TARGET="@0@-config-target.h"'.format(target),
'-DTARGET_ARCH_PREFIX=target_' + target_base_arch.to_lower(),
]
link_args = emulator_link_args
target-info.c
+11
View File
@@ -110,6 +110,17 @@ bool target_s390x(void)
return target_arch() == SYS_EMU_TARGET_S390X;
}
bool target_base_riscv(void)
{
switch (target_arch()) {
case SYS_EMU_TARGET_RISCV32:
case SYS_EMU_TARGET_RISCV64:
return true;
default:
return false;
}
}
bool target_riscv64(void)
{
return target_arch() == SYS_EMU_TARGET_RISCV64;
target/alpha/fpu_helper.c
+1 -1
View File
@@ -248,7 +248,7 @@ uint64_t HELPER(muls)(CPUAlphaState *env, uint64_t a, uint64_t b)
return float32_to_s(fr);
}
uint64_t HELPER(alpha_divs)(CPUAlphaState *env, uint64_t a, uint64_t b)
uint64_t HELPER(divs)(CPUAlphaState *env, uint64_t a, uint64_t b)
{
float32 fa, fb, fr;
target/alpha/helper.h
+1 -1
View File
@@ -47,7 +47,7 @@ DEF_HELPER_FLAGS_1(memory_to_s, TCG_CALL_NO_RWG_SE, i64, i32)
DEF_HELPER_FLAGS_3(adds, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(subs, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(muls, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(alpha_divs, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_RWG, i64, env, i64, i64)
DEF_HELPER_FLAGS_2(sqrts, TCG_CALL_NO_RWG, i64, env, i64)
DEF_HELPER_FLAGS_3(addt, TCG_CALL_NO_RWG, i64, env, i64, i64)
target/alpha/translate.c
+2 -2
View File
@@ -790,7 +790,7 @@ static inline void glue(gen_, name)(DisasContext *ctx, \
IEEE_ARITH3(adds)
IEEE_ARITH3(subs)
IEEE_ARITH3(muls)
IEEE_ARITH3(alpha_divs)
IEEE_ARITH3(divs)
IEEE_ARITH3(addt)
IEEE_ARITH3(subt)
IEEE_ARITH3(mult)
@@ -2086,7 +2086,7 @@ static DisasJumpType translate_one(DisasContext *ctx, uint32_t insn)
case 0x03:
/* DIVS */
REQUIRE_FEN;
gen_alpha_divs(ctx, ra, rb, rc, fn11);
gen_divs(ctx, ra, rb, rc, fn11);
break;
case 0x20:
/* ADDT */
target/hexagon/gen_tcg.h
+1 -1
View File
@@ -1135,7 +1135,7 @@
#define fGEN_TCG_J2_pause(SHORTCODE) \
do { \
uiV = uiV; \
gen_helper_hexagon_raise_exception(tcg_env, \
gen_helper_raise_exception(tcg_env, \
tcg_constant_i32(EXCP_YIELD), \
tcg_constant_i32(ctx->next_PC)); \
} while (0)
target/hexagon/gen_tcg_sys.h
+1 -1
View File
@@ -80,7 +80,7 @@
#define fGEN_TCG_Y2_wait(SHORTCODE) \
do { \
RsV = RsV; \
gen_helper_hexagon_wait(tcg_env); \
gen_helper_wait(tcg_env); \
} while (0)
#define fGEN_TCG_Y2_resume(SHORTCODE) \
target/hexagon/helper.h
+2 -2
View File
@@ -18,7 +18,7 @@
#include "internal.h"
#include "helper_protos_generated.h.inc"
DEF_HELPER_FLAGS_3(hexagon_raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32, i32)
DEF_HELPER_FLAGS_3(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32, i32)
DEF_HELPER_2(commit_store, void, env, int)
DEF_HELPER_3(gather_store, void, env, i32, int)
DEF_HELPER_1(commit_hvx_stores, void, env)
@@ -138,7 +138,7 @@ DEF_HELPER_3(sreg_write_masked, void, env, i32, i32)
DEF_HELPER_3(setprio, void, env, i32, i32)
DEF_HELPER_2(start, void, env, i32)
DEF_HELPER_1(stop, void, env)
DEF_HELPER_1(hexagon_wait, void, env)
DEF_HELPER_1(wait, void, env)
DEF_HELPER_2(resume, void, env, i32)
DEF_HELPER_1(resched, void, env)
DEF_HELPER_3(modify_ssr, void, env, i32, i32)
target/hexagon/op_helper.c
+2 -2
View File
@@ -93,7 +93,7 @@ G_NORETURN void hexagon_raise_exception_err(CPUHexagonState *env,
do_raise_exception(env, exception, pc, 0);
}
G_NORETURN void HELPER(hexagon_raise_exception)(CPUHexagonState *env, uint32_t excp,
G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp,
uint32_t PC)
{
hexagon_raise_exception_err(env, excp, PC);
@@ -1839,7 +1839,7 @@ void HELPER(resched)(CPUHexagonState *env)
resched(env);
}
void HELPER(hexagon_wait)(CPUHexagonState *env)
void HELPER(wait)(CPUHexagonState *env)
{
BQL_LOCK_GUARD();
target/hexagon/translate.c
+2 -2
View File
@@ -139,7 +139,7 @@ intptr_t ctx_tmp_vreg_off(DisasContext *ctx, int regnum,
static void gen_precise_exception(int cause, uint32_t PC)
{
tcg_gen_movi_i32(hex_cause_code, cause);
gen_helper_hexagon_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT_PRECISE),
gen_helper_raise_exception(tcg_env, tcg_constant_i32(HEX_EVENT_PRECISE),
tcg_constant_i32(PC));
}
@@ -1146,7 +1146,7 @@ static void check_imprecise_exception(DisasContext *ctx)
TCGLabel *label = gen_new_label();
tcg_gen_brcondi_tl(TCG_COND_EQ, hex_imprecise_exception, 0, label);
gen_helper_hexagon_raise_exception(tcg_env, hex_imprecise_exception, PC);
gen_helper_raise_exception(tcg_env, hex_imprecise_exception, PC);
gen_set_label(label);
}
#endif
target/hppa/helper.h
+3 -3
View File
@@ -1,4 +1,4 @@
DEF_HELPER_2(hppa_excp, noreturn, env, int)
DEF_HELPER_2(excp, noreturn, env, int)
DEF_HELPER_FLAGS_3(stby_b, TCG_CALL_NO_WG, void, env, tl, tl)
DEF_HELPER_FLAGS_3(stby_b_parallel, TCG_CALL_NO_WG, void, env, tl, tl)
@@ -82,8 +82,8 @@ DEF_HELPER_FLAGS_4(fmpynfadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64)
DEF_HELPER_FLAGS_0(read_interval_timer, TCG_CALL_NO_RWG, tl)
#ifndef CONFIG_USER_ONLY
DEF_HELPER_1(hppa_halt, noreturn, env)
DEF_HELPER_1(hppa_reset, noreturn, env)
DEF_HELPER_1(halt, noreturn, env)
DEF_HELPER_1(reset, noreturn, env)
DEF_HELPER_1(rfi, void, env)
DEF_HELPER_1(rfi_r, void, env)
DEF_HELPER_FLAGS_2(b_gate_priv, TCG_CALL_NO_WG, i64, env, i64)
target/hppa/op_helper.c
+2 -2
View File
@@ -30,7 +30,7 @@
#include "user/page-protection.h"
#endif
G_NORETURN void HELPER(hppa_excp)(CPUHPPAState *env, int excp)
G_NORETURN void HELPER(excp)(CPUHPPAState *env, int excp)
{
CPUState *cs = env_cpu(env);
@@ -341,7 +341,7 @@ target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr,
if (excp == EXCP_DTLB_MISS) {
excp = EXCP_NA_DTLB_MISS;
}
HELPER(hppa_excp)(env, excp);
HELPER(excp)(env, excp);
}
return (want & prot) != 0;
#endif
target/hppa/sys_helper.c
+4 -4
View File
@@ -48,16 +48,16 @@ void HELPER(write_interval_timer)(CPUHPPAState *env, target_ulong val)
timer_mod(cpu->alarm_timer, timeout);
}
void HELPER(hppa_halt)(CPUHPPAState *env)
void HELPER(halt)(CPUHPPAState *env)
{
qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN);
HELPER(hppa_excp)(env, EXCP_HLT);
HELPER(excp)(env, EXCP_HLT);
}
void HELPER(hppa_reset)(CPUHPPAState *env)
void HELPER(reset)(CPUHPPAState *env)
{
qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
HELPER(hppa_excp)(env, EXCP_HLT);
HELPER(excp)(env, EXCP_HLT);
}
target_ulong HELPER(swap_system_mask)(CPUHPPAState *env, target_ulong nsm)
target/hppa/translate.c
+3 -3
View File
@@ -726,7 +726,7 @@ static void install_link(DisasContext *ctx, unsigned link, bool with_sr0)
static void gen_excp_1(int exception)
{
gen_helper_hppa_excp(tcg_env, tcg_constant_i32(exception));
gen_helper_excp(tcg_env, tcg_constant_i32(exception));
}
static void gen_excp(DisasContext *ctx, int exception)
@@ -2450,7 +2450,7 @@ static bool trans_halt(DisasContext *ctx, arg_halt *a)
#ifndef CONFIG_USER_ONLY
set_psw_xb(ctx, 0);
nullify_over(ctx);
gen_helper_hppa_halt(tcg_env);
gen_helper_halt(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
@@ -2462,7 +2462,7 @@ static bool trans_reset(DisasContext *ctx, arg_reset *a)
#ifndef CONFIG_USER_ONLY
set_psw_xb(ctx, 0);
nullify_over(ctx);
gen_helper_hppa_reset(tcg_env);
gen_helper_reset(tcg_env);
ctx->base.is_jmp = DISAS_NORETURN;
return nullify_end(ctx);
#endif
target/microblaze/helper.h
+5 -5
View File
@@ -1,15 +1,15 @@
DEF_HELPER_FLAGS_2(microblaze_raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32)
DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(microblaze_fadd, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(frsub, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(microblaze_fmul, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(microblaze_fdiv, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_2(flt, TCG_CALL_NO_WG, i32, env, i32)
DEF_HELPER_FLAGS_2(fint, TCG_CALL_NO_WG, i32, env, i32)
DEF_HELPER_FLAGS_2(microblaze_fsqrt, TCG_CALL_NO_WG, i32, env, i32)
DEF_HELPER_FLAGS_2(fsqrt, TCG_CALL_NO_WG, i32, env, i32)
DEF_HELPER_FLAGS_3(fcmp_un, TCG_CALL_NO_WG, i32, env, i32, i32)
DEF_HELPER_FLAGS_3(fcmp_lt, TCG_CALL_NO_WG, i32, env, i32, i32)
target/microblaze/op_helper.c
+5 -5
View File
@@ -62,7 +62,7 @@ uint32_t HELPER(get)(uint32_t id, uint32_t ctrl)
return 0xdead0000 | id;
}
void HELPER(microblaze_raise_exception)(CPUMBState *env, uint32_t index)
void HELPER(raise_exception)(CPUMBState *env, uint32_t index)
{
CPUState *cs = env_cpu(env);
@@ -154,7 +154,7 @@ static void update_fpu_flags(CPUMBState *env, int flags, uintptr_t ra)
}
}
uint32_t HELPER(microblaze_fadd)(CPUMBState *env, uint32_t a, uint32_t b)
uint32_t HELPER(fadd)(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
@@ -183,7 +183,7 @@ uint32_t HELPER(frsub)(CPUMBState *env, uint32_t a, uint32_t b)
return fd.l;
}
uint32_t HELPER(microblaze_fmul)(CPUMBState *env, uint32_t a, uint32_t b)
uint32_t HELPER(fmul)(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
@@ -198,7 +198,7 @@ uint32_t HELPER(microblaze_fmul)(CPUMBState *env, uint32_t a, uint32_t b)
return fd.l;
}
uint32_t HELPER(microblaze_fdiv)(CPUMBState *env, uint32_t a, uint32_t b)
uint32_t HELPER(fdiv)(CPUMBState *env, uint32_t a, uint32_t b)
{
CPU_FloatU fd, fa, fb;
int flags;
@@ -352,7 +352,7 @@ uint32_t HELPER(fint)(CPUMBState *env, uint32_t a)
return r;
}
uint32_t HELPER(microblaze_fsqrt)(CPUMBState *env, uint32_t a)
uint32_t HELPER(fsqrt)(CPUMBState *env, uint32_t a)
{
CPU_FloatU fd, fa;
int flags;
target/microblaze/translate.c
+5 -5
View File
@@ -100,7 +100,7 @@ static void t_sync_flags(DisasContext *dc)
static void gen_raise_exception(DisasContext *dc, uint32_t index)
{
gen_helper_microblaze_raise_exception(tcg_env, tcg_constant_i32(index));
gen_helper_raise_exception(tcg_env, tcg_constant_i32(index));
dc->base.is_jmp = DISAS_NORETURN;
}
@@ -421,10 +421,10 @@ static void gen_cmpu(TCGv_i32 out, TCGv_i32 ina, TCGv_i32 inb)
DO_TYPEA(cmp, false, gen_cmp)
DO_TYPEA(cmpu, false, gen_cmpu)
ENV_WRAPPER3(gen_fadd, gen_helper_microblaze_fadd)
ENV_WRAPPER3(gen_fadd, gen_helper_fadd)
ENV_WRAPPER3(gen_frsub, gen_helper_frsub)
ENV_WRAPPER3(gen_fmul, gen_helper_microblaze_fmul)
ENV_WRAPPER3(gen_fdiv, gen_helper_microblaze_fdiv)
ENV_WRAPPER3(gen_fmul, gen_helper_fmul)
ENV_WRAPPER3(gen_fdiv, gen_helper_fdiv)
ENV_WRAPPER3(gen_fcmp_un, gen_helper_fcmp_un)
ENV_WRAPPER3(gen_fcmp_lt, gen_helper_fcmp_lt)
ENV_WRAPPER3(gen_fcmp_eq, gen_helper_fcmp_eq)
@@ -447,7 +447,7 @@ DO_TYPEA_CFG(fcmp_ge, use_fpu, true, gen_fcmp_ge)
ENV_WRAPPER2(gen_flt, gen_helper_flt)
ENV_WRAPPER2(gen_fint, gen_helper_fint)
ENV_WRAPPER2(gen_fsqrt, gen_helper_microblaze_fsqrt)
ENV_WRAPPER2(gen_fsqrt, gen_helper_fsqrt)
DO_TYPEA0_CFG(flt, use_fpu >= 2, true, gen_flt)
DO_TYPEA0_CFG(fint, use_fpu >= 2, true, gen_fint)
target/or1k/helper.h
+1 -1
View File
@@ -59,7 +59,7 @@ FOP_CMP(ult)
#undef FOP_CMP
/* interrupt */
DEF_HELPER_FLAGS_1(or1k_rfe, 0, void, env)
DEF_HELPER_FLAGS_1(rfe, 0, void, env)
/* sys */
DEF_HELPER_FLAGS_3(mtspr, 0, void, env, i32, i32)
target/or1k/interrupt_helper.c
+1 -1
View File
@@ -22,7 +22,7 @@
#include "cpu.h"
#include "exec/helper-proto.h"
void HELPER(or1k_rfe)(CPUOpenRISCState *env)
void HELPER(rfe)(CPUOpenRISCState *env)
{
env->pc = env->epcr;
env->lock_addr = -1;
target/or1k/translate.c
+1 -1
View File
@@ -1110,7 +1110,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a)
if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
gen_helper_or1k_rfe(tcg_env);
gen_helper_rfe(tcg_env);
dc->base.is_jmp = DISAS_EXIT;
}
return true;
target/riscv/kvm/kvm-cpu.c
+2
View File
@@ -26,6 +26,7 @@
#include "qapi/error.h"
#include "qemu/error-report.h"
#include "qemu/main-loop.h"
#include "qemu/target-info.h"
#include "qapi/visitor.h"
#include "system/system.h"
#include "system/kvm.h"
@@ -2208,6 +2209,7 @@ static const TypeInfo kvm_cpu_accel_type_info = {
.parent = TYPE_ACCEL_CPU,
.class_init = kvm_cpu_accel_class_init,
.is_available = target_base_riscv,
.abstract = true,
};
static void kvm_cpu_accel_register_types(void)
target/riscv/tcg/tcg-cpu.c
+1
View File
@@ -1748,6 +1748,7 @@ static const TypeInfo riscv_tcg_cpu_accel_type_info = {
.parent = TYPE_ACCEL_CPU,
.class_init = riscv_tcg_cpu_accel_class_init,
.is_available = target_base_riscv,
.abstract = true,
};
target/rx/helper.h
+6 -6
View File
@@ -3,11 +3,11 @@ DEF_HELPER_1(raise_access_fault, noreturn, env)
DEF_HELPER_1(raise_privilege_violation, noreturn, env)
DEF_HELPER_1(wait, noreturn, env)
DEF_HELPER_2(trap, noreturn, env, i32)
DEF_HELPER_3(rx_fadd, f32, env, f32, f32)
DEF_HELPER_3(rx_fsub, f32, env, f32, f32)
DEF_HELPER_3(rx_fmul, f32, env, f32, f32)
DEF_HELPER_3(rx_fdiv, f32, env, f32, f32)
DEF_HELPER_3(rx_fcmp, void, env, f32, f32)
DEF_HELPER_3(fadd, f32, env, f32, f32)
DEF_HELPER_3(fsub, f32, env, f32, f32)
DEF_HELPER_3(fmul, f32, env, f32, f32)
DEF_HELPER_3(fdiv, f32, env, f32, f32)
DEF_HELPER_3(fcmp, void, env, f32, f32)
DEF_HELPER_2(ftoi, i32, env, f32)
DEF_HELPER_2(round, i32, env, f32)
DEF_HELPER_2(itof, f32, env, i32)
@@ -17,7 +17,7 @@ DEF_HELPER_2(set_psw_rte, void, env, i32)
DEF_HELPER_2(set_psw, void, env, i32)
DEF_HELPER_1(pack_psw, i32, env)
DEF_HELPER_3(div, i32, env, i32, i32)
DEF_HELPER_3(rx_divu, i32, env, i32, i32)
DEF_HELPER_3(divu, i32, env, i32, i32)
DEF_HELPER_1(scmpu, void, env)
DEF_HELPER_1(smovu, void, env)
DEF_HELPER_1(smovf, void, env)
target/rx/op_helper.c
+30 -30
View File
@@ -46,17 +46,17 @@ static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte)
}
}
void helper_set_psw(CPURXState *env, uint32_t psw)
void HELPER(set_psw)(CPURXState *env, uint32_t psw)
{
_set_psw(env, psw, 0);
}
void helper_set_psw_rte(CPURXState *env, uint32_t psw)
void HELPER(set_psw_rte)(CPURXState *env, uint32_t psw)
{
_set_psw(env, psw, 1);
}
uint32_t helper_pack_psw(CPURXState *env)
uint32_t HELPER(pack_psw)(CPURXState *env)
{
return rx_cpu_pack_psw(env);
}
@@ -120,7 +120,7 @@ static void update_fpsw(CPURXState *env, float32 ret, uintptr_t retaddr)
}
}
void helper_set_fpsw(CPURXState *env, uint32_t val)
void HELPER(set_fpsw)(CPURXState *env, uint32_t val)
{
static const int roundmode[] = {
float_round_nearest_even,
@@ -139,7 +139,7 @@ void helper_set_fpsw(CPURXState *env, uint32_t val)
}
#define FLOATOP(op, func) \
float32 helper_##op(CPURXState *env, float32 t0, float32 t1) \
float32 HELPER(op)(CPURXState *env, float32 t0, float32 t1) \
{ \
float32 ret; \
ret = func(t0, t1, &env->fp_status); \
@@ -147,12 +147,12 @@ void helper_set_fpsw(CPURXState *env, uint32_t val)
return ret; \
}
FLOATOP(rx_fadd, float32_add)
FLOATOP(rx_fsub, float32_sub)
FLOATOP(rx_fmul, float32_mul)
FLOATOP(rx_fdiv, float32_div)
FLOATOP(fadd, float32_add)
FLOATOP(fsub, float32_sub)
FLOATOP(fmul, float32_mul)
FLOATOP(fdiv, float32_div)
void helper_rx_fcmp(CPURXState *env, float32 t0, float32 t1)
void HELPER(fcmp)(CPURXState *env, float32 t0, float32 t1)
{
int st;
st = float32_compare(t0, t1, &env->fp_status);
@@ -172,7 +172,7 @@ void helper_rx_fcmp(CPURXState *env, float32 t0, float32 t1)
}
}
uint32_t helper_ftoi(CPURXState *env, float32 t0)
uint32_t HELPER(ftoi)(CPURXState *env, float32 t0)
{
uint32_t ret;
ret = float32_to_int32_round_to_zero(t0, &env->fp_status);
@@ -180,7 +180,7 @@ uint32_t helper_ftoi(CPURXState *env, float32 t0)
return ret;
}
uint32_t helper_round(CPURXState *env, float32 t0)
uint32_t HELPER(round)(CPURXState *env, float32 t0)
{
uint32_t ret;
ret = float32_to_int32(t0, &env->fp_status);
@@ -188,7 +188,7 @@ uint32_t helper_round(CPURXState *env, float32 t0)
return ret;
}
float32 helper_itof(CPURXState *env, uint32_t t0)
float32 HELPER(itof)(CPURXState *env, uint32_t t0)
{
float32 ret;
ret = int32_to_float32(t0, &env->fp_status);
@@ -197,7 +197,7 @@ float32 helper_itof(CPURXState *env, uint32_t t0)
}
/* string operations */
void helper_scmpu(CPURXState *env)
void HELPER(scmpu)(CPURXState *env)
{
uint8_t tmp0, tmp1;
if (env->regs[3] == 0) {
@@ -234,7 +234,7 @@ static void (* const cpu_stfn[])(CPUArchState *env,
cpu_stb_data_ra, cpu_stw_le_data_ra, cpu_stl_le_data_ra,
};
void helper_sstr(CPURXState *env, uint32_t sz)
void HELPER(sstr)(CPURXState *env, uint32_t sz)
{
tcg_debug_assert(sz < 3);
while (env->regs[3] != 0) {
@@ -266,23 +266,23 @@ static void smov(uint32_t mode, CPURXState *env)
}
}
void helper_smovu(CPURXState *env)
void HELPER(smovu)(CPURXState *env)
{
smov(OP_SMOVU, env);
}
void helper_smovf(CPURXState *env)
void HELPER(smovf)(CPURXState *env)
{
smov(OP_SMOVF, env);
}
void helper_smovb(CPURXState *env)
void HELPER(smovb)(CPURXState *env)
{
smov(OP_SMOVB, env);
}
void helper_suntil(CPURXState *env, uint32_t sz)
void HELPER(suntil)(CPURXState *env, uint32_t sz)
{
uint32_t tmp;
tcg_debug_assert(sz < 3);
@@ -301,7 +301,7 @@ void helper_suntil(CPURXState *env, uint32_t sz)
env->psw_c = (tmp <= env->regs[2]);
}
void helper_swhile(CPURXState *env, uint32_t sz)
void HELPER(swhile)(CPURXState *env, uint32_t sz)
{
uint32_t tmp;
tcg_debug_assert(sz < 3);
@@ -321,7 +321,7 @@ void helper_swhile(CPURXState *env, uint32_t sz)
}
/* accumulator operations */
void helper_rmpa(CPURXState *env, uint32_t sz)
void HELPER(rmpa)(CPURXState *env, uint32_t sz)
{
uint64_t result_l, prev;
int32_t result_h;
@@ -363,7 +363,7 @@ void helper_rmpa(CPURXState *env, uint32_t sz)
env->regs[4] = result_l & 0xffffffff;
}
void helper_racw(CPURXState *env, uint32_t imm)
void HELPER(racw)(CPURXState *env, uint32_t imm)
{
int64_t acc;
acc = env->acc;
@@ -379,7 +379,7 @@ void helper_racw(CPURXState *env, uint32_t imm)
env->acc = acc;
}
void helper_satr(CPURXState *env)
void HELPER(satr)(CPURXState *env)
{
if (env->psw_o >> 31) {
if ((int)env->psw_s < 0) {
@@ -395,7 +395,7 @@ void helper_satr(CPURXState *env)
}
/* div */
uint32_t helper_div(CPURXState *env, uint32_t num, uint32_t den)
uint32_t HELPER(div)(CPURXState *env, uint32_t num, uint32_t den)
{
uint32_t ret = num;
if (!((num == INT_MIN && den == -1) || den == 0)) {
@@ -407,7 +407,7 @@ uint32_t helper_div(CPURXState *env, uint32_t num, uint32_t den)
return ret;
}
uint32_t helper_rx_divu(CPURXState *env, uint32_t num, uint32_t den)
uint32_t HELPER(divu)(CPURXState *env, uint32_t num, uint32_t den)
{
uint32_t ret = num;
if (den != 0) {
@@ -430,22 +430,22 @@ void raise_exception(CPURXState *env, int index,
cpu_loop_exit_restore(cs, retaddr);
}
G_NORETURN void helper_raise_privilege_violation(CPURXState *env)
G_NORETURN void HELPER(raise_privilege_violation)(CPURXState *env)
{
raise_exception(env, RX_EXCP_PRIVILEGE_VIOLATION, GETPC());
}
G_NORETURN void helper_raise_access_fault(CPURXState *env)
G_NORETURN void HELPER(raise_access_fault)(CPURXState *env)
{
raise_exception(env, RX_EXCP_ACCESS, GETPC());
}
G_NORETURN void helper_raise_illegal_instruction(CPURXState *env)
G_NORETURN void HELPER(raise_illegal_instruction)(CPURXState *env)
{
raise_exception(env, RX_EXCP_ILLEGAL_INSTRUCTION, GETPC());
}
G_NORETURN void helper_wait(CPURXState *env)
G_NORETURN void HELPER(wait)(CPURXState *env)
{
CPUState *cs = env_cpu(env);
@@ -455,7 +455,7 @@ G_NORETURN void helper_wait(CPURXState *env)
raise_exception(env, EXCP_HLT, 0);
}
G_NORETURN void helper_trap(CPURXState *env, uint32_t vec)
G_NORETURN void HELPER(trap)(CPURXState *env, uint32_t vec)
{
raise_exception(env, RX_EXCP_TRAP_BASE + vec, 0);
}
target/rx/translate.c
+7 -7
View File
@@ -1252,7 +1252,7 @@ static void rx_div(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
static void rx_divu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
gen_helper_rx_divu(ret, tcg_env, arg1, arg2);
gen_helper_divu(ret, tcg_env, arg1, arg2);
}
/* div #imm, rd */
@@ -1864,16 +1864,16 @@ static bool trans_SATR(DisasContext *ctx, arg_SATR *a)
return true; \
}
FOP(FADD, rx_fadd)
FOP(FSUB, rx_fsub)
FOP(FMUL, rx_fmul)
FOP(FDIV, rx_fdiv)
FOP(FADD, fadd)
FOP(FSUB, fsub)
FOP(FMUL, fmul)
FOP(FDIV, fdiv)
/* fcmp #imm, rd */
static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a)
{
TCGv_i32 imm = tcg_constant_i32(li(ctx, 0));
gen_helper_rx_fcmp(tcg_env, cpu_regs[a->rd], imm);
gen_helper_fcmp(tcg_env, cpu_regs[a->rd], imm);
return true;
}
@@ -1884,7 +1884,7 @@ static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a)
TCGv_i32 val, mem;
mem = tcg_temp_new_i32();
val = rx_load_source(ctx, mem, a->ld, MO_32, a->rs);
gen_helper_rx_fcmp(tcg_env, cpu_regs[a->rd], val);
gen_helper_fcmp(tcg_env, cpu_regs[a->rd], val);
return true;
}
target/sparc/crypto_helper.c
+15 -15
View File
@@ -52,42 +52,42 @@ static uint64_t aes_round(uint64_t key, uint64_t s2, uint64_t s3,
return r.d[out];
}
uint64_t helper_aes_eround01(uint64_t key, uint64_t s2, uint64_t s3)
uint64_t HELPER(aes_eround01)(uint64_t key, uint64_t s2, uint64_t s3)
{
return aes_round(key, s2, s3, 0, false, false);
}
uint64_t helper_aes_eround23(uint64_t key, uint64_t s2, uint64_t s3)
uint64_t HELPER(aes_eround23)(uint64_t key, uint64_t s2, uint64_t s3)
{
return aes_round(key, s2, s3, 1, false, false);
}
uint64_t helper_aes_dround01(uint64_t key, uint64_t s2, uint64_t s3)
uint64_t HELPER(aes_dround01)(uint64_t key, uint64_t s2, uint64_t s3)
{
return aes_round(key, s2, s3, 0, true, false);
}
uint64_t helper_aes_dround23(uint64_t key, uint64_t s2, uint64_t s3)
uint64_t HELPER(aes_dround23)(uint64_t key, uint64_t s2, uint64_t s3)
{
return aes_round(key, s2, s3, 1, true, false);
}
uint64_t helper_aes_eround01_l(uint64_t key, uint64_t s2, uint64_t s3)
uint64_t HELPER(aes_eround01_l)(uint64_t key, uint64_t s2, uint64_t s3)
{
return aes_round(key, s2, s3, 0, false, true);
}
uint64_t helper_aes_eround23_l(uint64_t key, uint64_t s2, uint64_t s3)
uint64_t HELPER(aes_eround23_l)(uint64_t key, uint64_t s2, uint64_t s3)
{
return aes_round(key, s2, s3, 1, false, true);
}
uint64_t helper_aes_dround01_l(uint64_t key, uint64_t s2, uint64_t s3)
uint64_t HELPER(aes_dround01_l)(uint64_t key, uint64_t s2, uint64_t s3)
{
return aes_round(key, s2, s3, 0, true, true);
}
uint64_t helper_aes_dround23_l(uint64_t key, uint64_t s2, uint64_t s3)
uint64_t HELPER(aes_dround23_l)(uint64_t key, uint64_t s2, uint64_t s3)
{
return aes_round(key, s2, s3, 1, true, true);
}
@@ -114,7 +114,7 @@ static uint32_t aes_subword(uint32_t x)
* AES Cryptographic Operations 4-operand (Section 7.3)
* AES key expansion with RotWord, SubWord, and RCON.
*/
uint64_t helper_aes_kexpand1(uint64_t rs1, uint64_t rs2, uint32_t imm)
uint64_t HELPER(aes_kexpand1)(uint64_t rs1, uint64_t rs2, uint32_t imm)
{
static const uint8_t rcon[10] = {
0x01, 0x02, 0x04, 0x08, 0x10,
@@ -135,7 +135,7 @@ uint64_t helper_aes_kexpand1(uint64_t rs1, uint64_t rs2, uint32_t imm)
* AES Cryptographic Operations 3-operand (Section 7.4)
* AES key expansion with SubWord, without RotWord or RCON.
*/
uint64_t helper_aes_kexpand0(uint64_t rs1, uint64_t rs2)
uint64_t HELPER(aes_kexpand0)(uint64_t rs1, uint64_t rs2)
{
return aes_kexpand(rs1, aes_subword(rs2));
}
@@ -144,7 +144,7 @@ uint64_t helper_aes_kexpand0(uint64_t rs1, uint64_t rs2)
* AES Cryptographic Operations 3-operand (Section 7.4)
* AES key expansion without SubWord, RotWord, or RCON.
*/
uint64_t helper_aes_kexpand2(uint64_t rs1, uint64_t rs2)
uint64_t HELPER(aes_kexpand2)(uint64_t rs1, uint64_t rs2)
{
return aes_kexpand(rs1, (uint32_t)rs2);
}
@@ -153,7 +153,7 @@ uint64_t helper_aes_kexpand2(uint64_t rs1, uint64_t rs2)
* CRC32C Operation 3-operand (Section 7.19)
* Accumulate CRC32C over the eight bytes of rs2, most significant first.
*/
uint64_t helper_crc32c(uint64_t rs1, uint64_t rs2)
uint64_t HELPER(crc32c)(uint64_t rs1, uint64_t rs2)
{
uint8_t buf[8];
/* IV and result are byte-swapped in the register. */
@@ -172,7 +172,7 @@ uint64_t helper_crc32c(uint64_t rs1, uint64_t rs2)
* Compress one SHA-1 block from f8-f23 into f0-f4.
* Clear f5 to match SPARC M7 behavior.
*/
void helper_sha1(CPUSPARCState *env)
void HELPER(sha1)(CPUSPARCState *env)
{
uint32_t a = env->fpr[0].l.upper;
uint32_t b = env->fpr[0].l.lower;
@@ -396,7 +396,7 @@ static void sha512_compress(uint64_t state[8], const uint64_t block[16])
}
/* Compress one SHA-256 block from f8-f23 into f0-f7. */
void helper_sha256(CPUSPARCState *env)
void HELPER(sha256)(CPUSPARCState *env)
{
uint32_t state[8], block[16];
@@ -422,7 +422,7 @@ void helper_sha256(CPUSPARCState *env)
* Compress one SHA-512 block from FD16, FD18, ..., FD46
* into FD0, FD2, ..., FD14.
*/
void helper_sha512(CPUSPARCState *env)
void HELPER(sha512)(CPUSPARCState *env)
{
uint64_t state[8], block[16];
target/tricore/fpu_helper.c
+6 -6
View File
@@ -118,7 +118,7 @@ static void f_update_psw_flags(CPUTriCoreState *env, uint8_t flags)
}
#define FADD_SUB(op) \
uint32_t HELPER(tricore_f##op)(CPUTriCoreState *env, uint32_t r1, uint32_t r2) \
uint32_t HELPER(f##op)(CPUTriCoreState *env, uint32_t r1, uint32_t r2) \
{ \
float32 arg1 = make_float32(r1); \
float32 arg2 = make_float32(r2); \
@@ -144,7 +144,7 @@ uint32_t HELPER(tricore_f##op)(CPUTriCoreState *env, uint32_t r1, uint32_t r2) \
FADD_SUB(add)
FADD_SUB(sub)
uint32_t HELPER(tricore_fmul)(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
uint32_t HELPER(fmul)(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
uint32_t flags;
float32 arg1 = make_float32(r1);
@@ -251,7 +251,7 @@ uint32_t HELPER(qseed)(CPUTriCoreState *env, uint32_t r1)
return (uint32_t) result;
}
uint32_t HELPER(tricore_fdiv)(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
uint32_t HELPER(fdiv)(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
uint32_t flags;
float32 arg1 = make_float32(r1);
@@ -331,7 +331,7 @@ uint32_t HELPER(fmsub)(CPUTriCoreState *env, uint32_t r1,
return (uint32_t)f_result;
}
uint32_t HELPER(tricore_fcmp)(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
uint32_t HELPER(fcmp)(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
{
uint32_t result, flags;
float32 arg1 = make_float32(r1);
@@ -354,7 +354,7 @@ uint32_t HELPER(tricore_fcmp)(CPUTriCoreState *env, uint32_t r1, uint32_t r2)
return result;
}
uint32_t HELPER(tricore_ftoi)(CPUTriCoreState *env, uint32_t arg)
uint32_t HELPER(ftoi)(CPUTriCoreState *env, uint32_t arg)
{
float32 f_arg = make_float32(arg);
int32_t result, flags;
@@ -447,7 +447,7 @@ uint32_t HELPER(ftohp)(CPUTriCoreState *env, uint32_t arg)
return result;
}
uint32_t HELPER(tricore_itof)(CPUTriCoreState *env, uint32_t arg)
uint32_t HELPER(itof)(CPUTriCoreState *env, uint32_t arg)
{
float32 f_result;
uint32_t flags;
target/tricore/helper.h
+7 -7
View File
@@ -102,18 +102,18 @@ DEF_HELPER_FLAGS_1(parity, TCG_CALL_NO_RWG_SE, i32, i32)
/* float */
DEF_HELPER_FLAGS_4(pack, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32, i32)
DEF_HELPER_1(unpack, i64, i32)
DEF_HELPER_3(tricore_fadd, i32, env, i32, i32)
DEF_HELPER_3(tricore_fsub, i32, env, i32, i32)
DEF_HELPER_3(tricore_fmul, i32, env, i32, i32)
DEF_HELPER_3(tricore_fdiv, i32, env, i32, i32)
DEF_HELPER_3(fadd, i32, env, i32, i32)
DEF_HELPER_3(fsub, i32, env, i32, i32)
DEF_HELPER_3(fmul, i32, env, i32, i32)
DEF_HELPER_3(fdiv, i32, env, i32, i32)
DEF_HELPER_4(fmadd, i32, env, i32, i32, i32)
DEF_HELPER_4(fmsub, i32, env, i32, i32, i32)
DEF_HELPER_3(tricore_fcmp, i32, env, i32, i32)
DEF_HELPER_3(fcmp, i32, env, i32, i32)
DEF_HELPER_2(qseed, i32, env, i32)
DEF_HELPER_2(tricore_ftoi, i32, env, i32)
DEF_HELPER_2(ftoi, i32, env, i32)
DEF_HELPER_2(ftohp, i32, env, i32)
DEF_HELPER_2(hptof, i32, env, i32)
DEF_HELPER_2(tricore_itof, i32, env, i32)
DEF_HELPER_2(itof, i32, env, i32)
DEF_HELPER_2(utof, i32, env, i32)
DEF_HELPER_2(ftoiz, i32, env, i32)
DEF_HELPER_2(ftou, i32, env, i32)
target/tricore/translate.c
+7 -7
View File
@@ -6290,10 +6290,10 @@ static void decode_rr_divide(DisasContext *ctx)
}
break;
case OPC2_32_RR_MUL_F:
gen_helper_tricore_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
gen_helper_fmul(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_DIV_F:
gen_helper_tricore_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
gen_helper_fdiv(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_FTOHP:
if (has_feature(ctx, TRICORE_FEATURE_162)) {
@@ -6310,13 +6310,13 @@ static void decode_rr_divide(DisasContext *ctx)
}
break;
case OPC2_32_RR_CMP_F:
gen_helper_tricore_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
gen_helper_fcmp(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r2]);
break;
case OPC2_32_RR_FTOI:
gen_helper_tricore_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
gen_helper_ftoi(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_ITOF:
gen_helper_tricore_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
gen_helper_itof(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
break;
case OPC2_32_RR_FTOU:
gen_helper_ftou(cpu_gpr_d[r3], tcg_env, cpu_gpr_d[r1]);
@@ -6725,10 +6725,10 @@ static void decode_rrr_divide(DisasContext *ctx)
}
break;
case OPC2_32_RRR_ADD_F:
gen_helper_tricore_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
gen_helper_fadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_SUB_F:
gen_helper_tricore_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
gen_helper_fsub(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1], cpu_gpr_d[r3]);
break;
case OPC2_32_RRR_MADD_F:
gen_helper_fmadd(cpu_gpr_d[r4], tcg_env, cpu_gpr_d[r1],
tests/unit/test-multi-target.c
+26 -8
View File
@@ -30,13 +30,20 @@
/* stub for system/main.c */
int (*qemu_main)(void);
static void test_qom_types_are_unique(void)
static void test_qom_types_are_unique(const void *data)
{
module_call_init(MODULE_INIT_TARGET_INFO);
g_autoptr(GSList) targets = object_class_get_list(TYPE_TARGET_INFO, false);
g_assert(targets);
const TargetInfo *first_ti = TARGET_INFO_CLASS(targets->data)->target_info;
target_info_qom_set_target_info(first_ti);
const TargetInfo *ti = data;
/* QOM types can be initialized only once, so do it in a subprocess. */
if (!g_test_subprocess()) {
/* parent process path - respawn this exact test path */
g_test_trap_subprocess(NULL, 0, G_TEST_SUBPROCESS_INHERIT_STDERR);
g_test_trap_assert_passed();
return;
}
/* child process path */
target_info_qom_set_target_info(ti);
/* register all types */
module_call_init(MODULE_INIT_QOM);
@@ -47,7 +54,18 @@ static void test_qom_types_are_unique(void)
int main(int argc, char **argv)
{
g_test_init(&argc, &argv, NULL);
g_test_add_func("/multi-targets/qom-types-are-unique",
test_qom_types_are_unique);
module_call_init(MODULE_INIT_TARGET_INFO);
g_autoptr(GSList) targets = object_class_get_list_sorted(TYPE_TARGET_INFO,
false);
g_assert(targets);
for (GSList *elem = targets; elem; elem = elem->next) {
const TargetInfo *ti = TARGET_INFO_CLASS(elem->data)->target_info;
g_autofree char *path =
g_strdup_printf("/multi-targets/qom-types-are-unique/%s",
ti->target_name);
g_test_add_data_func(path, ti, test_qom_types_are_unique);
}
return g_test_run();
}