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hw/hexagon: convert virt board to hex-board
Build the virt machine with the hex-board helpers instead of its own copies, and drop the machine state that nothing used. The machine, its device tree and its devices are unchanged; virt writes interrupts as the bare line number. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
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Brian Cain committed
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@@ -8,26 +8,15 @@
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "hw/hexagon/virt.h"
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#include "elf.h"
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#include "hw/char/pl011.h"
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#include "hw/core/clock.h"
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#include "hw/core/sysbus-fdt.h"
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#include "hw/hexagon/hexagon.h"
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#include "hw/hexagon/hex-board.h"
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#include "hw/hexagon/hex-subsys.h"
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#include "hw/core/loader.h"
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#include "hw/core/qdev-properties.h"
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#include "hw/core/qdev-clock.h"
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#include "hw/core/register.h"
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#include "qemu/error-report.h"
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#include "qemu/guest-random.h"
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#include "qemu/target-info.h"
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#include "qemu/units.h"
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#include "machine_cfg_v68n_1024.h.inc"
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#include "system/address-spaces.h"
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#include "system/device_tree.h"
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#include "system/reset.h"
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#include "system/system.h"
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#include <libfdt.h>
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enum {
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VIRT_UART0,
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@@ -49,222 +38,9 @@ static const MemMapEntry base_memmap[] = {
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};
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static void create_fdt(HexagonVirtMachineState *vms)
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{
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MachineState *ms = MACHINE(vms);
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void *fdt = create_device_tree(&vms->fdt_size);
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uint8_t rng_seed[32];
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if (!fdt) {
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error_report("create_device_tree() failed");
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exit(1);
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}
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ms->fdt = fdt;
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qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1);
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qemu_fdt_setprop_string(fdt, "/", "model", "hexagon-virt,qemu");
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qemu_fdt_setprop_string(fdt, "/", "compatible", "qcom,sm8150");
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qemu_fdt_add_subnode(fdt, "/soc");
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qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2);
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qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1);
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qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0);
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qemu_fdt_add_subnode(fdt, "/chosen");
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qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed));
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qemu_fdt_setprop(fdt, "/chosen", "rng-seed", rng_seed, sizeof(rng_seed));
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}
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static int32_t fdt_add_l2vic(HexagonVirtMachineState *vms,
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const struct hexagon_machine_config *m_cfg)
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{
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MachineState *ms = MACHINE(vms);
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int32_t l2vic_phandle = qemu_fdt_alloc_phandle(ms->fdt);
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char *nodename = g_strdup_printf("/soc/interrupt-controller@%x",
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m_cfg->l2vic_base);
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const char compat[] = "qcom,h2-pic\0hvm-pic";
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qemu_fdt_setprop_cell(ms->fdt, "/soc", "interrupt-parent", l2vic_phandle);
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qemu_fdt_add_subnode(ms->fdt, nodename);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x0);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "#interrupt-cells", 0x1);
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qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
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qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0,
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m_cfg->l2vic_base, m_cfg->l2vic_size);
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qemu_fdt_setprop(ms->fdt, nodename, "interrupt-controller", NULL, 0);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle", l2vic_phandle);
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g_free(nodename);
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return l2vic_phandle;
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}
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static void fdt_add_hvx(HexagonVirtMachineState *vms,
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const struct hexagon_machine_config *m_cfg)
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{
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const MachineState *ms = MACHINE(vms);
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uint32_t vtcm_size_bytes = m_cfg->cfgtable.vtcm_size_kb * 1024;
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if (vtcm_size_bytes > 0) {
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qemu_fdt_add_subnode(ms->fdt, "/soc/vtcm");
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qemu_fdt_setprop_string(ms->fdt, "/soc/vtcm", "compatible",
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"qcom,hexagon_vtcm");
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assert(sizeof(m_cfg->cfgtable.vtcm_base) == sizeof(uint32_t));
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qemu_fdt_setprop_cells(ms->fdt, "/soc/vtcm", "reg", 0,
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m_cfg->cfgtable.vtcm_base << 16,
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vtcm_size_bytes);
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}
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if (m_cfg->cfgtable.ext_contexts > 0) {
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qemu_fdt_add_subnode(ms->fdt, "/soc/hvx");
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qemu_fdt_setprop_string(ms->fdt, "/soc/hvx", "compatible",
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"qcom,hexagon-hvx");
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qemu_fdt_setprop_cells(ms->fdt, "/soc/hvx", "qcom,hvx-max-ctxts",
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m_cfg->cfgtable.ext_contexts);
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qemu_fdt_setprop_cells(ms->fdt, "/soc/hvx", "qcom,hvx-vlength",
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m_cfg->cfgtable.hvx_vec_log_length);
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}
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}
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static int32_t fdt_add_clocks(const HexagonVirtMachineState *vms)
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{
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MachineState *ms = MACHINE(vms);
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int32_t clk_phandle = qemu_fdt_alloc_phandle(ms->fdt);
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qemu_fdt_add_subnode(ms->fdt, "/apb-pclk");
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qemu_fdt_setprop_string(ms->fdt, "/apb-pclk", "compatible", "fixed-clock");
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qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "#clock-cells", 0x0);
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qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "clock-frequency", 24000000);
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qemu_fdt_setprop_string(ms->fdt, "/apb-pclk", "clock-output-names",
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"clk24mhz");
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qemu_fdt_setprop_cell(ms->fdt, "/apb-pclk", "phandle", clk_phandle);
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return clk_phandle;
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}
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static void fdt_add_uart(const HexagonVirtMachineState *vms, int uart,
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int32_t clk_phandle, int32_t l2vic_phandle)
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{
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char *nodename;
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hwaddr base = base_memmap[uart].base;
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hwaddr size = base_memmap[uart].size;
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assert(uart == 0);
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const char compat[] = "arm,pl011\0arm,primecell";
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const char clocknames[] = "uartclk\0apb_pclk";
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MachineState *ms = MACHINE(vms);
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DeviceState *dev;
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SysBusDevice *s;
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dev = qdev_new(TYPE_PL011);
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s = SYS_BUS_DEVICE(dev);
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qdev_prop_set_chr(dev, "chardev", serial_hd(0));
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qdev_connect_clock_in(dev, "clk", vms->apb_clk);
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, base);
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sysbus_connect_irq(s, 0,
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qdev_get_gpio_in(vms->parent_obj.l2vic, VIRT_UART0_IRQ));
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nodename = g_strdup_printf("/pl011@%" PRIx64, base);
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qemu_fdt_add_subnode(ms->fdt, nodename);
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/* Note that we can't use setprop_string because of the embedded NUL */
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qemu_fdt_setprop(ms->fdt, nodename, "compatible", compat, sizeof(compat));
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qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, size);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", VIRT_UART0_IRQ);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
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l2vic_phandle);
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qemu_fdt_setprop_cells(ms->fdt, nodename, "clocks", clk_phandle,
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clk_phandle);
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qemu_fdt_setprop(ms->fdt, nodename, "clock-names", clocknames,
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sizeof(clocknames));
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qemu_fdt_setprop_string(ms->fdt, "/chosen", "stdout-path", nodename);
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qemu_fdt_add_subnode(ms->fdt, "/aliases");
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qemu_fdt_setprop_string(ms->fdt, "/aliases", "serial0", nodename);
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g_free(nodename);
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}
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static void fdt_add_cpu_nodes(const HexagonVirtMachineState *vms)
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{
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MachineState *ms = MACHINE(vms);
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qemu_fdt_add_subnode(ms->fdt, "/cpus");
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qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#address-cells", 0x1);
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qemu_fdt_setprop_cell(ms->fdt, "/cpus", "#size-cells", 0x0);
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/* cpu nodes */
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for (int num = ms->smp.cpus - 1; num >= 0; num--) {
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char *nodename = g_strdup_printf("/cpus/cpu@%d", num);
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qemu_fdt_add_subnode(ms->fdt, nodename);
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qemu_fdt_setprop_string(ms->fdt, nodename, "device_type", "cpu");
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qemu_fdt_setprop_cell(ms->fdt, nodename, "reg", num);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "phandle",
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qemu_fdt_alloc_phandle(ms->fdt));
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g_free(nodename);
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}
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}
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static void create_virtio_devices(HexagonVirtMachineState *vms,
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int32_t l2vic_phandle)
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{
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MachineState *ms = MACHINE(vms);
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hwaddr size = base_memmap[VIRT_MMIO].size;
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for (int i = 0; i < VIRTIO_DEV_COUNT; i++) {
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int irq = VIRTIO_IRQ_BASE + i;
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hwaddr base = base_memmap[VIRT_MMIO].base + i * size;
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char *nodename = g_strdup_printf("/soc/virtio_mmio@%" PRIx64, base);
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DeviceState *dev = qdev_new("virtio-mmio");
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SysBusDevice *s = SYS_BUS_DEVICE(dev);
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object_property_add_child(OBJECT(MACHINE(vms)), "virtio-mmio[*]",
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OBJECT(dev));
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sysbus_realize_and_unref(s, &error_fatal);
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sysbus_mmio_map(s, 0, base);
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sysbus_connect_irq(s, 0,
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qdev_get_gpio_in(vms->parent_obj.l2vic, irq));
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vms->virtio_mmio[i] = dev;
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qemu_fdt_add_subnode(ms->fdt, nodename);
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qemu_fdt_setprop_string(ms->fdt, nodename, "compatible",
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"virtio,mmio");
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qemu_fdt_setprop_cells(ms->fdt, nodename, "reg", 0, base, size);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupts", irq);
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qemu_fdt_setprop_cell(ms->fdt, nodename, "interrupt-parent",
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l2vic_phandle);
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g_free(nodename);
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}
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}
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void hexagon_load_fdt(const HexagonVirtMachineState *vms)
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{
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MachineState *ms = MACHINE(vms);
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hwaddr fdt_addr = base_memmap[VIRT_FDT].base;
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uint32_t fdtsize = vms->fdt_size;
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g_assert(fdtsize <= base_memmap[VIRT_FDT].size);
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/* copy in the device tree */
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rom_add_blob_fixed_as("fdt", ms->fdt, fdtsize, fdt_addr,
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&address_space_memory);
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qemu_register_reset_nosnapshotload(
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qemu_fdt_randomize_seeds,
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rom_ptr_for_as(&address_space_memory, fdt_addr, fdtsize));
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}
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static uint64_t load_kernel(const HexagonVirtMachineState *vms)
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{
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MachineState *ms = MACHINE(vms);
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uint64_t entry = 0;
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if (load_elf_ram_sym(ms->kernel_filename, NULL, NULL, NULL, &entry, NULL,
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NULL, NULL, 0, EM_HEXAGON, 0, 0, &address_space_memory,
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false, NULL) > 0) {
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return entry;
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}
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error_report("error loading '%s'", ms->kernel_filename);
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exit(1);
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return hex_board_load_elf(MACHINE(vms)->kernel_filename, NULL, NULL, NULL);
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}
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static uint64_t load_bios(HexagonVirtMachineState *vms)
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@@ -283,75 +59,42 @@ static uint64_t load_bios(HexagonVirtMachineState *vms)
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return bios_addr; /* Return entry point at address 0x0 */
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}
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static void do_cpu_reset(void *opaque)
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{
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HexagonCPU *cpu = opaque;
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CPUState *cs = CPU(cpu);
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cpu_reset(cs);
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}
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static void virt_init(MachineState *ms)
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{
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HexagonVirtMachineState *vms = HEXAGON_VIRT_MACHINE(ms);
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const struct hexagon_machine_config *m_cfg = &v68n_1024;
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int32_t clk_phandle;
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int32_t l2vic_phandle;
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uint64_t start = 0;
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bool have_start = false;
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create_fdt(vms);
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hex_board_create_fdt(ms, "hexagon-virt,qemu", "qcom,sm8150",
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&vms->fdt_size);
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qemu_fdt_setprop_string(ms->fdt, "/chosen", "bootargs", ms->kernel_cmdline);
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vms->sys = get_system_memory();
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/* Create APB clock for peripherals */
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vms->apb_clk = clock_new(OBJECT(ms), "apb-pclk");
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clock_set_hz(vms->apb_clk, 24000000);
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hex_subsys_create(&vms->parent_obj, m_cfg, v68_rev);
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hex_board_create_tcm(m_cfg, &vms->tcm);
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hex_board_fdt_add_hvx(ms, m_cfg);
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if (m_cfg->l2tcm_size) {
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memory_region_init_ram(&vms->tcm, NULL, "tcm.ram", m_cfg->l2tcm_size,
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&error_fatal);
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memory_region_add_subregion(vms->sys, m_cfg->cfgtable.l2tcm_base << 16,
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&vms->tcm);
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l2vic_phandle = hex_board_fdt_add_l2vic(ms, m_cfg);
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hex_board_create_virtio(ms, base_memmap[VIRT_MMIO].base,
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base_memmap[VIRT_MMIO].size, VIRTIO_IRQ_BASE,
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VIRTIO_DEV_COUNT, l2vic_phandle);
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if (ms->kernel_filename) {
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start = load_kernel(vms);
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have_start = true;
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} else if (ms->firmware) {
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start = load_bios(vms);
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have_start = true;
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}
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hex_board_create_cpus(ms, have_start, start);
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fdt_add_hvx(vms, m_cfg);
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hex_board_fdt_add_cpus(ms);
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hex_board_create_uart(ms, base_memmap[VIRT_UART0].base,
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base_memmap[VIRT_UART0].size, VIRT_UART0_IRQ,
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l2vic_phandle);
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l2vic_phandle = fdt_add_l2vic(vms, m_cfg);
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create_virtio_devices(vms, l2vic_phandle);
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g_autofree HexagonCPU **cpus = g_new(HexagonCPU *, ms->smp.cpus);
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for (int i = 0; i < ms->smp.cpus; i++) {
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HexagonCPU *cpu = HEXAGON_CPU(object_new(ms->cpu_type));
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qemu_register_reset(do_cpu_reset, cpu);
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if (i == 0) {
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if (ms->kernel_filename) {
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uint64_t entry = load_kernel(vms);
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qdev_prop_set_uint32(DEVICE(cpu), "exec-start-addr", entry);
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} else if (ms->firmware) {
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uint64_t entry = load_bios(vms);
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qdev_prop_set_uint32(DEVICE(cpu), "exec-start-addr", entry);
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}
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}
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qdev_prop_set_uint32(DEVICE(cpu), "htid", i);
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qdev_prop_set_bit(DEVICE(cpu), "start-powered-off", (i != 0));
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hex_subsys_add_cpu(&vms->parent_obj, DEVICE(cpu));
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cpus[i] = cpu;
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}
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hex_subsys_realize_cluster(&vms->parent_obj);
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for (int i = 0; i < ms->smp.cpus; i++) {
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hex_subsys_realize_cpu(&vms->parent_obj, DEVICE(cpus[i]), (i == 0));
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}
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fdt_add_cpu_nodes(vms);
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clk_phandle = fdt_add_clocks(vms);
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fdt_add_uart(vms, VIRT_UART0, clk_phandle, l2vic_phandle);
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hexagon_load_fdt(vms);
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hex_board_load_fdt(ms, vms->fdt_size, base_memmap[VIRT_FDT].base);
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}
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@@ -17,15 +17,9 @@ struct HexagonVirtMachineState {
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HexagonCommonMachineState parent_obj;
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int fdt_size;
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MemoryRegion *sys;
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MemoryRegion tcm;
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MemoryRegion bios;
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Clock *apb_clk;
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DeviceState *virtio_mmio[VIRTIO_DEV_COUNT];
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};
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void hexagon_load_fdt(const struct HexagonVirtMachineState *vms);
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#define TYPE_HEXAGON_VIRT_MACHINE MACHINE_TYPE_NAME("virt")
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OBJECT_DECLARE_SIMPLE_TYPE(HexagonVirtMachineState, HEXAGON_VIRT_MACHINE)
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