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tcg: Generic expansion of tcg_gen_rem_*

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Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson committed 2026-10-24 17:14:49 +02:00
1 parent ede15210e2
commit 04ab234084
3 files changed
+21 -42
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include/tcg/tcg-op-common.h
-2
View File
@@ -123,7 +123,6 @@ void tcg_gen_plugin_mem_cb(TCGv_i64 addr, unsigned meminfo);
/* 32 bit ops */
void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_remu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
void tcg_gen_andc_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2);
@@ -204,7 +203,6 @@ void tcg_gen_st_i32(TCGv_i32 arg1, TCGv_ptr arg2, tcg_target_long offset);
/* 64 bit ops */
void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_remu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
void tcg_gen_andc_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2);
include/tcg/tcg-op-def.h.inc
+1
View File
@@ -15,6 +15,7 @@ DEF2(neg, TCGV, TCGV)
DEF2(not, TCGV, TCGV)
DEF3(or, TCGV, TCGV, TCGV)
DEF3(ori, TCGV, TCGV, TINT)
DEF3(rem, TCGV, TCGV, TCGV)
DEF3(sar, TCGV, TCGV, TCGV)
DEF3(sari, TCGV, TCGV, TINT)
DEF3(shl, TCGV, TCGV, TCGV)
tcg/tcg-op.c
+20 -40
View File
@@ -484,6 +484,26 @@ void tcg_gen_ori(TCGType type, TCGTemp *dst, TCGTemp *src1, int64_t src2)
}
}
void tcg_gen_rem(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2)
{
if (tcg_op_supported(INDEX_op_rems, type, 0)) {
tcg_gen_op_ttt(INDEX_op_rems, type, dst, src1, src2);
} else {
g_autoptr(TCGTemp) tmp = tcg_temp_new_ebb(type);
if (tcg_op_supported(INDEX_op_divs, type, 0)) {
tcg_gen_op_ttt(INDEX_op_divs, type, tmp, src1, src2);
tcg_gen_mul(type, tmp, tmp, src2);
tcg_gen_sub(type, dst, src1, tmp);
} else if (tcg_op_supported(INDEX_op_divs2, type, 0)) {
tcg_gen_sari(type, tmp, src1, tcg_type_bits(type) - 1);
tcg_gen_op_ttttt(INDEX_op_divs2, type, tmp, dst, src1, tmp, src2);
} else {
g_assert_not_reached();
}
}
}
void tcg_gen_sar(TCGType type, TCGTemp *dst, TCGTemp *src1, TCGTemp *src2)
{
tcg_gen_op_ttt(INDEX_op_sar, type, dst, src1, src2);
@@ -623,26 +643,6 @@ void tcg_gen_negsetcondi_i32(TCGCond cond, TCGv_i32 ret,
tcg_gen_negsetcond_i32(cond, ret, arg1, tcg_constant_i32(arg2));
}
void tcg_gen_rem_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (tcg_op_supported(INDEX_op_rems, TCG_TYPE_I32, 0)) {
tcg_gen_op3_i32(INDEX_op_rems, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
tcg_gen_op3_i32(INDEX_op_divs, t0, arg1, arg2);
tcg_gen_mul_i32(t0, t0, arg2);
tcg_gen_sub_i32(ret, arg1, t0);
tcg_temp_free_i32(t0);
} else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I32, 0)) {
TCGv_i32 t0 = tcg_temp_ebb_new_i32();
tcg_gen_sari_i32(t0, arg1, 31);
tcg_gen_op5_i32(INDEX_op_divs2, t0, ret, arg1, t0, arg2);
tcg_temp_free_i32(t0);
} else {
g_assert_not_reached();
}
}
void tcg_gen_divu_i32(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
{
if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I32, 0)) {
@@ -1537,26 +1537,6 @@ void tcg_gen_negsetcond_i64(TCGCond cond, TCGv_i64 ret,
}
}
void tcg_gen_rem_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (tcg_op_supported(INDEX_op_rems, TCG_TYPE_I64, 0)) {
tcg_gen_op3_i64(INDEX_op_rems, ret, arg1, arg2);
} else if (tcg_op_supported(INDEX_op_divs, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
tcg_gen_op3_i64(INDEX_op_divs, t0, arg1, arg2);
tcg_gen_mul_i64(t0, t0, arg2);
tcg_gen_sub_i64(ret, arg1, t0);
tcg_temp_free_i64(t0);
} else if (tcg_op_supported(INDEX_op_divs2, TCG_TYPE_I64, 0)) {
TCGv_i64 t0 = tcg_temp_ebb_new_i64();
tcg_gen_sari_i64(t0, arg1, 63);
tcg_gen_op5_i64(INDEX_op_divs2, t0, ret, arg1, t0, arg2);
tcg_temp_free_i64(t0);
} else {
g_assert_not_reached();
}
}
void tcg_gen_divu_i64(TCGv_i64 ret, TCGv_i64 arg1, TCGv_i64 arg2)
{
if (tcg_op_supported(INDEX_op_divu, TCG_TYPE_I64, 0)) {