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Merge tag 'v7.4-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6

Browse Source 
Pull crypto updates from Herbert Xu:
 "API:
   - Fix algif_skcipher source SG overrun
   - Allow hmac(sha512) for non-root users

  Algorithms:
   - Add wrapper for zeroing AES key context
   - Avoid redundant stream initialisations in zstd

  Drivers:
   - Remove hisilicon/sec.
   - Handle digest-only authenc requests in atmel
   - Handle zero-length skcipher requests in mxs-dcp
   - Lower the default priority of caam/qi2

  Others:
   - Optimise key comparison in rhashtable lookup that uses constant
     parameters"

* tag 'v7.4-p1' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (146 commits)
  crypto: atmel-tdes - consolidate error paths in atmel_tdes_dma_init()
  crypto: atmel-tdes - reuse fast in atmel_tdes_crypt_start()
  crypto: atmel-tdes - use separate DMA scatterlists
  MAINTAINERS: delete entry for John Allen
  hwrng: amd - use PMBASE_OFFSET consistently
  hwrng: cctrng - simplify cctrng_probe()
  hwrng: intel - simplify intel_rng_mod_init()
  crypto: qat - fix use of destroyed vf2pf_lock on VF restart
  crypto: qat - initialise state_lock on every path in adf_devmgr_add_dev()
  hwrng: imx-rngc - Use optional clock
  crypto: talitos - init tasklets before requesting IRQs
  crypto: algif_skcipher - rewind rounded output bytes
  crypto: algif_hash - Allow hmac(sha512) for unpriviledged users
  crypto: sa2ul - Remove unused fields
  hwrng: stm32 - use devm_platform_ioremap_resource() in stm32_rng_probe()
  hwrng: stm32 - drop redundant initializations
  hwrng: amd - simplify control flow in amd_rng_mod_init()
  hwrng: stm32 - reuse clock rate in stm32_rng_clock_freq_restrain()
  hwrng: stm32 - use swap() in stm32_rng_probe()
  hwrng: cctrng - drop redundant initializations
  ...
This commit is contained in:
Linus Torvalds committed 2026-10-22 09:36:46 -10:00
2 parents 2a08195e4d 178aff4cf4
commit bf23250845
144 files changed
+1758 -4270
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Documentation/ABI/testing/sysfs-driver-qat_kpt
+2 -1
View File
@@ -14,7 +14,8 @@ Contact: qat-linux@intel.com
Description:
(RW) Enables or disables Key Protection Technology (KPT).
Write 1 to enable KPT, or 0 to disable it.
Write 1 to enable KPT, or 0 to disable it. The device must be
in the down state before changing the KPT state.
Example usage::
Documentation/devicetree/bindings/crypto/hisilicon,hip06-sec.yaml
-134
View File
@@ -1,134 +0,0 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/crypto/hisilicon,hip06-sec.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon hip06/hip07 Security Accelerator
maintainers:
- Jonathan Cameron <Jonathan.Cameron@huawei.com>
properties:
compatible:
enum:
- hisilicon,hip06-sec
- hisilicon,hip07-sec
reg:
items:
- description: Registers for backend processing engines
- description: Registers for common functionality
- description: Registers for queue 0
- description: Registers for queue 1
- description: Registers for queue 2
- description: Registers for queue 3
- description: Registers for queue 4
- description: Registers for queue 5
- description: Registers for queue 6
- description: Registers for queue 7
- description: Registers for queue 8
- description: Registers for queue 9
- description: Registers for queue 10
- description: Registers for queue 11
- description: Registers for queue 12
- description: Registers for queue 13
- description: Registers for queue 14
- description: Registers for queue 15
interrupts:
items:
- description: SEC unit error queue interrupt
- description: Completion interrupt for queue 0
- description: Error interrupt for queue 0
- description: Completion interrupt for queue 1
- description: Error interrupt for queue 1
- description: Completion interrupt for queue 2
- description: Error interrupt for queue 2
- description: Completion interrupt for queue 3
- description: Error interrupt for queue 3
- description: Completion interrupt for queue 4
- description: Error interrupt for queue 4
- description: Completion interrupt for queue 5
- description: Error interrupt for queue 5
- description: Completion interrupt for queue 6
- description: Error interrupt for queue 6
- description: Completion interrupt for queue 7
- description: Error interrupt for queue 7
- description: Completion interrupt for queue 8
- description: Error interrupt for queue 8
- description: Completion interrupt for queue 9
- description: Error interrupt for queue 9
- description: Completion interrupt for queue 10
- description: Error interrupt for queue 10
- description: Completion interrupt for queue 11
- description: Error interrupt for queue 11
- description: Completion interrupt for queue 12
- description: Error interrupt for queue 12
- description: Completion interrupt for queue 13
- description: Error interrupt for queue 13
- description: Completion interrupt for queue 14
- description: Error interrupt for queue 14
- description: Completion interrupt for queue 15
- description: Error interrupt for queue 15
dma-coherent: true
iommus:
maxItems: 1
required:
- compatible
- reg
- interrupts
- dma-coherent
additionalProperties: false
examples:
- |
bus {
#address-cells = <2>;
#size-cells = <2>;
crypto@400d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x400 0xd0000000 0x0 0x10000
0x400 0xd2000000 0x0 0x10000
0x400 0xd2010000 0x0 0x10000
0x400 0xd2020000 0x0 0x10000
0x400 0xd2030000 0x0 0x10000
0x400 0xd2040000 0x0 0x10000
0x400 0xd2050000 0x0 0x10000
0x400 0xd2060000 0x0 0x10000
0x400 0xd2070000 0x0 0x10000
0x400 0xd2080000 0x0 0x10000
0x400 0xd2090000 0x0 0x10000
0x400 0xd20a0000 0x0 0x10000
0x400 0xd20b0000 0x0 0x10000
0x400 0xd20c0000 0x0 0x10000
0x400 0xd20d0000 0x0 0x10000
0x400 0xd20e0000 0x0 0x10000
0x400 0xd20f0000 0x0 0x10000
0x400 0xd2100000 0x0 0x10000>;
interrupts = <576 4>,
<577 1>, <578 4>,
<579 1>, <580 4>,
<581 1>, <582 4>,
<583 1>, <584 4>,
<585 1>, <586 4>,
<587 1>, <588 4>,
<589 1>, <590 4>,
<591 1>, <592 4>,
<593 1>, <594 4>,
<595 1>, <596 4>,
<597 1>, <598 4>,
<599 1>, <600 4>,
<601 1>, <602 4>,
<603 1>, <604 4>,
<605 1>, <606 4>,
<607 1>, <608 4>;
dma-coherent;
iommus = <&p1_smmu_alg_a 0x600>;
};
};
Documentation/devicetree/bindings/trivial-devices.yaml
+2
View File
@@ -69,6 +69,8 @@ properties:
- asteralabs,pt5161l
# ATECC508A - i2c h/w elliptic curve crypto module
- atmel,atecc508a
# ATECC608A - i2c h/w elliptic curve crypto module
- atmel,atecc608a
# ATECC608B - i2c h/w elliptic curve crypto module
- atmel,atecc608b
# ATSHA204 - i2c h/w symmetric crypto module
MAINTAINERS
+11 -2
View File
@@ -1088,7 +1088,6 @@ F: include/linux/cdx/*
AMD CRYPTOGRAPHIC COPROCESSOR (CCP) DRIVER
M: Tom Lendacky <thomas.lendacky@amd.com>
M: John Allen <john.allen@amd.com>
L: linux-crypto@vger.kernel.org
S: Supported
F: drivers/crypto/ccp/
@@ -10420,7 +10419,7 @@ F: include/video/
FREESCALE CAAM (Cryptographic Acceleration and Assurance Module) DRIVER
M: Horia Geantă <horia.geanta@nxp.com>
M: Pankaj Gupta <pankaj.gupta@nxp.com>
M: Gaurav Jain <gaurav.jain@nxp.com>
M: Sahil Malhotra <sahil.malhotra@nxp.com>
L: linux-crypto@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/crypto/fsl,sec-v4.0*
@@ -12523,6 +12522,7 @@ F: drivers/crypto/nx/Makefile
F: drivers/crypto/nx/nx-842*
F: include/linux/sw842.h
F: lib/842/
F: lib/tests/842_decompress_kunit.c
IBM Power in-Nest Crypto Acceleration
M: Breno Leitão <leitao@debian.org>
@@ -22582,6 +22582,15 @@ S: Maintained
F: Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml
F: drivers/i2c/busses/i2c-qcom-cci.c
QUALCOMM INLINE CRYPTO ENGINE DRIVER
M: Abel Vesa <abelvesa@kernel.org>
L: linux-arm-msm@vger.kernel.org
L: linux-crypto@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/crypto/qcom,inline-crypto-engine.yaml
F: drivers/soc/qcom/ice.c
F: include/soc/qcom/ice.h
QUALCOMM INTERCONNECT BWMON DRIVER
M: Krzysztof Kozlowski <krzk@kernel.org>
L: linux-arm-msm@vger.kernel.org
arch/arm/crypto/aes-neonbs-glue.c
+1 -1
View File
@@ -60,7 +60,7 @@ static int aesbs_setkey(struct crypto_skcipher *tfm, const u8 *in_key,
unsigned int key_len)
{
struct aesbs_ctx *ctx = crypto_skcipher_ctx(tfm);
struct crypto_aes_ctx rk;
struct crypto_aes_ctx rk __cleanup(aes_zeroize_ctx);
int err;
err = aes_expandkey(&rk, in_key, key_len);
arch/arm64/boot/dts/hisilicon/hip07.dtsi
-280
View File
@@ -1113,74 +1113,6 @@
num-pins = <2>;
};
};
p0_mbigen_alg_a:interrupt-controller@d0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xd0080000 0x0 0x10000>;
p0_mbigen_sec_a: intc_sec {
msi-parent = <&p0_its_dsa_a 0x40400>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <33>;
};
p0_mbigen_smmu_alg_a: intc_smmu_alg {
msi-parent = <&p0_its_dsa_a 0x40b1b>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <3>;
};
};
p0_mbigen_alg_b:interrupt-controller@8,d0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x8 0xd0080000 0x0 0x10000>;
p0_mbigen_sec_b: intc_sec {
msi-parent = <&p0_its_dsa_b 0x42400>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <33>;
};
p0_mbigen_smmu_alg_b: intc_smmu_alg {
msi-parent = <&p0_its_dsa_b 0x42b1b>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <3>;
};
};
p1_mbigen_alg_a:interrupt-controller@400,d0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x400 0xd0080000 0x0 0x10000>;
p1_mbigen_sec_a: intc_sec {
msi-parent = <&p1_its_dsa_a 0x44400>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <33>;
};
p1_mbigen_smmu_alg_a: intc_smmu_alg {
msi-parent = <&p1_its_dsa_a 0x44b1b>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <3>;
};
};
p1_mbigen_alg_b:interrupt-controller@408,d0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x408 0xd0080000 0x0 0x10000>;
p1_mbigen_sec_b: intc_sec {
msi-parent = <&p1_its_dsa_b 0x46400>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <33>;
};
p1_mbigen_smmu_alg_b: intc_smmu_alg {
msi-parent = <&p1_its_dsa_b 0x46b1b>;
interrupt-controller;
#interrupt-cells = <2>;
num-pins = <3>;
};
};
p0_mbigen_dsa_a: interrupt-controller@c0080000 {
compatible = "hisilicon,mbigen-v2";
reg = <0x0 0xc0080000 0x0 0x10000>;
@@ -1237,54 +1169,6 @@
hisilicon,broken-prefetch-cmd;
status = "disabled";
};
p0_smmu_alg_a: iommu@d0040000 {
compatible = "arm,smmu-v3";
reg = <0x0 0xd0040000 0x0 0x20000>;
interrupt-parent = <&p0_mbigen_smmu_alg_a>;
interrupts = <733 1>,
<734 1>,
<735 1>;
interrupt-names = "eventq", "gerror", "priq";
#iommu-cells = <1>;
dma-coherent;
hisilicon,broken-prefetch-cmd;
};
p0_smmu_alg_b: iommu@8d0040000 {
compatible = "arm,smmu-v3";
reg = <0x8 0xd0040000 0x0 0x20000>;
interrupt-parent = <&p0_mbigen_smmu_alg_b>;
interrupts = <733 1>,
<734 1>,
<735 1>;
interrupt-names = "eventq", "gerror", "priq";
#iommu-cells = <1>;
dma-coherent;
hisilicon,broken-prefetch-cmd;
};
p1_smmu_alg_a: iommu@400d0040000 {
compatible = "arm,smmu-v3";
reg = <0x400 0xd0040000 0x0 0x20000>;
interrupt-parent = <&p1_mbigen_smmu_alg_a>;
interrupts = <733 1>,
<734 1>,
<735 1>;
interrupt-names = "eventq", "gerror", "priq";
#iommu-cells = <1>;
dma-coherent;
hisilicon,broken-prefetch-cmd;
};
p1_smmu_alg_b: iommu@408d0040000 {
compatible = "arm,smmu-v3";
reg = <0x408 0xd0040000 0x0 0x20000>;
interrupt-parent = <&p1_mbigen_smmu_alg_b>;
interrupts = <733 1>,
<734 1>,
<735 1>;
interrupt-names = "eventq", "gerror", "priq";
#iommu-cells = <1>;
dma-coherent;
hisilicon,broken-prefetch-cmd;
};
soc {
compatible = "simple-bus";
@@ -1745,170 +1629,6 @@
0x0 0 0 4 &mbigen_pcie2_a 671 4>;
status = "disabled";
};
p0_sec_a: crypto@d0000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x0 0xd0000000 0x0 0x10000>,
<0x0 0xd2000000 0x0 0x10000>,
<0x0 0xd2010000 0x0 0x10000>,
<0x0 0xd2020000 0x0 0x10000>,
<0x0 0xd2030000 0x0 0x10000>,
<0x0 0xd2040000 0x0 0x10000>,
<0x0 0xd2050000 0x0 0x10000>,
<0x0 0xd2060000 0x0 0x10000>,
<0x0 0xd2070000 0x0 0x10000>,
<0x0 0xd2080000 0x0 0x10000>,
<0x0 0xd2090000 0x0 0x10000>,
<0x0 0xd20a0000 0x0 0x10000>,
<0x0 0xd20b0000 0x0 0x10000>,
<0x0 0xd20c0000 0x0 0x10000>,
<0x0 0xd20d0000 0x0 0x10000>,
<0x0 0xd20e0000 0x0 0x10000>,
<0x0 0xd20f0000 0x0 0x10000>,
<0x0 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p0_mbigen_sec_a>;
iommus = <&p0_smmu_alg_a 0x600>;
dma-coherent;
interrupts = <576 4>,
<577 1>, <578 4>,
<579 1>, <580 4>,
<581 1>, <582 4>,
<583 1>, <584 4>,
<585 1>, <586 4>,
<587 1>, <588 4>,
<589 1>, <590 4>,
<591 1>, <592 4>,
<593 1>, <594 4>,
<595 1>, <596 4>,
<597 1>, <598 4>,
<599 1>, <600 4>,
<601 1>, <602 4>,
<603 1>, <604 4>,
<605 1>, <606 4>,
<607 1>, <608 4>;
};
p0_sec_b: crypto@8d0000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x8 0xd0000000 0x0 0x10000>,
<0x8 0xd2000000 0x0 0x10000>,
<0x8 0xd2010000 0x0 0x10000>,
<0x8 0xd2020000 0x0 0x10000>,
<0x8 0xd2030000 0x0 0x10000>,
<0x8 0xd2040000 0x0 0x10000>,
<0x8 0xd2050000 0x0 0x10000>,
<0x8 0xd2060000 0x0 0x10000>,
<0x8 0xd2070000 0x0 0x10000>,
<0x8 0xd2080000 0x0 0x10000>,
<0x8 0xd2090000 0x0 0x10000>,
<0x8 0xd20a0000 0x0 0x10000>,
<0x8 0xd20b0000 0x0 0x10000>,
<0x8 0xd20c0000 0x0 0x10000>,
<0x8 0xd20d0000 0x0 0x10000>,
<0x8 0xd20e0000 0x0 0x10000>,
<0x8 0xd20f0000 0x0 0x10000>,
<0x8 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p0_mbigen_sec_b>;
iommus = <&p0_smmu_alg_b 0x600>;
dma-coherent;
interrupts = <576 4>,
<577 1>, <578 4>,
<579 1>, <580 4>,
<581 1>, <582 4>,
<583 1>, <584 4>,
<585 1>, <586 4>,
<587 1>, <588 4>,
<589 1>, <590 4>,
<591 1>, <592 4>,
<593 1>, <594 4>,
<595 1>, <596 4>,
<597 1>, <598 4>,
<599 1>, <600 4>,
<601 1>, <602 4>,
<603 1>, <604 4>,
<605 1>, <606 4>,
<607 1>, <608 4>;
};
p1_sec_a: crypto@400d0000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x400 0xd0000000 0x0 0x10000>,
<0x400 0xd2000000 0x0 0x10000>,
<0x400 0xd2010000 0x0 0x10000>,
<0x400 0xd2020000 0x0 0x10000>,
<0x400 0xd2030000 0x0 0x10000>,
<0x400 0xd2040000 0x0 0x10000>,
<0x400 0xd2050000 0x0 0x10000>,
<0x400 0xd2060000 0x0 0x10000>,
<0x400 0xd2070000 0x0 0x10000>,
<0x400 0xd2080000 0x0 0x10000>,
<0x400 0xd2090000 0x0 0x10000>,
<0x400 0xd20a0000 0x0 0x10000>,
<0x400 0xd20b0000 0x0 0x10000>,
<0x400 0xd20c0000 0x0 0x10000>,
<0x400 0xd20d0000 0x0 0x10000>,
<0x400 0xd20e0000 0x0 0x10000>,
<0x400 0xd20f0000 0x0 0x10000>,
<0x400 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p1_mbigen_sec_a>;
iommus = <&p1_smmu_alg_a 0x600>;
dma-coherent;
interrupts = <576 4>,
<577 1>, <578 4>,
<579 1>, <580 4>,
<581 1>, <582 4>,
<583 1>, <584 4>,
<585 1>, <586 4>,
<587 1>, <588 4>,
<589 1>, <590 4>,
<591 1>, <592 4>,
<593 1>, <594 4>,
<595 1>, <596 4>,
<597 1>, <598 4>,
<599 1>, <600 4>,
<601 1>, <602 4>,
<603 1>, <604 4>,
<605 1>, <606 4>,
<607 1>, <608 4>;
};
p1_sec_b: crypto@408d0000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x408 0xd0000000 0x0 0x10000>,
<0x408 0xd2000000 0x0 0x10000>,
<0x408 0xd2010000 0x0 0x10000>,
<0x408 0xd2020000 0x0 0x10000>,
<0x408 0xd2030000 0x0 0x10000>,
<0x408 0xd2040000 0x0 0x10000>,
<0x408 0xd2050000 0x0 0x10000>,
<0x408 0xd2060000 0x0 0x10000>,
<0x408 0xd2070000 0x0 0x10000>,
<0x408 0xd2080000 0x0 0x10000>,
<0x408 0xd2090000 0x0 0x10000>,
<0x408 0xd20a0000 0x0 0x10000>,
<0x408 0xd20b0000 0x0 0x10000>,
<0x408 0xd20c0000 0x0 0x10000>,
<0x408 0xd20d0000 0x0 0x10000>,
<0x408 0xd20e0000 0x0 0x10000>,
<0x408 0xd20f0000 0x0 0x10000>,
<0x408 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p1_mbigen_sec_b>;
iommus = <&p1_smmu_alg_b 0x600>;
dma-coherent;
interrupts = <576 4>,
<577 1>, <578 4>,
<579 1>, <580 4>,
<581 1>, <582 4>,
<583 1>, <584 4>,
<585 1>, <586 4>,
<587 1>, <588 4>,
<589 1>, <590 4>,
<591 1>, <592 4>,
<593 1>, <594 4>,
<595 1>, <596 4>,
<597 1>, <598 4>,
<599 1>, <600 4>,
<601 1>, <602 4>,
<603 1>, <604 4>,
<605 1>, <606 4>,
<607 1>, <608 4>;
};
};
};
arch/arm64/crypto/aes-neonbs-glue.c
+1 -1
View File
@@ -247,7 +247,7 @@ static int aesbs_xts_setkey(struct crypto_skcipher *tfm, const u8 *in_key,
unsigned int key_len)
{
struct aesbs_xts_ctx *ctx = crypto_skcipher_ctx(tfm);
struct crypto_aes_ctx rk;
struct crypto_aes_ctx rk __cleanup(aes_zeroize_ctx);
int err;
err = xts_verify_key(tfm, in_key, key_len);
arch/powerpc/crypto/vmx.c
+3 -11
View File
@@ -8,12 +8,7 @@
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/types.h>
#include <linux/err.h>
#include <linux/cpufeature.h>
#include <linux/crypto.h>
#include <asm/cputable.h>
#include <crypto/internal/skcipher.h>
#include "aesp8-ppc.h"
@@ -24,7 +19,7 @@ static int __init p8_init(void)
ret = crypto_register_skcipher(&p8_aes_cbc_alg);
if (ret)
goto err;
return ret;
ret = crypto_register_skcipher(&p8_aes_ctr_alg);
if (ret)
@@ -40,7 +35,6 @@ err_unregister_aes_ctr:
crypto_unregister_skcipher(&p8_aes_ctr_alg);
err_unregister_aes_cbc:
crypto_unregister_skcipher(&p8_aes_cbc_alg);
err:
return ret;
}
@@ -54,8 +48,6 @@ static void __exit p8_exit(void)
module_cpu_feature_match(PPC_MODULE_FEATURE_VEC_CRYPTO, p8_init);
module_exit(p8_exit);
MODULE_AUTHOR("Marcelo Cerri<mhcerri@br.ibm.com>");
MODULE_DESCRIPTION("IBM VMX cryptographic acceleration instructions "
"support on Power 8");
MODULE_AUTHOR("Marcelo Cerri <mhcerri@br.ibm.com>");
MODULE_DESCRIPTION("IBM VMX cryptographic acceleration instructions support on Power 8");
MODULE_LICENSE("GPL");
MODULE_VERSION("1.0.0");
crypto/algapi.c
+22 -1
View File
@@ -424,7 +424,6 @@ static void crypto_free_alg(struct crypto_alg *alg)
unsigned int algsize = alg->cra_type->algsize;
u8 *p = (u8 *)alg - algsize;
crypto_destroy_alg(alg);
kfree(p);
}
@@ -494,9 +493,31 @@ void crypto_unregister_alg(struct crypto_alg *alg)
LIST_HEAD(list);
down_write(&crypto_alg_sem);
if (alg->cra_flags & CRYPTO_ALG_DUP_FIRST) {
struct crypto_alg *q, *r = NULL;
list_for_each_entry(q, &crypto_alg_list, cra_list) {
if (crypto_is_larval(q))
continue;
if (strcmp(q->cra_driver_name, alg->cra_driver_name))
continue;
r = q;
break;
}
if (!r) {
up_write(&crypto_alg_sem);
ret = -ENOENT;
goto not_found;
}
alg = r;
}
ret = crypto_remove_alg(alg, &list);
up_write(&crypto_alg_sem);
not_found:
if (WARN(ret, "Algorithm %s is not registered", alg->cra_driver_name))
return;
crypto/algif_hash.c
+1 -1
View File
@@ -23,7 +23,7 @@ static const struct af_alg_allowlist_entry hash_allowlist[] = {
{ "hmac(sha224)" }, /* iwd */
{ "hmac(sha256)" }, /* iwd */
{ "hmac(sha384)" }, /* iwd */
{ "hmac(sha512)" }, /* iwd, sha512hmac */
{ "hmac(sha512)", AF_ALG_UNPRIVILEGED }, /* iwd, sha512hmac */
{ "md4" }, /* iwd */
{ "md5" }, /* iwd */
{ "sha1", AF_ALG_UNPRIVILEGED }, /* iwd, iproute2 < 7.0 */
crypto/algif_skcipher.c
+6 -2
View File
@@ -135,12 +135,16 @@ static int _skcipher_recvmsg(struct socket *sock, struct msghdr *msg,
* full block size buffers.
*/
if (ctx->more || len < ctx->used) {
if (len < bs) {
size_t excess = len % bs;
len -= excess;
iov_iter_revert(&msg->msg_iter, excess);
if (!len) {
err = -EINVAL;
goto free;
}
len -= len % bs;
cflags |= CRYPTO_SKCIPHER_REQ_NOTFINAL;
}
crypto/asymmetric_keys/Kconfig
+12
View File
@@ -114,4 +114,16 @@ config FIPS_SIGNATURE_SELFTEST_ECDSA
depends on CRYPTO_SHA256=y || CRYPTO_SHA256=FIPS_SIGNATURE_SELFTEST
depends on CRYPTO_ECDSA=y || CRYPTO_ECDSA=FIPS_SIGNATURE_SELFTEST
config VERIFY_PEFILE_KUNIT_TEST
bool "KUnit tests for signed PE file parsing" if !KUNIT_ALL_TESTS
depends on KUNIT=y && SIGNED_PE_FILE_VERIFICATION
default KUNIT_ALL_TESTS
help
Enable KUnit tests for the PE binary parser used by signed PE file
signature verification. The tests build small malformed PE images in
memory and check that pefile_parse_binary() rejects them instead of
reading out of bounds.
If unsure, say N.
endif # ASYMMETRIC_KEY_TYPE
crypto/asymmetric_keys/Makefile
+2
View File
@@ -79,3 +79,5 @@ verify_signed_pefile-y := \
$(obj)/mscode_parser.o: $(obj)/mscode.asn1.h $(obj)/mscode.asn1.h
$(obj)/mscode.asn1.o: $(obj)/mscode.asn1.c $(obj)/mscode.asn1.h
obj-$(CONFIG_VERIFY_PEFILE_KUNIT_TEST) += verify_pefile_test.o
crypto/asymmetric_keys/pkcs7_parser.c
+6
View File
@@ -111,6 +111,12 @@ static int pkcs7_check_authattrs(struct pkcs7_message *msg)
if (!!sinfo->authattrs != want)
goto inconsistent;
#ifdef CONFIG_PKCS7_WAIVE_AUTHATTRS_REJECTION_FOR_MLDSA
if (sinfo->authattrs &&
strncmp(sinfo->sig->pkey_algo, "mldsa", 5) != 0)
msg->authattrs_rej_waivable = false;
#endif
if (!sinfo->authattrs &&
sinfo->sig->algo_takes_data)
sinfo->sig->hash_algo = "none";
crypto/asymmetric_keys/restrict.c
+6 -2
View File
@@ -243,10 +243,14 @@ static int key_or_keyring_common(struct key *dest_keyring,
if (IS_ERR(key))
key = NULL;
} else if (trusted->type == &key_type_asymmetric) {
const struct asymmetric_key_ids *kids;
const struct asymmetric_key_id **signer_ids;
signer_ids = (const struct asymmetric_key_id **)
asymmetric_key_ids(trusted)->id;
kids = asymmetric_key_ids(trusted);
if (!kids)
return -ENOKEY;
signer_ids = (const struct asymmetric_key_id **)kids->id;
/*
* The auth_ids come from the candidate key (the
crypto/asymmetric_keys/verify_pefile.c
+5
View File
@@ -87,6 +87,11 @@ static int pefile_parse_binary(const void *pebuf, unsigned int pelen,
if (ctx->n_data_dirents > (ctx->header_size - cursor) / sizeof(*dde))
return -ELIBBAD;
/* the certificate table entry must be present in the data directory */
if (ctx->n_data_dirents <=
offsetof(struct data_directory, certs) / sizeof(*dde))
return -ELIBBAD;
ddir = pebuf + cursor;
cursor += sizeof(*dde) * ctx->n_data_dirents;
crypto/asymmetric_keys/verify_pefile_test.c
+100
View File
@@ -0,0 +1,100 @@
// SPDX-License-Identifier: GPL-2.0
/*
* KUnit tests for the signed PE binary parser in verify_pefile.c.
*
* The cases build small malformed PE images in memory and call
* verify_pefile_signature(), which parses the image before any signature
* check, so the parser is exercised without a keyring or a real signature.
*/
#include <kunit/test.h>
#include <linux/slab.h>
#include <linux/pe.h>
#include <linux/verification.h>
/*
* Build a minimal PE32 image whose optional header declares @data_dirs data
* directory entries. header_size is sized to hold them and the image is a few
* bytes larger. With @data_dirs < 5 the certificate table entry (fixed index
* 4) lies outside the declared directory.
*/
static void *build_pe32(u16 data_dirs, unsigned int *out_len)
{
size_t cursor = sizeof(struct mz_hdr) + sizeof(struct pe_hdr) +
sizeof(struct pe32_opt_hdr);
size_t header_size = cursor + ((size_t)data_dirs + 1) *
sizeof(struct data_dirent);
size_t pelen = header_size + 8;
struct mz_hdr *mz;
struct pe_hdr *pe;
struct pe32_opt_hdr *opt;
void *buf = kzalloc(pelen, GFP_KERNEL);
if (!buf)
return NULL;
mz = buf;
mz->magic = IMAGE_DOS_SIGNATURE;
mz->peaddr = sizeof(struct mz_hdr);
pe = buf + sizeof(struct mz_hdr);
pe->magic = IMAGE_NT_SIGNATURE;
opt = buf + sizeof(struct mz_hdr) + sizeof(struct pe_hdr);
opt->magic = IMAGE_NT_OPTIONAL_HDR32_MAGIC;
opt->header_size = header_size;
opt->data_dirs = data_dirs;
*out_len = pelen;
return buf;
}
/*
* data_dirs = 0: the certificate table entry (index 4) is absent, so the
* parser must reject the image instead of reading ddir->certs past the end.
*/
static void pefile_missing_certs_dirent(struct kunit *test)
{
unsigned int len;
void *buf = build_pe32(0, &len);
int ret;
KUNIT_ASSERT_NOT_NULL(test, buf);
ret = verify_pefile_signature(buf, len, NULL,
VERIFYING_KEXEC_PE_SIGNATURE);
KUNIT_EXPECT_EQ(test, ret, -ELIBBAD);
kfree(buf);
}
/*
* data_dirs = 5: the certificate table entry is present (and zero, i.e.
* unsigned), so the parser gets past the directory bound and rejects the image
* as unsigned (-ENODATA) rather than -ELIBBAD.
*/
static void pefile_present_certs_dirent(struct kunit *test)
{
unsigned int len;
void *buf = build_pe32(5, &len);
int ret;
KUNIT_ASSERT_NOT_NULL(test, buf);
ret = verify_pefile_signature(buf, len, NULL,
VERIFYING_KEXEC_PE_SIGNATURE);
KUNIT_EXPECT_EQ(test, ret, -ENODATA);
kfree(buf);
}
static struct kunit_case verify_pefile_cases[] = {
KUNIT_CASE(pefile_missing_certs_dirent),
KUNIT_CASE(pefile_present_certs_dirent),
{}
};
static struct kunit_suite verify_pefile_suite = {
.name = "verify_pefile",
.test_cases = verify_pefile_cases,
};
kunit_test_suite(verify_pefile_suite);
MODULE_LICENSE("GPL");
MODULE_DESCRIPTION("KUnit tests for the signed PE binary parser");
crypto/asymmetric_keys/x509_public_key.c
+4 -2
View File
@@ -53,9 +53,11 @@ int x509_get_sig_params(struct x509_certificate *cert)
if (sig->algo_takes_data) {
/* The signature algorithm does whatever passes for hashing. */
sig->m = (u8 *)cert->tbs;
sig->m = kmemdup(cert->tbs, cert->tbs_size, GFP_KERNEL);
if (!sig->m)
return -ENOMEM;
sig->m_size = cert->tbs_size;
sig->m_free = false;
sig->m_free = true;
goto out;
}
crypto/cast5_generic.c
+1 -3
View File
@@ -483,9 +483,7 @@ int cast5_setkey(struct crypto_tfm *tfm, const u8 *key, unsigned int key_len)
c->rr = key_len <= 10 ? 1 : 0;
memset(p_key, 0, 16);
memcpy(p_key, key, key_len);
memcpy_and_pad(p_key, sizeof(p_key), key, key_len, 0);
x[0] = be32_to_cpu(p_key[0]);
x[1] = be32_to_cpu(p_key[1]);
crypto/cast6_generic.c
+1 -2
View File
@@ -112,8 +112,7 @@ int __cast6_setkey(struct cast6_ctx *c, const u8 *in_key, unsigned int key_len)
if (key_len % 4 != 0)
return -EINVAL;
memset(p_key, 0, 32);
memcpy(p_key, in_key, key_len);
memcpy_and_pad(p_key, sizeof(p_key), in_key, key_len, 0);
key[0] = be32_to_cpu(p_key[0]); /* A */
key[1] = be32_to_cpu(p_key[1]); /* B */
crypto/ecc.c
+31 -2
View File
@@ -1423,9 +1423,22 @@ static void ecc_point_add(const struct ecc_point *result,
vli_set(result->x, q->x, ndigits);
vli_set(result->y, q->y, ndigits);
vli_mod_sub(z, result->x, p->x, curve->p, ndigits);
if (vli_is_zero(z, ndigits)) {
if (vli_cmp(p->y, q->y, ndigits)) {
/* P + (-P) is the point at infinity. */
vli_clear(result->x, ndigits);
vli_clear(result->y, ndigits);
return;
}
/* The co-Z addition formula does not handle P == Q. */
z[0] = 1;
ecc_point_double_jacobian(result->x, result->y, z, curve);
goto out;
}
vli_set(px, p->x, ndigits);
vli_set(py, p->y, ndigits);
xycz_add(px, py, result->x, result->y, curve);
out:
vli_mod_inv(z, z, curve->p, ndigits);
apply_z(result->x, result->y, z, curve);
}
@@ -1465,22 +1478,38 @@ void ecc_point_mult_shamir(const struct ecc_point *result,
vli_set(rx, point->x, ndigits);
vli_set(ry, point->y, ndigits);
vli_clear(z + 1, ndigits - 1);
z[0] = 1;
z[0] = !ecc_point_is_zero(point);
for (--i; i >= 0; i--) {
ecc_point_double_jacobian(rx, ry, z, curve);
idx = !!vli_test_bit(u1, i);
idx |= (!!vli_test_bit(u2, i)) << 1;
point = points[idx];
if (point) {
if (point && !ecc_point_is_zero(point)) {
u64 tx[ECC_MAX_DIGITS];
u64 ty[ECC_MAX_DIGITS];
u64 tz[ECC_MAX_DIGITS];
if (vli_is_zero(z, ndigits)) {
/* Adding to infinity starts a new accumulator. */
vli_set(rx, point->x, ndigits);
vli_set(ry, point->y, ndigits);
z[0] = 1;
continue;
}
vli_set(tx, point->x, ndigits);
vli_set(ty, point->y, ndigits);
apply_z(tx, ty, z, curve);
vli_mod_sub(tz, rx, tx, curve->p, ndigits);
if (vli_is_zero(tz, ndigits)) {
if (!vli_cmp(ry, ty, ndigits))
ecc_point_double_jacobian(rx, ry, z,
curve);
else
/* Adding opposite points yields infinity. */
vli_clear(z, ndigits);
continue;
}
xycz_add(tx, ty, rx, ry, curve);
vli_mod_mult_fast(z, z, tz, curve);
}
crypto/lskcipher.c
+5 -1
View File
@@ -75,6 +75,7 @@ static int crypto_lskcipher_crypt_unaligned(
unsigned ivsize = crypto_lskcipher_ivsize(tfm);
unsigned bs = crypto_lskcipher_blocksize(tfm);
unsigned cs = crypto_lskcipher_chunksize(tfm);
u32 flags = 0;
int err;
u8 *tiv;
u8 *p;
@@ -98,13 +99,16 @@ static int crypto_lskcipher_crypt_unaligned(
if (chunk > cs)
chunk &= ~(cs - 1);
if (chunk == len)
flags |= CRYPTO_LSKCIPHER_FLAG_FINAL;
memcpy(p, src, chunk);
err = crypt(tfm, p, p, chunk, tiv, CRYPTO_LSKCIPHER_FLAG_FINAL);
err = crypt(tfm, p, p, chunk, tiv, flags);
if (err)
goto out;
memcpy(dst, p, chunk);
flags |= CRYPTO_LSKCIPHER_FLAG_CONT;
src += chunk;
dst += chunk;
len -= chunk;
crypto/rsassa-pkcs1.c
+2 -2
View File
@@ -169,7 +169,7 @@ static int rsassa_pkcs1_sign(struct crypto_sig *tfm,
u8 *in_buf;
int err;
if (!ctx->key_size)
if (ctx->key_size < 11)
return -EINVAL;
if (dlen < ctx->key_size)
@@ -231,7 +231,7 @@ static int rsassa_pkcs1_verify(struct crypto_sig *tfm,
int err;
/* RFC 8017 sec 8.2.2 step 1 - length checking */
if (!ctx->key_size ||
if (ctx->key_size < 11 ||
slen != ctx->key_size ||
rsassa_pkcs1_invalid_hash_len(dlen, hash_prefix))
return -EINVAL;
crypto/tcrypt.c
+101 -81
View File
@@ -56,6 +56,21 @@
*/
#define get_driver_name(tfm_type, tfm) crypto_tfm_alg_driver_name(tfm_type ## _tfm(tfm))
struct tcrypt_aead_request {
struct aead_request *req;
struct crypto_wait wait;
};
struct tcrypt_ahash_request {
struct ahash_request *req;
struct crypto_wait wait;
};
struct tcrypt_skcipher_request {
struct skcipher_request *req;
struct crypto_wait wait;
};
/*
* Used by test_cipher_speed()
*/
@@ -129,18 +144,15 @@ static void sg_init_aead(struct scatterlist *sg, char *xbuf[XBUFSIZE],
sg_set_buf(&sg[k + 1], xbuf[k], rem);
}
static inline int do_one_aead_op(struct aead_request *req, int ret)
static inline int do_one_aead_op(struct tcrypt_aead_request *req, int ret)
{
struct crypto_wait *wait = req->base.data;
return crypto_wait_req(ret, wait);
return crypto_wait_req(ret, &req->wait);
}
struct test_mb_aead_data {
struct scatterlist sg[XBUFSIZE];
struct scatterlist sgout[XBUFSIZE];
struct aead_request *req;
struct crypto_wait wait;
struct tcrypt_aead_request req;
char *xbuf[XBUFSIZE];
char *xoutbuf[XBUFSIZE];
char *axbuf[XBUFSIZE];
@@ -154,14 +166,14 @@ static int do_mult_aead_op(struct test_mb_aead_data *data, int enc,
/* Fire up a bunch of concurrent requests */
for (i = 0; i < num_mb; i++) {
if (enc == ENCRYPT)
rc[i] = crypto_aead_encrypt(data[i].req);
rc[i] = crypto_aead_encrypt(data[i].req.req);
else
rc[i] = crypto_aead_decrypt(data[i].req);
rc[i] = crypto_aead_decrypt(data[i].req.req);
}
/* Wait for all requests to finish */
for (i = 0; i < num_mb; i++) {
rc[i] = crypto_wait_req(rc[i], &data[i].wait);
rc[i] = crypto_wait_req(rc[i], &data[i].req.wait);
if (rc[i]) {
pr_info("concurrent request %d error %d\n", i, rc[i]);
@@ -310,21 +322,21 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs,
}
for (i = 0; i < num_mb; ++i) {
data[i].req = aead_request_alloc(tfm, GFP_KERNEL);
if (!data[i].req) {
data[i].req.req = aead_request_alloc(tfm, GFP_KERNEL);
if (!data[i].req.req) {
pr_err("alg: aead: Failed to allocate request for %s\n",
algo);
while (i--)
aead_request_free(data[i].req);
aead_request_free(data[i].req.req);
goto out_free_xoutbuf;
}
}
for (i = 0; i < num_mb; ++i) {
crypto_init_wait(&data[i].wait);
aead_request_set_callback(data[i].req,
crypto_init_wait(&data[i].req.wait);
aead_request_set_callback(data[i].req.req,
CRYPTO_TFM_REQ_MAY_BACKLOG,
crypto_req_done, &data[i].wait);
crypto_req_done, &data[i].req.wait);
}
pr_info("testing speed of multibuffer %s (%s) %s\n", algo,
@@ -386,16 +398,16 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs,
bs + (enc ? authsize : 0),
assoc, aad_size);
aead_request_set_ad(cur->req, aad_size);
aead_request_set_ad(cur->req.req, aad_size);
if (!enc) {
aead_request_set_crypt(cur->req,
aead_request_set_crypt(cur->req.req,
cur->sgout,
cur->sg,
bs, iv);
ret = crypto_aead_encrypt(cur->req);
ret = do_one_aead_op(cur->req, ret);
ret = crypto_aead_encrypt(cur->req.req);
ret = do_one_aead_op(&cur->req, ret);
if (ret) {
pr_err("calculating auth failed (%d)\n",
@@ -404,7 +416,7 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs,
}
}
aead_request_set_crypt(cur->req, cur->sg,
aead_request_set_crypt(cur->req.req, cur->sg,
cur->sgout, bs +
(enc ? 0 : authsize),
iv);
@@ -432,7 +444,7 @@ static void test_mb_aead_speed(const char *algo, int enc, int secs,
out:
for (i = 0; i < num_mb; ++i)
aead_request_free(data[i].req);
aead_request_free(data[i].req.req);
out_free_xoutbuf:
for (i = 0; i < num_mb; ++i)
testmgr_free_buf(data[i].xoutbuf);
@@ -450,9 +462,10 @@ out_free_iv:
kfree(iv);
}
static int test_aead_jiffies(struct aead_request *req, int enc,
static int test_aead_jiffies(struct tcrypt_aead_request *treq, int enc,
int blen, int secs)
{
struct aead_request *req = treq->req;
unsigned long start, end;
int bcount;
int ret;
@@ -460,9 +473,9 @@ static int test_aead_jiffies(struct aead_request *req, int enc,
for (start = jiffies, end = start + secs * HZ, bcount = 0;
time_before(jiffies, end); bcount++) {
if (enc)
ret = do_one_aead_op(req, crypto_aead_encrypt(req));
ret = do_one_aead_op(treq, crypto_aead_encrypt(req));
else
ret = do_one_aead_op(req, crypto_aead_decrypt(req));
ret = do_one_aead_op(treq, crypto_aead_decrypt(req));
if (ret)
return ret;
@@ -473,8 +486,9 @@ static int test_aead_jiffies(struct aead_request *req, int enc,
return 0;
}
static int test_aead_cycles(struct aead_request *req, int enc, int blen)
static int test_aead_cycles(struct tcrypt_aead_request *treq, int enc, int blen)
{
struct aead_request *req = treq->req;
unsigned long cycles = 0;
int ret = 0;
int i;
@@ -482,9 +496,9 @@ static int test_aead_cycles(struct aead_request *req, int enc, int blen)
/* Warm-up run. */
for (i = 0; i < 4; i++) {
if (enc)
ret = do_one_aead_op(req, crypto_aead_encrypt(req));
ret = do_one_aead_op(treq, crypto_aead_encrypt(req));
else
ret = do_one_aead_op(req, crypto_aead_decrypt(req));
ret = do_one_aead_op(treq, crypto_aead_decrypt(req));
if (ret)
goto out;
@@ -496,9 +510,9 @@ static int test_aead_cycles(struct aead_request *req, int enc, int blen)
start = get_cycles();
if (enc)
ret = do_one_aead_op(req, crypto_aead_encrypt(req));
ret = do_one_aead_op(treq, crypto_aead_encrypt(req));
else
ret = do_one_aead_op(req, crypto_aead_decrypt(req));
ret = do_one_aead_op(treq, crypto_aead_decrypt(req));
end = get_cycles();
if (ret)
@@ -520,6 +534,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
unsigned int tcount, u8 authsize,
unsigned int aad_size, u8 *keysize)
{
struct tcrypt_aead_request treq;
unsigned int i, j;
struct crypto_aead *tfm;
int ret = -ENOMEM;
@@ -535,7 +550,6 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
char *axbuf[XBUFSIZE];
const int *b_size;
unsigned int iv_len;
struct crypto_wait wait;
iv = kzalloc(MAX_IVLEN, GFP_KERNEL);
if (!iv)
@@ -577,7 +591,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
goto out_noreq;
}
crypto_init_wait(&wait);
crypto_init_wait(&treq.wait);
pr_info("testing speed of %s (%s) %s\n", algo,
get_driver_name(crypto_aead, tfm), e);
@@ -587,9 +601,10 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
algo);
goto out_noreq;
}
treq.req = req;
aead_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
crypto_req_done, &wait);
crypto_req_done, &treq.wait);
i = 0;
do {
@@ -650,7 +665,7 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
*/
aead_request_set_crypt(req, sgout, sg,
bs, iv);
ret = do_one_aead_op(req,
ret = do_one_aead_op(&treq,
crypto_aead_encrypt(req));
if (ret) {
@@ -665,11 +680,11 @@ static void test_aead_speed(const char *algo, int enc, unsigned int secs,
iv);
if (secs) {
ret = test_aead_jiffies(req, enc, bs,
ret = test_aead_jiffies(&treq, enc, bs,
secs);
cond_resched();
} else {
ret = test_aead_cycles(req, enc, bs);
ret = test_aead_cycles(&treq, enc, bs);
}
if (ret) {
@@ -709,23 +724,22 @@ static void test_hash_sg_init(struct scatterlist *sg)
}
}
static inline int do_one_ahash_op(struct ahash_request *req, int ret)
static inline int do_one_ahash_op(struct tcrypt_ahash_request *treq, int ret)
{
struct crypto_wait *wait = req->base.data;
return crypto_wait_req(ret, wait);
return crypto_wait_req(ret, &treq->wait);
}
static int test_ahash_jiffies_digest(struct ahash_request *req, int blen,
char *out, int secs)
static int test_ahash_jiffies_digest(struct tcrypt_ahash_request *treq,
int blen, char *out, int secs)
{
struct ahash_request *req = treq->req;
unsigned long start, end;
int bcount;
int ret;
for (start = jiffies, end = start + secs * HZ, bcount = 0;
time_before(jiffies, end); bcount++) {
ret = do_one_ahash_op(req, crypto_ahash_digest(req));
ret = do_one_ahash_op(treq, crypto_ahash_digest(req));
if (ret)
return ret;
}
@@ -736,28 +750,29 @@ static int test_ahash_jiffies_digest(struct ahash_request *req, int blen,
return 0;
}
static int test_ahash_jiffies(struct ahash_request *req, int blen,
static int test_ahash_jiffies(struct tcrypt_ahash_request *treq, int blen,
int plen, char *out, int secs)
{
struct ahash_request *req = treq->req;
unsigned long start, end;
int bcount, pcount;
int ret;
if (plen == blen)
return test_ahash_jiffies_digest(req, blen, out, secs);
return test_ahash_jiffies_digest(treq, blen, out, secs);
for (start = jiffies, end = start + secs * HZ, bcount = 0;
time_before(jiffies, end); bcount++) {
ret = do_one_ahash_op(req, crypto_ahash_init(req));
ret = do_one_ahash_op(treq, crypto_ahash_init(req));
if (ret)
return ret;
for (pcount = 0; pcount < blen; pcount += plen) {
ret = do_one_ahash_op(req, crypto_ahash_update(req));
ret = do_one_ahash_op(treq, crypto_ahash_update(req));
if (ret)
return ret;
}
/* we assume there is enough space in 'out' for the result */
ret = do_one_ahash_op(req, crypto_ahash_final(req));
ret = do_one_ahash_op(treq, crypto_ahash_final(req));
if (ret)
return ret;
}
@@ -768,15 +783,16 @@ static int test_ahash_jiffies(struct ahash_request *req, int blen,
return 0;
}
static int test_ahash_cycles_digest(struct ahash_request *req, int blen,
char *out)
static int test_ahash_cycles_digest(struct tcrypt_ahash_request *treq,
int blen, char *out)
{
struct ahash_request *req = treq->req;
unsigned long cycles = 0;
int ret, i;
/* Warm-up run. */
for (i = 0; i < 4; i++) {
ret = do_one_ahash_op(req, crypto_ahash_digest(req));
ret = do_one_ahash_op(treq, crypto_ahash_digest(req));
if (ret)
goto out;
}
@@ -787,7 +803,7 @@ static int test_ahash_cycles_digest(struct ahash_request *req, int blen,
start = get_cycles();
ret = do_one_ahash_op(req, crypto_ahash_digest(req));
ret = do_one_ahash_op(treq, crypto_ahash_digest(req));
if (ret)
goto out;
@@ -806,26 +822,27 @@ out:
return 0;
}
static int test_ahash_cycles(struct ahash_request *req, int blen,
static int test_ahash_cycles(struct tcrypt_ahash_request *treq, int blen,
int plen, char *out)
{
struct ahash_request *req = treq->req;
unsigned long cycles = 0;
int i, pcount, ret;
if (plen == blen)
return test_ahash_cycles_digest(req, blen, out);
return test_ahash_cycles_digest(treq, blen, out);
/* Warm-up run. */
for (i = 0; i < 4; i++) {
ret = do_one_ahash_op(req, crypto_ahash_init(req));
ret = do_one_ahash_op(treq, crypto_ahash_init(req));
if (ret)
goto out;
for (pcount = 0; pcount < blen; pcount += plen) {
ret = do_one_ahash_op(req, crypto_ahash_update(req));
ret = do_one_ahash_op(treq, crypto_ahash_update(req));
if (ret)
goto out;
}
ret = do_one_ahash_op(req, crypto_ahash_final(req));
ret = do_one_ahash_op(treq, crypto_ahash_final(req));
if (ret)
goto out;
}
@@ -836,15 +853,15 @@ static int test_ahash_cycles(struct ahash_request *req, int blen,
start = get_cycles();
ret = do_one_ahash_op(req, crypto_ahash_init(req));
ret = do_one_ahash_op(treq, crypto_ahash_init(req));
if (ret)
goto out;
for (pcount = 0; pcount < blen; pcount += plen) {
ret = do_one_ahash_op(req, crypto_ahash_update(req));
ret = do_one_ahash_op(treq, crypto_ahash_update(req));
if (ret)
goto out;
}
ret = do_one_ahash_op(req, crypto_ahash_final(req));
ret = do_one_ahash_op(treq, crypto_ahash_final(req));
if (ret)
goto out;
@@ -867,7 +884,7 @@ static void test_ahash_speed_common(const char *algo, unsigned int secs,
struct hash_speed *speed, unsigned mask)
{
struct scatterlist sg[TVMEMSIZE];
struct crypto_wait wait;
struct tcrypt_ahash_request treq;
struct ahash_request *req;
struct crypto_ahash *tfm;
char *output;
@@ -896,9 +913,10 @@ static void test_ahash_speed_common(const char *algo, unsigned int secs,
goto out;
}
crypto_init_wait(&wait);
treq.req = req;
crypto_init_wait(&treq.wait);
ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
crypto_req_done, &wait);
crypto_req_done, &treq.wait);
output = kmalloc(MAX_DIGEST_SIZE, GFP_KERNEL);
if (!output)
@@ -927,11 +945,11 @@ static void test_ahash_speed_common(const char *algo, unsigned int secs,
ahash_request_set_crypt(req, sg, output, speed[i].plen);
if (secs) {
ret = test_ahash_jiffies(req, speed[i].blen,
ret = test_ahash_jiffies(&treq, speed[i].blen,
speed[i].plen, output, secs);
cond_resched();
} else {
ret = test_ahash_cycles(req, speed[i].blen,
ret = test_ahash_cycles(&treq, speed[i].blen,
speed[i].plen, output);
}
@@ -1217,16 +1235,16 @@ out_free_data:
kfree(data);
}
static inline int do_one_acipher_op(struct skcipher_request *req, int ret)
static inline int do_one_acipher_op(struct tcrypt_skcipher_request *req,
int ret)
{
struct crypto_wait *wait = req->base.data;
return crypto_wait_req(ret, wait);
return crypto_wait_req(ret, &req->wait);
}
static int test_acipher_jiffies(struct skcipher_request *req, int enc,
static int test_acipher_jiffies(struct tcrypt_skcipher_request *treq, int enc,
int blen, int secs)
{
struct skcipher_request *req = treq->req;
unsigned long start, end;
int bcount;
int ret;
@@ -1234,10 +1252,10 @@ static int test_acipher_jiffies(struct skcipher_request *req, int enc,
for (start = jiffies, end = start + secs * HZ, bcount = 0;
time_before(jiffies, end); bcount++) {
if (enc)
ret = do_one_acipher_op(req,
ret = do_one_acipher_op(treq,
crypto_skcipher_encrypt(req));
else
ret = do_one_acipher_op(req,
ret = do_one_acipher_op(treq,
crypto_skcipher_decrypt(req));
if (ret)
@@ -1249,9 +1267,10 @@ static int test_acipher_jiffies(struct skcipher_request *req, int enc,
return 0;
}
static int test_acipher_cycles(struct skcipher_request *req, int enc,
static int test_acipher_cycles(struct tcrypt_skcipher_request *treq, int enc,
int blen)
{
struct skcipher_request *req = treq->req;
unsigned long cycles = 0;
int ret = 0;
int i;
@@ -1259,10 +1278,10 @@ static int test_acipher_cycles(struct skcipher_request *req, int enc,
/* Warm-up run. */
for (i = 0; i < 4; i++) {
if (enc)
ret = do_one_acipher_op(req,
ret = do_one_acipher_op(treq,
crypto_skcipher_encrypt(req));
else
ret = do_one_acipher_op(req,
ret = do_one_acipher_op(treq,
crypto_skcipher_decrypt(req));
if (ret)
@@ -1275,10 +1294,10 @@ static int test_acipher_cycles(struct skcipher_request *req, int enc,
start = get_cycles();
if (enc)
ret = do_one_acipher_op(req,
ret = do_one_acipher_op(treq,
crypto_skcipher_encrypt(req));
else
ret = do_one_acipher_op(req,
ret = do_one_acipher_op(treq,
crypto_skcipher_decrypt(req));
end = get_cycles();
@@ -1300,8 +1319,8 @@ static void test_skcipher_speed(const char *algo, int enc, unsigned int secs,
struct cipher_speed_template *template,
unsigned int tcount, u8 *keysize, bool async)
{
struct tcrypt_skcipher_request treq;
unsigned int ret, i, j, k, iv_len;
struct crypto_wait wait;
const char *key;
char iv[128];
struct skcipher_request *req;
@@ -1314,7 +1333,7 @@ static void test_skcipher_speed(const char *algo, int enc, unsigned int secs,
else
e = "decryption";
crypto_init_wait(&wait);
crypto_init_wait(&treq.wait);
tfm = crypto_alloc_skcipher(algo, 0, async ? 0 : CRYPTO_ALG_ASYNC);
@@ -1333,8 +1352,9 @@ static void test_skcipher_speed(const char *algo, int enc, unsigned int secs,
goto out;
}
treq.req = req;
skcipher_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
crypto_req_done, &wait);
crypto_req_done, &treq.wait);
i = 0;
do {
@@ -1401,11 +1421,11 @@ static void test_skcipher_speed(const char *algo, int enc, unsigned int secs,
skcipher_request_set_crypt(req, sg, sg, bs, iv);
if (secs) {
ret = test_acipher_jiffies(req, enc,
ret = test_acipher_jiffies(&treq, enc,
bs, secs);
cond_resched();
} else {
ret = test_acipher_cycles(req, enc,
ret = test_acipher_cycles(&treq, enc,
bs);
}
crypto/testmgr.c
+6 -5
View File
@@ -3958,16 +3958,17 @@ static int test_sig_one(struct crypto_sig *tfm, const struct sig_testvec *vecs)
*/
err = crypto_sig_verify(tfm, vecs->c, vecs->c_size,
vecs->m, vecs->m_size);
if (err) {
pr_err("alg: sig: verify test failed: err %d\n", err);
return err;
if (err != vecs->verify_error) {
pr_err("alg: sig: verify test failed: expected %d, got %d\n",
vecs->verify_error, err);
return err ?: -EINVAL;
}
/*
* Don't invoke sign test (which requires a private key)
* for vectors with only a public key.
* for vectors with only a public key or an invalid signature.
*/
if (vecs->public_key_vec)
if (vecs->public_key_vec || vecs->verify_error)
return 0;
sig_size = crypto_sig_maxsize(tfm);
crypto/testmgr.h
+326 -1
View File
@@ -161,6 +161,7 @@ struct sig_testvec {
unsigned int param_len;
unsigned int m_size;
unsigned int c_size;
int verify_error;
bool public_key_vec;
enum OID algo;
};
@@ -1443,6 +1444,140 @@ static const struct sig_testvec x962_ecdsa_nist_p192_tv_template[] = {
};
static const struct sig_testvec x962_ecdsa_nist_p256_tv_template[] = {
/* Invalid signature: Q = G, r = s, e = 3r mod n. */
{
.key =
"\x04\x6b\x17\xd1\xf2\xe1\x2c\x42\x47\xf8\xbc\xe6\xe5\x63\xa4\x40"
"\xf2\x77\x03\x7d\x81\x2d\xeb\x33\xa0\xf4\xa1\x39\x45\xd8\x98\xc2"
"\x96\x4f\xe3\x42\xe2\xfe\x1a\x7f\x9b\x8e\xe7\xeb\x4a\x7c\x0f\x9e"
"\x16\x2b\xce\x33\x57\x6b\x31\x5e\xce\xcb\xb6\x40\x68\x37\xbf\x51"
"\xf5",
.key_len = 65,
.m =
"\xb2\xc3\x09\x72\x03\x17\x9d\xaa\x5c\x4a\xd8\xff\x02\xfe\xcb\x15"
"\x21\x53\x81\x77\x45\xec\x45\x24\x3d\x68\x10\xb9\xf2\xa5\x88\x3a",
.m_size = 32,
.c =
"\x30\x46\x02\x21\x00\x90\xeb\xad\xd0\x56\x5d\x34\x8e\x74\x18\xf2"
"\xff\xab\xaa\x43\xb1\x9f\x68\xd4\x0c\x4f\x01\x4b\xe3\x10\x60\x9e"
"\x7e\xfa\x58\x39\xd9\x02\x21\x00\x90\xeb\xad\xd0\x56\x5d\x34\x8e"
"\x74\x18\xf2\xff\xab\xaa\x43\xb1\x9f\x68\xd4\x0c\x4f\x01\x4b\xe3"
"\x10\x60\x9e\x7e\xfa\x58\x39\xd9",
.c_size = 72,
.verify_error = -EKEYREJECTED,
.public_key_vec = true,
},
/* Invalid signature: Q = -G, r = s, e = 3r mod n. */
{
.key =
"\x04\x6b\x17\xd1\xf2\xe1\x2c\x42\x47\xf8\xbc\xe6\xe5\x63\xa4\x40"
"\xf2\x77\x03\x7d\x81\x2d\xeb\x33\xa0\xf4\xa1\x39\x45\xd8\x98\xc2"
"\x96\xb0\x1c\xbd\x1c\x01\xe5\x80\x65\x71\x18\x14\xb5\x83\xf0\x61"
"\xe9\xd4\x31\xcc\xa9\x94\xce\xa1\x31\x34\x49\xbf\x97\xc8\x40\xae"
"\x0a",
.key_len = 65,
.m =
"\xb2\xc3\x09\x72\x03\x17\x9d\xaa\x5c\x4a\xd8\xff\x02\xfe\xcb\x15"
"\x21\x53\x81\x77\x45\xec\x45\x24\x3d\x68\x10\xb9\xf2\xa5\x88\x3a",
.m_size = 32,
.c =
"\x30\x46\x02\x21\x00\x90\xeb\xad\xd0\x56\x5d\x34\x8e\x74\x18\xf2"
"\xff\xab\xaa\x43\xb1\x9f\x68\xd4\x0c\x4f\x01\x4b\xe3\x10\x60\x9e"
"\x7e\xfa\x58\x39\xd9\x02\x21\x00\x90\xeb\xad\xd0\x56\x5d\x34\x8e"
"\x74\x18\xf2\xff\xab\xaa\x43\xb1\x9f\x68\xd4\x0c\x4f\x01\x4b\xe3"
"\x10\x60\x9e\x7e\xfa\x58\x39\xd9",
.c_size = 72,
.verify_error = -EKEYREJECTED,
.public_key_vec = true,
},
/* Wycheproof secp256r1/SHA-256 tcId 60. */
{
.key =
"\x04\x29\x27\xb1\x05\x12\xba\xe3\xed\xdc\xfe\x46\x78\x28\x12\x8b"
"\xad\x29\x03\x26\x99\x19\xf7\x08\x60\x69\xc8\xc4\xdf\x6c\x73\x28"
"\x38\xc7\x78\x79\x64\xea\xac\x00\xe5\x92\x1f\xb1\x49\x8a\x60\xf4"
"\x60\x67\x66\xb3\xd9\x68\x50\x01\x55\x8d\x1a\x97\x4e\x73\x41\x51"
"\x3e",
.key_len = 65,
.m =
"\x70\x23\x9d\xd8\x77\xf7\xc9\x44\xc4\x22\xf4\x4d\xea\x4e\xd1\xa5"
"\x2f\x26\x27\x41\x6f\xaf\x2f\x07\x2f\xa5\x0c\x77\x2e\xd6\xf8\x07",
.m_size = 32,
.c =
"\x30\x44\x02\x20\x64\xa1\xaa\xb5\x00\x0d\x0e\x80\x4f\x3e\x2f\xc0"
"\x2b\xde\xe9\xbe\x8f\xf3\x12\x33\x4e\x2b\xa1\x6d\x11\x54\x7c\x97"
"\x71\x1c\x89\x8e\x02\x20\x6a\xf0\x15\x97\x1c\xc3\x0b\xe6\xd1\xa2"
"\x06\xd4\xe0\x13\xe0\x99\x77\x72\xa2\xf9\x1d\x73\x28\x6f\xfd\x68"
"\x3b\x9b\xb2\xcf\x4f\x1b",
.c_size = 70,
.public_key_vec = true,
},
/* Wycheproof secp256r1/SHA-256 tcId 210. */
{
.key =
"\x04\xc6\xa7\x71\x52\x70\x24\x22\x77\x92\x17\x0a\x6f\x8e\xee\x73"
"\x5b\xf3\x2b\x7f\x98\xaf\x66\x9e\xad\x29\x98\x02\xe3\x2d\x7c\x31"
"\x07\xbc\x3b\x4b\x5e\x65\xab\x88\x7b\xbd\x34\x35\x72\xb3\xe5\x61"
"\x92\x61\xfe\x3a\x07\x3e\x2f\xfd\x78\x41\x2f\x72\x68\x67\xdb\x58"
"\x9e",
.key_len = 65,
.m =
"\xbb\x5a\x52\xf4\x2f\x9c\x92\x61\xed\x43\x61\xf5\x94\x22\xa1\xe3"
"\x00\x36\xe7\xc3\x2b\x27\x0c\x88\x07\xa4\x19\xfe\xca\x60\x50\x23",
.m_size = 32,
.c =
"\x30\x45\x02\x20\x7c\xf2\x7b\x18\x8d\x03\x4f\x7e\x8a\x52\x38\x03"
"\x04\xb5\x1a\xc3\xc0\x89\x69\xe2\x77\xf2\x1b\x35\xa6\x0b\x48\xfc"
"\x47\x66\x99\x78\x02\x21\x00\xb6\xdb\x6d\xb6\x24\x92\x49\x25\x49"
"\x24\x92\x49\x24\x92\x49\x24\x62\x5b\xd7\xa0\x9b\xec\x4c\xa8\x1b"
"\xcd\xd9\xf8\xfd\x6b\x63\xcc",
.c_size = 71,
.public_key_vec = true,
},
/* Q = G, d = 1, k = 2. */
{
.key =
"\x04\x6b\x17\xd1\xf2\xe1\x2c\x42\x47\xf8\xbc\xe6\xe5\x63\xa4\x40"
"\xf2\x77\x03\x7d\x81\x2d\xeb\x33\xa0\xf4\xa1\x39\x45\xd8\x98\xc2"
"\x96\x4f\xe3\x42\xe2\xfe\x1a\x7f\x9b\x8e\xe7\xeb\x4a\x7c\x0f\x9e"
"\x16\x2b\xce\x33\x57\x6b\x31\x5e\xce\xcb\xb6\x40\x68\x37\xbf\x51"
"\xf5",
.key_len = 65,
.m =
"\x35\x9d\x17\x29\xb9\x1a\x52\xe9\x8b\xb5\x95\xc3\x86\x28\x3c\x10"
"\x30\x44\x95\x1a\xa1\x08\x20\xf0\xa0\x22\xc4\x18\xc2\x71\xa0\xcc",
.m_size = 32,
.c =
"\x30\x44\x02\x20\x7c\xf2\x7b\x18\x8d\x03\x4f\x7e\x8a\x52\x38\x03"
"\x04\xb5\x1a\xc3\xc0\x89\x69\xe2\x77\xf2\x1b\x35\xa6\x0b\x48\xfc"
"\x47\x66\x99\x78\x02\x20\x59\x47\xc9\x21\x23\x0e\xd1\x34\x0b\x03"
"\xe6\xe3\x45\x6e\xab\x69\xf8\x66\xff\x7e\x8c\x7d\x1e\x13\x23\x17"
"\x06\x8a\x84\xec\x1d\x22",
.c_size = 70,
.public_key_vec = true,
},
/* Q = -G, d = n - 1, k = 2. */
{
.key =
"\x04\x6b\x17\xd1\xf2\xe1\x2c\x42\x47\xf8\xbc\xe6\xe5\x63\xa4\x40"
"\xf2\x77\x03\x7d\x81\x2d\xeb\x33\xa0\xf4\xa1\x39\x45\xd8\x98\xc2"
"\x96\xb0\x1c\xbd\x1c\x01\xe5\x80\x65\x71\x18\x14\xb5\x83\xf0\x61"
"\xe9\xd4\x31\xcc\xa9\x94\xce\xa1\x31\x34\x49\xbf\x97\xc8\x40\xae"
"\x0a",
.key_len = 65,
.m =
"\x35\x9d\x17\x29\xb9\x1a\x52\xe9\x8b\xb5\x95\xc3\x86\x28\x3c\x10"
"\x30\x44\x95\x1a\xa1\x08\x20\xf0\xa0\x22\xc4\x18\xc2\x71\xa0\xcc",
.m_size = 32,
.c =
"\x30\x45\x02\x20\x7c\xf2\x7b\x18\x8d\x03\x4f\x7e\x8a\x52\x38\x03"
"\x04\xb5\x1a\xc3\xc0\x89\x69\xe2\x77\xf2\x1b\x35\xa6\x0b\x48\xfc"
"\x47\x66\x99\x78\x02\x21\x00\xdc\x55\x4e\x07\x96\x0b\x81\xb6\x80"
"\xb1\xae\xe0\x40\xb9\x90\xa5\xf4\xc4\x90\x49\xbb\xa2\xa1\x62\x70"
"\xc5\x88\x51\x39\xe8\xa8\xfb",
.c_size = 71,
.public_key_vec = true,
},
{
.key = /* secp256r1(sha1) */
"\x04\xb9\x7b\xbb\xd7\x17\x64\xd2\x7e\xfc\x81\x5d\x87\x06\x83\x41"
@@ -1827,7 +1962,8 @@ static const struct sig_testvec p1363_ecdsa_nist_p256_tv_template[] = {
};
/*
* EC-RDSA test vectors are generated by gost-engine.
* EC-RDSA test vectors generated by gost-engine, followed by constructed
* exceptional-point regression vectors.
*/
static const struct sig_testvec ecrdsa_tv_template[] = {
{
@@ -1973,6 +2109,195 @@ static const struct sig_testvec ecrdsa_tv_template[] = {
.m_size = 64,
.public_key_vec = true,
},
/*
* Constructed EC-RDSA exceptional-point vectors.
* With Q = dG, choose k = z1 + d*z2 (mod n), r = x(kG) mod n,
* e = -r/z2 (mod n), and s = r*d + k*e (mod n).
* The input digest is e, encoded little-endian.
*/
/* cp256a: Q=G, z1 = 3, z2 = 1. */
{
.key =
"\x04\x40\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x14\x1e\x9f\x9e\x9c\xc9\xac\x22\xb1\xe3\x23\xdf\x2d\x4f"
"\x29\x35\x76\x2b\x3f\x45\x5a\x50\xdf\x27\xda\x9c\x98\xe0\x71\xe4"
"\x91\x8d",
.key_len = 66,
.params = /* OID_gostCPSignA */
"\x30\x13\x06\x07\x2a\x85\x03\x02\x02\x23\x01\x06\x08\x2a\x85\x03"
"\x07\x01\x01\x02\x02",
.param_len = 21,
.c =
"\x1a\xed\x44\xae\xd4\x4a\xed\x44\xae\xd4\x4a\xed\x44\xae\xd4\x49"
"\x32\x67\xe0\x26\x16\xfd\xb7\xaf\xa4\xd7\x3e\x61\xd4\xf9\x7b\x94"
"\xf7\x06\x3e\x70\x63\xe7\x06\x3e\x70\x63\xe7\x06\x3e\x70\x63\xe7"
"\x06\x3e\x70\x63\xe7\x06\x3e\x70\x63\xe7\x06\x3e\x70\x63\xe4\xb7",
.c_size = 64,
.m =
"\xdc\xd3\xfd\x46\xcb\x14\x9d\xe1\x8f\x92\x54\xb2\x0c\xa0\x22\x66"
"\x18\x9c\x8f\xc1\xf9\x18\x9c\x8f\xc1\xf9\x18\x9c\x8f\xc1\xf9\x08",
.m_size = 32,
.algo = OID_gost2012PKey256,
.public_key_vec = true,
},
/* cp256a: Q=-G, z1 = 7, z2 = 6. */
{
.key =
"\x04\x40\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x83\xdf\x60\x61\x63\x36\x53\xdd\x4e\x1c\xdc\x20\xd2\xb0"
"\xd6\xca\x89\xd4\xc0\xba\xa5\xaf\x20\xd8\x25\x63\x67\x1f\x8e\x1b"
"\x6e\x72",
.key_len = 66,
.params = /* OID_gostCPSignA */
"\x30\x13\x06\x07\x2a\x85\x03\x02\x02\x23\x01\x06\x08\x2a\x85\x03"
"\x07\x01\x01\x02\x02",
.param_len = 21,
.c =
"\x2a\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa"
"\x92\x10\x2d\x68\x19\x8f\x22\xd5\x60\xeb\x59\xd6\xf3\xe5\x9e\xc2"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01",
.c_size = 64,
.m =
"\xc3\x9e\xe5\xf3\xd6\x59\xeb\x60\xd5\x22\x8f\x19\x68\x2d\x10\x92"
"\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\xaa\x2a",
.m_size = 32,
.algo = OID_gost2012PKey256,
.public_key_vec = true,
},
/* cp256a: Q=-2G, z1 = 5, z2 = 2. */
{
.key =
"\x04\x40\x95\xfd\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\xff\xff\x14\x1e\x9f\x9e\x9c\xc9\xac\x22\xb1\xe3\x23\xdf\x2d\x4f"
"\x29\x35\x76\x2b\x3f\x45\x5a\x50\xdf\x27\xda\x9c\x98\xe0\x71\xe4"
"\x91\x8d",
.key_len = 66,
.params = /* OID_gostCPSignA */
"\x30\x13\x06\x07\x2a\x85\x03\x02\x02\x23\x01\x06\x08\x2a\x85\x03"
"\x07\x01\x01\x02\x02",
.param_len = 21,
.c =
"\x7f\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\xb6\x30\x88\x38\x4c\xad\x68\x80\x22\xc2\x0d\x84\xdb\xb0\xdc\x47"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x01",
.c_size = 64,
.m =
"\x49\xdc\xb0\xdb\x84\x0d\xc2\x22\x80\x68\xad\x4c\x38\x88\x30\xb6"
"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\x7f",
.m_size = 32,
.algo = OID_gost2012PKey256,
.public_key_vec = true,
},
/* tc512a: Q=G, z1 = 3, z2 = 1. */
{
.key =
"\x04\x81\x80\x03\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\xa4\xf2\x15\x52\xcb\x89\xa5\x89\xb8\xf5\x35\xc2\x5f"
"\xfe\x28\x80\xe9\x41\x3a\x0e\xa5\xe6\x75\x3d\xe9\x36\xd0\x4f\xbe"
"\x26\x16\xdf\x21\xa9\xef\xcb\xfd\x64\x80\x77\xc1\xab\xf1\xac\x93"
"\x1c\x5e\xce\xe6\x50\x54\xe2\x16\x88\x1b\xa6\xe3\x6a\x83\x7a\xe8"
"\xcf\x03\x75",
.key_len = 131,
.params = /* OID_gostTC26Sign512A */
"\x30\x0b\x06\x09\x2a\x85\x03\x07\x01\x02\x01\x02\x01",
.param_len = 13,
.c =
"\xd8\xc0\xd7\xe3\xfb\xa6\xca\xff\x6a\xd1\xb4\xb4\x82\x1d\x15\x6f"
"\xa7\xc7\xbd\x63\x95\xb8\x29\x0d\xd4\xfa\xb1\x1c\x36\xbd\x32\x8d"
"\x1a\xba\xf1\x2e\xbc\x7b\xf2\x02\x96\xf8\xef\x2a\x5e\x72\x64\x86"
"\x67\x62\xfb\x62\x8e\x83\x53\x63\xb7\xe6\x78\x3c\x42\xd7\x0d\x1d"
"\xb7\xbf\xb8\x09\x56\xc8\x67\x00\x31\xba\x19\x19\x29\xf6\x4e\x30"
"\x1d\x68\x16\x34\x23\x6d\x47\xa6\x0e\x57\x1a\x4b\xed\xc0\xef\x25"
"\x74\x52\xef\x78\xb5\xb9\x8d\xbb\x3d\x9f\x31\x29\xd9\x34\x94\x33"
"\xce\x2a\x3a\x35\xcb\x51\x9c\x91\xe2\xd6\x33\xd7\xb3\x73\xae\x16",
.c_size = 128,
.m =
"\x5f\x04\x9d\x6b\x69\x7d\xf7\xe7\xcb\x1b\x81\x2f\x76\xfe\x20\xcd"
"\x2c\xcc\xd0\x74\x63\xfa\x52\x32\x56\xfb\xd3\x3e\xba\xa5\x93\xb3"
"\xd9\x10\x3f\x12\xb4\xe5\xa8\xf1\x59\xb8\x92\xdc\xcb\xe9\x97\xe2"
"\xcf\xb1\x09\xd6\xe6\xe6\x45\xce\xff\x98\x37\xa9\xf6\x47\x40\x48",
.m_size = 64,
.algo = OID_gost2012PKey512,
.public_key_vec = true,
},
/* tc512a: Q=-G, z1 = 7, z2 = 6. */
{
.key =
"\x04\x81\x80\x03\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x23\x0b\xea\xad\x34\x76\x5a\x76\x47\x0a\xca\x3d\xa0"
"\x01\xd7\x7f\x16\xbe\xc5\xf1\x5a\x19\x8a\xc2\x16\xc9\x2f\xb0\x41"
"\xd9\xe9\x20\xde\x56\x10\x34\x02\x9b\x7f\x88\x3e\x54\x0e\x53\x6c"
"\xe3\xa1\x31\x19\xaf\xab\x1d\xe9\x77\xe4\x59\x1c\x95\x7c\x85\x17"
"\x30\xfc\x8a",
.key_len = 131,
.params = /* OID_gostTC26Sign512A */
"\x30\x0b\x06\x09\x2a\x85\x03\x07\x01\x02\x01\x02\x01",
.param_len = 13,
.c =
"\x7f\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\x93\xf3\x4a\x99\x7a\x46\xc4\x88\xb7\xf9\x15\xc6\xa7\x02\xb0\x30"
"\x4d\xa5\x9c\x55\xfd\x69\x5c\x2e\xe5\x66\xd8\xa0\x8f\x88\x59\x37"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x03",
.c_size = 128,
.m =
"\x3a\x59\x88\x8f\xa0\xd8\x66\xe5\x2e\x5c\x69\xfd\x55\x9c\xa5\x4d"
"\x30\xb0\x02\xa7\xc6\x15\xf9\xb7\x88\xc4\x46\x7a\x99\x4a\xf3\x93"
"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\x7f",
.m_size = 64,
.algo = OID_gost2012PKey512,
.public_key_vec = true,
},
/* tc512a: Q=-2G, z1 = 5, z2 = 2. */
{
.key =
"\x04\x81\x80\x7c\x13\xea\xd2\xd9\xaf\x82\xb9\x1f\xb2\xfd\xe1\x8d"
"\xf4\x5b\x37\xe4\xf2\x04\x6a\x2a\x1d\x15\x16\x95\x2a\x5d\x40\xcd"
"\xbb\x34\x44\x2f\x2b\x13\x0a\x47\xb0\xf6\xe5\xa5\x58\x3a\xf4\x54"
"\x09\xb0\x1d\xf5\x5c\xf1\xbf\x9d\x86\xa5\x97\xab\x96\x29\x62\xfc"
"\xdc\x89\x3b\x76\x3d\x50\x6e\x8a\xcf\x02\x4c\x74\x0e\x6e\xe0\x1f"
"\x28\xab\x27\x9b\x20\x02\xc8\xc4\x12\xcb\x8a\xe3\xa4\x27\xce\x39"
"\x62\xdf\x35\x6d\xc1\x65\x7f\x7b\x48\x90\x11\x8f\x19\x7c\x1e\x67"
"\x91\x97\xeb\x90\x85\x25\xfc\x86\xb3\x88\x6e\x5c\x57\x1f\x1d\x1d"
"\x3b\xec\x37",
.key_len = 131,
.params = /* OID_gostTC26Sign512A */
"\x30\x0b\x06\x09\x2a\x85\x03\x07\x01\x02\x01\x02\x01",
.param_len = 13,
.c =
"\x7f\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\x93\xf3\x4a\x99\x7a\x46\xc4\x88\xb7\xf9\x15\xc6\xa7\x02\xb0\x30"
"\x4d\xa5\x9c\x55\xfd\x69\x5c\x2e\xe5\x66\xd8\xa0\x8f\x88\x59\x33"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00"
"\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x03",
.c_size = 128,
.m =
"\x39\x59\x88\x8f\xa0\xd8\x66\xe5\x2e\x5c\x69\xfd\x55\x9c\xa5\x4d"
"\x30\xb0\x02\xa7\xc6\x15\xf9\xb7\x88\xc4\x46\x7a\x99\x4a\xf3\x93"
"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff"
"\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\xff\x7f",
.m_size = 64,
.algo = OID_gost2012PKey512,
.public_key_vec = true,
},
};
/*
crypto/zstd.c
+28 -12
View File
@@ -96,6 +96,7 @@ static int zstd_compress_one(struct acomp_req *req, struct zstd_ctx *ctx,
static int zstd_compress(struct acomp_req *req)
{
bool stream_initialized = false;
struct crypto_acomp_stream *s;
unsigned int pos, scur, dcur;
unsigned int total_out = 0;
@@ -115,12 +116,6 @@ static int zstd_compress(struct acomp_req *req)
if (ret)
goto out;
ctx->cctx = zstd_init_cstream(&ctx->params, 0, ctx->wksp, ctx->wksp_size);
if (!ctx->cctx) {
ret = -EINVAL;
goto out;
}
do {
dcur = acomp_walk_next_dst(&walk);
if (!dcur) {
@@ -142,6 +137,19 @@ static int zstd_compress(struct acomp_req *req)
goto out;
}
if (!stream_initialized) {
ctx->cctx = zstd_init_cstream(&ctx->params, 0,
ctx->wksp, ctx->wksp_size);
if (!ctx->cctx) {
/* Release in the reverse of the map order. */
acomp_walk_done_src(&walk, 0);
acomp_walk_done_dst(&walk, 0);
ret = -EINVAL;
goto out;
}
stream_initialized = true;
}
if (scur) {
inbuf.pos = 0;
inbuf.src = walk.src.virt.addr;
@@ -207,6 +215,7 @@ static int zstd_decompress_one(struct acomp_req *req, struct zstd_ctx *ctx,
static int zstd_decompress(struct acomp_req *req)
{
bool stream_initialized = false;
struct crypto_acomp_stream *s;
unsigned int total_out = 0;
unsigned int scur, dcur;
@@ -224,12 +233,6 @@ static int zstd_decompress(struct acomp_req *req)
if (ret)
goto out;
ctx->dctx = zstd_init_dstream(ZSTD_MAX_SIZE, ctx->wksp, ctx->wksp_size);
if (!ctx->dctx) {
ret = -EINVAL;
goto out;
}
do {
scur = acomp_walk_next_src(&walk);
if (scur) {
@@ -255,6 +258,19 @@ static int zstd_decompress(struct acomp_req *req)
goto out;
}
if (!stream_initialized) {
ctx->dctx = zstd_init_dstream(ZSTD_MAX_SIZE, ctx->wksp,
ctx->wksp_size);
if (!ctx->dctx) {
/* Release in the reverse of the map order. */
acomp_walk_done_dst(&walk, 0);
acomp_walk_done_src(&walk, 0);
ret = -EINVAL;
goto out;
}
stream_initialized = true;
}
outbuf.pos = 0;
outbuf.dst = (u8 *)walk.dst.virt.addr;
outbuf.size = dcur;
drivers/char/hw_random/amd-rng.c
+12 -17
View File
@@ -80,7 +80,7 @@ static int amd_rng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
if (timeout-- == 0)
return read;
} else {
return 0;
return read;
}
} else {
*data = ioread32(priv->iobase + RNGDATA);
@@ -129,19 +129,15 @@ static int __init amd_rng_mod_init(void)
{
int err;
struct pci_dev *pdev = NULL;
const struct pci_device_id *ent;
u32 pmbase;
struct amd768_priv *priv;
for_each_pci_dev(pdev) {
ent = pci_match_id(pci_tbl, pdev);
if (ent)
goto found;
}
/* Device not found. */
return -ENODEV;
for_each_pci_dev(pdev)
if (pci_match_id(pci_tbl, pdev))
break;
if (!pdev)
return -ENODEV;
found:
err = pci_read_config_dword(pdev, 0x58, &pmbase);
if (err) {
err = pcibios_err_to_errno(err);
@@ -162,16 +158,16 @@ found:
if (!request_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE, DRV_NAME)) {
dev_err(&pdev->dev, DRV_NAME " region 0x%x already in use!\n",
pmbase + 0xF0);
pmbase + PMBASE_OFFSET);
err = -EBUSY;
goto out;
}
priv->iobase = ioport_map(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
if (!priv->iobase) {
pr_err(DRV_NAME "Cannot map ioport\n");
pr_err(DRV_NAME " cannot map ioport\n");
err = -EINVAL;
goto err_iomap;
goto err;
}
amd_rng.priv = (unsigned long)priv;
@@ -182,13 +178,12 @@ found:
err = hwrng_register(&amd_rng);
if (err) {
pr_err(DRV_NAME " registering failed (%d)\n", err);
goto err_hwrng;
ioport_unmap(priv->iobase);
goto err;
}
return 0;
err_hwrng:
ioport_unmap(priv->iobase);
err_iomap:
err:
release_region(pmbase + PMBASE_OFFSET, PMBASE_SIZE);
out:
kfree(priv);
drivers/char/hw_random/atmel-rng.c
+3 -8
View File
@@ -17,6 +17,7 @@
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/pm_runtime.h>
#include <linux/units.h>
#define TRNG_CR 0x00
#define TRNG_MR 0x04
@@ -85,20 +86,14 @@ out:
static int atmel_trng_init(struct atmel_trng *trng)
{
unsigned long rate;
int ret;
ret = clk_prepare_enable(trng->clk);
if (ret)
return ret;
if (trng->has_half_rate) {
rate = clk_get_rate(trng->clk);
/* if peripheral clk is above 100MHz, set HALFR */
if (rate > 100000000)
writel(TRNG_HALFR, trng->base + TRNG_MR);
}
if (trng->has_half_rate && clk_get_rate(trng->clk) > 100 * HZ_PER_MHZ)
writel(TRNG_HALFR, trng->base + TRNG_MR);
writel(TRNG_KEY | 1, trng->base + TRNG_CR);
drivers/char/hw_random/ba431-rng.c
+1 -1
View File
@@ -147,7 +147,7 @@ static int ba431_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
}
}
n *= sizeof(data);
n *= sizeof(*data);
return (n || !wait) ? n : -EIO;
}
drivers/char/hw_random/cctrng.c
+9 -18
View File
@@ -86,17 +86,12 @@ static inline u32 cc_ioread(struct cctrng_drvdata *drvdata, u32 reg)
static int cc_trng_pm_get(struct device *dev)
{
int rc = 0;
rc = pm_runtime_get_sync(dev);
/* pm_runtime_get_sync() can return 1 as a valid return code */
return (rc == 1 ? 0 : rc);
return pm_runtime_resume_and_get(dev);
}
static void cc_trng_pm_put_suspend(struct device *dev)
{
int rc = 0;
int rc;
rc = pm_runtime_put_autosuspend(dev);
if (rc)
@@ -213,7 +208,7 @@ static int cctrng_read(struct hwrng *rng, void *data, size_t max, bool wait)
struct cctrng_drvdata *drvdata = (struct cctrng_drvdata *)rng->priv;
struct device *dev = &(drvdata->pdev->dev);
u32 *buf = (u32 *)drvdata->circ.buf;
size_t copied = 0;
size_t copied;
size_t cnt_w;
size_t size;
size_t left;
@@ -273,7 +268,7 @@ static int cctrng_read(struct hwrng *rng, void *data, size_t max, bool wait)
static void cc_trng_hw_trigger(struct cctrng_drvdata *drvdata)
{
u32 tmp_smpl_cnt = 0;
u32 tmp_smpl_cnt;
struct device *dev = &(drvdata->pdev->dev);
dev_dbg(dev, "cctrng hw trigger.\n");
@@ -314,8 +309,8 @@ static void cc_trng_hw_trigger(struct cctrng_drvdata *drvdata)
static void cc_trng_compwork_handler(struct work_struct *w)
{
u32 isr = 0;
u32 ehr_valid = 0;
u32 isr;
u32 ehr_valid;
struct cctrng_drvdata *drvdata =
container_of(w, struct cctrng_drvdata, compwork);
struct device *dev = &(drvdata->pdev->dev);
@@ -458,7 +453,7 @@ static int cctrng_probe(struct platform_device *pdev)
{
struct cctrng_drvdata *drvdata;
struct device *dev = &pdev->dev;
int rc = 0;
int rc;
u32 val;
int irq;
@@ -539,7 +534,8 @@ static int cctrng_probe(struct platform_device *pdev)
rc = devm_hwrng_register(dev, &drvdata->rng);
if (rc) {
dev_err(dev, "Could not register hwrng device.\n");
goto post_pm_err;
cc_trng_pm_fini(drvdata);
return rc;
}
/* trigger HW to start generate data */
@@ -552,11 +548,6 @@ static int cctrng_probe(struct platform_device *pdev)
dev_info(dev, "ARM cctrng device initialized\n");
return 0;
post_pm_err:
cc_trng_pm_fini(drvdata);
return rc;
}
static void cctrng_remove(struct platform_device *pdev)
drivers/char/hw_random/core.c
+1
View File
@@ -376,6 +376,7 @@ static ssize_t rng_current_store(struct device *dev,
cur_rng_set_by_user = 1;
drop_current_rng();
} else {
err = -ENODEV;
list_for_each_entry(rng, &rng_list, list) {
if (sysfs_streq(rng->name, buf)) {
err = set_current_rng(rng);
drivers/char/hw_random/imx-rngc.c
+5 -5
View File
@@ -258,7 +258,7 @@ static int __init imx_rngc_probe(struct platform_device *pdev)
if (IS_ERR(rngc->base))
return PTR_ERR(rngc->base);
rngc->clk = devm_clk_get(&pdev->dev, NULL);
rngc->clk = devm_clk_get_optional(&pdev->dev, NULL);
if (IS_ERR(rngc->clk))
return dev_err_probe(&pdev->dev, PTR_ERR(rngc->clk), "Cannot get rng_clk\n");
@@ -266,7 +266,9 @@ static int __init imx_rngc_probe(struct platform_device *pdev)
if (irq < 0)
return irq;
clk_prepare_enable(rngc->clk);
ret = clk_prepare_enable(rngc->clk);
if (ret)
return dev_err_probe(&pdev->dev, ret, "Cannot enable rng_clk\n");
ver_id = readl(rngc->base + RNGC_VER_ID);
rng_type = FIELD_GET(RNG_TYPE, ver_id);
@@ -338,9 +340,7 @@ static int imx_rngc_resume(struct device *dev)
{
struct imx_rngc *rngc = dev_get_drvdata(dev);
clk_prepare_enable(rngc->clk);
return 0;
return clk_prepare_enable(rngc->clk);
}
static const struct dev_pm_ops imx_rngc_pm_ops = {
drivers/char/hw_random/intel-rng.c
+16 -18
View File
@@ -305,11 +305,11 @@ static int __init intel_init_hw_struct(struct intel_rng_hw *intel_rng_hw,
if ((intel_rng_hw->bios_cntl_val &
(BIOS_CNTL_LOCK_ENABLE_MASK|BIOS_CNTL_WRITE_ENABLE_MASK))
== BIOS_CNTL_LOCK_ENABLE_MASK) {
static __initdata /*const*/ char warning[] =
PFX "Firmware space is locked read-only. If you can't or\n"
PFX "don't want to disable this in firmware setup, and if\n"
PFX "you are certain that your system has a functional\n"
PFX "RNG, try using the 'no_fwh_detect' option.\n";
static const char warning[] __initconst =
PFX "Firmware space is locked read-only. If you can't or\n"
PFX "don't want to disable this in firmware setup, and if\n"
PFX "you are certain that your system has a functional\n"
PFX "RNG, try using the 'no_fwh_detect' option.\n";
if (no_fwh_detect)
return -ENODEV;
@@ -318,8 +318,8 @@ PFX "RNG, try using the 'no_fwh_detect' option.\n";
}
intel_rng_hw->mem = ioremap(INTEL_FWH_ADDR, INTEL_FWH_ADDR_LEN);
if (intel_rng_hw->mem == NULL)
return -EBUSY;
if (!intel_rng_hw->mem)
return -ENOMEM;
return 0;
}
@@ -327,7 +327,7 @@ PFX "RNG, try using the 'no_fwh_detect' option.\n";
static int __init intel_rng_mod_init(void)
{
int err = -ENODEV;
int err;
int i;
struct pci_dev *dev = NULL;
void __iomem *mem;
@@ -339,7 +339,7 @@ static int __init intel_rng_mod_init(void)
NULL);
if (!dev)
goto out; /* Device not found. */
return -ENODEV;
if (no_fwh_detect < 0) {
pci_dev_put(dev);
@@ -349,7 +349,7 @@ static int __init intel_rng_mod_init(void)
intel_rng_hw = kmalloc_obj(*intel_rng_hw);
if (!intel_rng_hw) {
pci_dev_put(dev);
goto out;
return -ENOMEM;
}
err = intel_init_hw_struct(intel_rng_hw, dev);
@@ -358,7 +358,7 @@ static int __init intel_rng_mod_init(void)
kfree(intel_rng_hw);
if (err == -ENODEV)
goto fwh_done;
goto out;
return err;
}
/*
@@ -374,21 +374,19 @@ static int __init intel_rng_mod_init(void)
iounmap(intel_rng_hw->mem);
kfree(intel_rng_hw);
if (err)
goto out;
return err;
fwh_done:
err = -ENOMEM;
mem = ioremap(INTEL_RNG_ADDR, INTEL_RNG_ADDR_LEN);
if (!mem)
goto out;
return -ENOMEM;
intel_rng.priv = (unsigned long)mem;
/* Check for Random Number Generator */
err = -ENODEV;
hw_status = hwstatus_get(mem);
if ((hw_status & INTEL_RNG_PRESENT) == 0) {
iounmap(mem);
goto out;
return -ENODEV;
}
pr_info("Intel 82802 RNG detected\n");
@@ -397,10 +395,10 @@ fwh_done:
pr_err(PFX "RNG registering failed (%d)\n",
err);
iounmap(mem);
return err;
}
out:
return err;
return 0;
}
static void __exit intel_rng_mod_exit(void)
drivers/char/hw_random/jh7110-trng.c
+29 -10
View File
@@ -320,9 +320,17 @@ static int starfive_trng_probe(struct platform_device *pdev)
return dev_err_probe(&pdev->dev, PTR_ERR(trng->rst),
"Error getting hardware reset line\n");
clk_prepare_enable(trng->hclk);
clk_prepare_enable(trng->ahb);
reset_control_deassert(trng->rst);
ret = clk_prepare_enable(trng->hclk);
if (ret)
return ret;
ret = clk_prepare_enable(trng->ahb);
if (ret)
goto disable_hclk;
ret = reset_control_deassert(trng->rst);
if (ret)
goto disable_ahb;
trng->rng.name = dev_driver_string(&pdev->dev);
trng->rng.init = starfive_trng_init;
@@ -342,13 +350,18 @@ static int starfive_trng_probe(struct platform_device *pdev)
pm_runtime_disable(&pdev->dev);
reset_control_assert(trng->rst);
clk_disable_unprepare(trng->ahb);
clk_disable_unprepare(trng->hclk);
return dev_err_probe(&pdev->dev, ret, "Failed to register hwrng\n");
ret = dev_err_probe(&pdev->dev, ret, "Failed to register hwrng\n");
goto disable_ahb;
}
return 0;
disable_ahb:
clk_disable_unprepare(trng->ahb);
disable_hclk:
clk_disable_unprepare(trng->hclk);
return ret;
}
static int __maybe_unused starfive_trng_suspend(struct device *dev)
@@ -364,11 +377,17 @@ static int __maybe_unused starfive_trng_suspend(struct device *dev)
static int __maybe_unused starfive_trng_resume(struct device *dev)
{
struct starfive_trng *trng = dev_get_drvdata(dev);
int ret;
clk_prepare_enable(trng->hclk);
clk_prepare_enable(trng->ahb);
ret = clk_prepare_enable(trng->hclk);
if (ret)
return ret;
return 0;
ret = clk_prepare_enable(trng->ahb);
if (ret)
clk_disable_unprepare(trng->hclk);
return ret;
}
static const struct dev_pm_ops starfive_trng_pm_ops = {
drivers/char/hw_random/omap-rng.c
+4 -4
View File
@@ -530,7 +530,7 @@ static void omap_rng_remove(struct platform_device *pdev)
clk_disable_unprepare(priv->clk_reg);
}
static int __maybe_unused omap_rng_suspend(struct device *dev)
static int omap_rng_suspend(struct device *dev)
{
struct omap_rng_dev *priv = dev_get_drvdata(dev);
@@ -540,7 +540,7 @@ static int __maybe_unused omap_rng_suspend(struct device *dev)
return 0;
}
static int __maybe_unused omap_rng_resume(struct device *dev)
static int omap_rng_resume(struct device *dev)
{
struct omap_rng_dev *priv = dev_get_drvdata(dev);
int ret;
@@ -556,12 +556,12 @@ static int __maybe_unused omap_rng_resume(struct device *dev)
return 0;
}
static SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
static DEFINE_SIMPLE_DEV_PM_OPS(omap_rng_pm, omap_rng_suspend, omap_rng_resume);
static struct platform_driver omap_rng_driver = {
.driver = {
.name = "omap_rng",
.pm = &omap_rng_pm,
.pm = pm_sleep_ptr(&omap_rng_pm),
.of_match_table = of_match_ptr(omap_rng_of_match),
},
.probe = omap_rng_probe,
drivers/char/hw_random/omap3-rom-rng.c
+2 -5
View File
@@ -42,12 +42,9 @@ static int omap3_rom_rng_read(struct hwrng *rng, void *data, size_t max, bool w)
ddata = (struct omap_rom_rng *)rng->priv;
r = pm_runtime_get_sync(ddata->dev);
if (r < 0) {
pm_runtime_put_noidle(ddata->dev);
r = pm_runtime_resume_and_get(ddata->dev);
if (r < 0)
return r;
}
ptr = virt_to_phys(data);
r = ddata->rom_rng_call(ptr, 4, RNG_GEN_HW);
drivers/char/hw_random/stm32-rng.c
+7 -15
View File
@@ -156,7 +156,7 @@ end:
*/
static int stm32_rng_conceal_seed_error_sw_reset(struct stm32_rng_private *priv)
{
unsigned int i = 0;
unsigned int i;
u32 sr = readl_relaxed(priv->base + RNG_SR);
writel_relaxed(sr & ~RNG_SR_SEIS, priv->base + RNG_SR);
@@ -187,7 +187,7 @@ static int stm32_rng_read(struct hwrng *rng, void *data, size_t max, bool wait)
{
struct stm32_rng_private *priv = container_of(rng, struct stm32_rng_private, rng);
unsigned int i = 0;
int retval = 0, err = 0;
int retval, err;
u32 sr;
retval = pm_runtime_resume_and_get(priv->dev);
@@ -264,7 +264,7 @@ static uint stm32_rng_clock_freq_restrain(struct hwrng *rng)
{
struct stm32_rng_private *priv =
container_of(rng, struct stm32_rng_private, rng);
unsigned long clock_rate = 0;
unsigned long clock_rate;
uint clock_div = 0;
clock_rate = clk_get_rate(priv->clk_bulk[0].clk);
@@ -277,7 +277,7 @@ static uint stm32_rng_clock_freq_restrain(struct hwrng *rng)
while ((clock_rate >> clock_div) > priv->data->max_clock_rate)
clock_div++;
pr_debug("RNG clk rate : %lu\n", clk_get_rate(priv->clk_bulk[0].clk) >> clock_div);
pr_debug("RNG clk rate: %lu\n", clock_rate >> clock_div);
return clock_div;
}
@@ -528,14 +528,13 @@ static int stm32_rng_probe(struct platform_device *ofdev)
struct device *dev = &ofdev->dev;
struct device_node *np = ofdev->dev.of_node;
struct stm32_rng_private *priv;
struct resource *res;
int ret;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->base = devm_platform_get_and_ioremap_resource(ofdev, 0, &res);
priv->base = devm_platform_ioremap_resource(ofdev, 0);
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);
@@ -569,18 +568,11 @@ static int stm32_rng_probe(struct platform_device *ofdev)
return dev_err_probe(dev, -EINVAL, "Failed to get clocks: %d\n", ret);
if (priv->data->nb_clock == 2) {
const char *id = priv->clk_bulk[1].id;
struct clk *clk = priv->clk_bulk[1].clk;
if (!priv->clk_bulk[0].id || !priv->clk_bulk[1].id)
return dev_err_probe(dev, -EINVAL, "Missing clock name\n");
if (strcmp(priv->clk_bulk[0].id, "core")) {
priv->clk_bulk[1].id = priv->clk_bulk[0].id;
priv->clk_bulk[1].clk = priv->clk_bulk[0].clk;
priv->clk_bulk[0].id = id;
priv->clk_bulk[0].clk = clk;
}
if (strcmp(priv->clk_bulk[0].id, "core"))
swap(priv->clk_bulk[0], priv->clk_bulk[1]);
}
pm_runtime_set_autosuspend_delay(dev, 100);
drivers/char/hw_random/virtio-rng.c
+3 -3
View File
@@ -81,13 +81,13 @@ static unsigned int copy_data(struct virtrng_info *vi, void *buf,
* steered into adjacent slab memory, including under
* speculation.
*/
avail = min_t(unsigned int, vi->data_avail, sizeof(vi->data));
avail = min(vi->data_avail, sizeof(vi->data));
if (vi->data_idx >= avail) {
vi->data_avail = 0;
request_entropy(vi);
return 0;
}
size = min_t(unsigned int, size, avail - vi->data_idx);
size = min(size, avail - vi->data_idx);
idx = array_index_nospec(vi->data_idx, sizeof(vi->data));
memcpy(buf, vi->data + idx, size);
vi->data_idx += size;
@@ -162,7 +162,7 @@ static int probe_common(struct virtio_device *vdev)
err = index;
goto err_ida;
}
sprintf(vi->name, "virtio_rng.%d", index);
snprintf(vi->name, sizeof(vi->name), "virtio_rng.%d", vi->index);
init_completion(&vi->have_data);
vi->hwrng = (struct hwrng) {
drivers/crypto/allwinner/sun8i-ss/sun8i-ss-hash.c
+1 -2
View File
@@ -120,12 +120,11 @@ int sun8i_ss_hash_init_tfm(struct crypto_ahash *tfm)
memcpy(algt->fbname, crypto_ahash_driver_name(op->fallback_tfm),
CRYPTO_MAX_ALG_NAME);
err = pm_runtime_get_sync(op->ss->dev);
err = pm_runtime_resume_and_get(op->ss->dev);
if (err < 0)
goto error_pm;
return 0;
error_pm:
pm_runtime_put_noidle(op->ss->dev);
crypto_free_ahash(op->fallback_tfm);
return err;
}
drivers/crypto/amcc/crypto4xx_core.c
+21 -14
View File
@@ -1046,8 +1046,7 @@ static void crypto4xx_bh_tasklet_cb(unsigned long data)
static inline irqreturn_t crypto4xx_interrupt_handler(int irq, void *data,
u32 clr_val)
{
struct device *dev = data;
struct crypto4xx_core_device *core_dev = dev_get_drvdata(dev);
struct crypto4xx_core_device *core_dev = data;
writel(clr_val, core_dev->dev->ce_base + CRYPTO4XX_INT_CLR);
tasklet_schedule(&core_dev->tasklet);
@@ -1206,9 +1205,19 @@ static int crypto4xx_probe(struct platform_device *ofdev)
struct device *dev = &ofdev->dev;
struct crypto4xx_core_device *core_dev;
struct device_node *np;
void __iomem *ce_base;
int irq;
u32 pvr;
bool is_revb = true;
irq = platform_get_irq(ofdev, 0);
if (irq < 0)
return irq;
ce_base = devm_platform_ioremap_resource(ofdev, 0);
if (IS_ERR(ce_base))
return PTR_ERR(ce_base);
np = of_find_compatible_node(NULL, NULL, "amcc,ppc460ex-crypto");
if (np) {
mtdcri(SDR0, PPC460EX_SDR0_SRST,
@@ -1251,9 +1260,7 @@ static int crypto4xx_probe(struct platform_device *ofdev)
if (!core_dev->dev)
return -ENOMEM;
core_dev->dev->ce_base = devm_platform_ioremap_resource(ofdev, 0);
if (IS_ERR(core_dev->dev->ce_base))
return PTR_ERR(core_dev->dev->ce_base);
core_dev->dev->ce_base = ce_base;
/*
* Older version of 460EX/GT have a hardware bug.
@@ -1291,15 +1298,11 @@ static int crypto4xx_probe(struct platform_device *ofdev)
(unsigned long) dev);
/* Register for Crypto isr, Crypto Engine IRQ */
core_dev->irq = platform_get_irq(ofdev, 0);
if (core_dev->irq < 0) {
rc = core_dev->irq;
goto err_tasklet;
}
core_dev->irq = irq;
rc = request_irq(core_dev->irq,
is_revb ? crypto4xx_ce_interrupt_handler_revb :
crypto4xx_ce_interrupt_handler,
0, KBUILD_MODNAME, dev);
0, KBUILD_MODNAME, core_dev);
if (rc)
goto err_tasklet;
@@ -1312,11 +1315,15 @@ static int crypto4xx_probe(struct platform_device *ofdev)
if (rc)
goto err_irq;
ppc4xx_trng_probe(core_dev);
rc = ppc4xx_trng_probe(core_dev);
if (rc)
goto err_crypto;
return 0;
err_crypto:
crypto4xx_unregister_alg(core_dev->dev);
err_irq:
free_irq(core_dev->irq, dev);
free_irq(core_dev->irq, core_dev);
err_tasklet:
tasklet_kill(&core_dev->tasklet);
err_build_sdr:
@@ -1337,7 +1344,7 @@ static void crypto4xx_remove(struct platform_device *ofdev)
* Free IRQ before killing the tasklet to prevent the interrupt
* handler from rescheduling the tasklet after it has been killed.
*/
free_irq(core_dev->irq, dev);
free_irq(core_dev->irq, core_dev);
tasklet_kill(&core_dev->tasklet);
/* Un-register with Linux CryptoAPI */
crypto4xx_unregister_alg(core_dev->dev);
drivers/crypto/amcc/crypto4xx_trng.c
+10 -5
View File
@@ -68,7 +68,7 @@ static const struct of_device_id ppc4xx_trng_match[] = {
{},
};
void ppc4xx_trng_probe(struct crypto4xx_core_device *core_dev)
int ppc4xx_trng_probe(struct crypto4xx_core_device *core_dev)
{
struct crypto4xx_device *dev = core_dev->dev;
struct device_node *trng = NULL;
@@ -79,17 +79,21 @@ void ppc4xx_trng_probe(struct crypto4xx_core_device *core_dev)
trng = of_find_matching_node(NULL, ppc4xx_trng_match);
if (!trng || !of_device_is_available(trng)) {
of_node_put(trng);
return;
return 0;
}
dev->trng_base = of_iomap(trng, 0);
of_node_put(trng);
if (!dev->trng_base)
if (!dev->trng_base) {
err = -EINVAL;
goto err_out;
}
rng = kzalloc_obj(*rng);
if (!rng)
if (!rng) {
err = -ENOMEM;
goto err_out;
}
rng->name = KBUILD_MODNAME;
rng->data_present = ppc4xx_trng_data_present;
@@ -105,13 +109,14 @@ void ppc4xx_trng_probe(struct crypto4xx_core_device *core_dev)
err);
goto err_out;
}
return;
return 0;
err_out:
iounmap(dev->trng_base);
kfree(rng);
dev->trng_base = NULL;
core_dev->trng = NULL;
return err;
}
void ppc4xx_trng_remove(struct crypto4xx_core_device *core_dev)
drivers/crypto/amcc/crypto4xx_trng.h
+3 -3
View File
@@ -13,11 +13,11 @@
#define __CRYPTO4XX_TRNG_H__
#ifdef CONFIG_HW_RANDOM_PPC4XX
void ppc4xx_trng_probe(struct crypto4xx_core_device *core_dev);
int ppc4xx_trng_probe(struct crypto4xx_core_device *core_dev);
void ppc4xx_trng_remove(struct crypto4xx_core_device *core_dev);
#else
static inline void ppc4xx_trng_probe(
struct crypto4xx_core_device *dev __maybe_unused) { }
static inline int ppc4xx_trng_probe(
struct crypto4xx_core_device *dev __maybe_unused) { return 0; }
static inline void ppc4xx_trng_remove(
struct crypto4xx_core_device *dev __maybe_unused) { }
#endif
drivers/crypto/amlogic/amlogic-gxl-cipher.c
+20 -5
View File
@@ -177,10 +177,13 @@ static int meson_cipher(struct skcipher_request *areq)
if (areq->src == areq->dst) {
nr_sgs = dma_map_sg(mc->dev, areq->src, sg_nents(areq->src),
DMA_BIDIRECTIONAL);
if (!nr_sgs) {
dev_err(mc->dev, "Invalid SG count %d\n", nr_sgs);
if (!nr_sgs || nr_sgs > MAXDESC - 3) {
dev_err(mc->dev, "Invalid BIDIR SG count %d\n", nr_sgs);
err = -EINVAL;
goto theend;
if (nr_sgs)
dma_unmap_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_BIDIRECTIONAL);
goto error_keyiv;
}
nr_sgd = nr_sgs;
} else {
@@ -189,14 +192,20 @@ static int meson_cipher(struct skcipher_request *areq)
if (!nr_sgs || nr_sgs > MAXDESC - 3) {
dev_err(mc->dev, "Invalid SG count %d\n", nr_sgs);
err = -EINVAL;
goto theend;
if (nr_sgs)
dma_unmap_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE);
goto error_keyiv;
}
nr_sgd = dma_map_sg(mc->dev, areq->dst, sg_nents(areq->dst),
DMA_FROM_DEVICE);
if (!nr_sgd || nr_sgd > MAXDESC - 3) {
dev_err(mc->dev, "Invalid SG count %d\n", nr_sgd);
err = -EINVAL;
goto theend;
if (nr_sgd)
dma_unmap_sg(mc->dev, areq->dst, sg_nents(areq->dst), DMA_FROM_DEVICE);
goto error_src;
}
}
@@ -251,6 +260,12 @@ static int meson_cipher(struct skcipher_request *areq)
ivsize, 0);
}
}
goto theend;
error_src:
dma_unmap_sg(mc->dev, areq->src, sg_nents(areq->src), DMA_TO_DEVICE);
error_keyiv:
dma_unmap_single(mc->dev, phykeyiv, keyivlen, DMA_TO_DEVICE);
theend:
kfree_sensitive(bkeyiv);
kfree_sensitive(backup_iv);
drivers/crypto/amlogic/amlogic-gxl-core.c
+21 -27
View File
@@ -37,12 +37,13 @@ static irqreturn_t meson_irq_handler(int irq, void *data)
complete(&mc->chanlist[flow].complete);
return IRQ_HANDLED;
}
dev_err(mc->dev, "%s %d Got irq for flow %d but ctrl is empty\n", __func__, irq, flow);
dev_err_ratelimited(mc->dev, "%s %d Got irq for flow %d but ctrl is empty\n", __func__, irq, flow);
return IRQ_NONE;
}
}
dev_err(mc->dev, "%s %d from unknown irq\n", __func__, irq);
return IRQ_HANDLED;
dev_err_ratelimited(mc->dev, "%s %d from unknown irq\n", __func__, irq);
return IRQ_NONE;
}
static struct meson_alg_template mc_algs[] = {
@@ -243,33 +244,29 @@ static int meson_crypto_probe(struct platform_device *pdev)
if (IS_ERR(mc->base))
return PTR_ERR(mc->base);
mc->busclk = devm_clk_get(&pdev->dev, "blkmv");
mc->busclk = devm_clk_get_enabled(&pdev->dev, "blkmv");
if (IS_ERR(mc->busclk)) {
err = PTR_ERR(mc->busclk);
dev_err(&pdev->dev, "Cannot get core clock err=%d\n", err);
return err;
}
for (i = 0; i < MAXFLOW; i++) {
mc->irqs[i] = platform_get_irq(pdev, i);
if (mc->irqs[i] < 0)
return mc->irqs[i];
err = devm_request_irq(&pdev->dev, mc->irqs[i], meson_irq_handler, 0,
"gxl-crypto", mc);
if (err < 0)
return err;
}
err = clk_prepare_enable(mc->busclk);
if (err != 0) {
dev_err(&pdev->dev, "Cannot prepare_enable busclk\n");
dev_err(&pdev->dev, "Cannot get/enable core clock err=%d\n", err);
return err;
}
err = meson_allocate_chanlist(mc);
if (err)
goto error_flow;
return err;
for (i = 0; i < MAXFLOW; i++) {
mc->irqs[i] = platform_get_irq(pdev, i);
if (mc->irqs[i] < 0) {
err = mc->irqs[i];
goto error_chanlist;
}
err = devm_request_irq(&pdev->dev, mc->irqs[i], meson_irq_handler, 0,
"gxl-crypto", mc);
if (err < 0)
goto error_chanlist;
}
err = meson_register_algs(mc);
if (err)
@@ -289,9 +286,8 @@ static int meson_crypto_probe(struct platform_device *pdev)
return 0;
error_alg:
meson_unregister_algs(mc);
error_chanlist:
meson_free_chanlist(mc, MAXFLOW - 1);
error_flow:
clk_disable_unprepare(mc->busclk);
return err;
}
@@ -306,8 +302,6 @@ static void meson_crypto_remove(struct platform_device *pdev)
meson_unregister_algs(mc);
meson_free_chanlist(mc, MAXFLOW - 1);
clk_disable_unprepare(mc->busclk);
}
static const struct of_device_id meson_crypto_of_match_table[] = {
drivers/crypto/aspeed/aspeed-hace-crypto.c
+1 -2
View File
@@ -576,7 +576,6 @@ static int aspeed_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,
{
struct aspeed_cipher_ctx *ctx = crypto_skcipher_ctx(cipher);
struct aspeed_hace_dev *hace_dev = ctx->hace_dev;
struct crypto_aes_ctx gen_aes_key;
CIPHER_DBG(hace_dev, "keylen: %d bits\n", (keylen * 8));
@@ -585,9 +584,9 @@ static int aspeed_aes_setkey(struct crypto_skcipher *cipher, const u8 *key,
return -EINVAL;
if (ctx->hace_dev->version == AST2500_VERSION) {
struct crypto_aes_ctx gen_aes_key __cleanup(aes_zeroize_ctx);
aes_expandkey(&gen_aes_key, key, keylen);
memcpy(ctx->key, gen_aes_key.key_enc, AES_MAX_KEYLENGTH);
} else {
memcpy(ctx->key, key, keylen);
}
drivers/crypto/atmel-aes.c
+3 -1
View File
@@ -1267,7 +1267,7 @@ static int atmel_aes_gcm_ghash_init(struct atmel_aes_dev *dd)
struct atmel_aes_gcm_ctx *ctx = atmel_aes_gcm_ctx_cast(dd->ctx);
/* Set the data length. */
atmel_aes_write(dd, AES_AADLENR, dd->total);
atmel_aes_write(dd, AES_AADLENR, dd->datalen);
atmel_aes_write(dd, AES_CLENR, 0);
/* If needed, overwrite the GCM Intermediate Hash Word Registers */
@@ -1826,6 +1826,8 @@ static int atmel_aes_authenc_transfer(struct atmel_aes_dev *dd, int err,
dd->is_async = true;
if (err)
return atmel_aes_complete(dd, err);
if (!rctx->textlen)
return atmel_aes_authenc_digest(dd);
/* Prepare src and dst scatter-lists to transfer cipher/plain texts. */
src = scatterwalk_ffwd(rctx->src, req->src, req->assoclen);
drivers/crypto/atmel-ecc.c
+6 -6
View File
@@ -177,16 +177,14 @@ static int atmel_ecdh_compute_shared_secret(struct kpp_request *req)
work_data->client = ctx->client;
ret = atmel_i2c_init_ecdh_cmd(&work_data->cmd, req->src);
if (ret)
goto free_work_data;
if (ret) {
kfree(work_data);
return ret;
}
atmel_i2c_enqueue(work_data, atmel_ecdh_done, req);
return -EINPROGRESS;
free_work_data:
kfree(work_data);
return ret;
}
static struct i2c_client *atmel_ecc_i2c_client_alloc(void)
@@ -348,6 +346,7 @@ static void atmel_ecc_remove(struct i2c_client *client)
static const struct of_device_id atmel_ecc_dt_ids[] = {
{ .compatible = "atmel,atecc508a", },
{ .compatible = "atmel,atecc608a", },
{ .compatible = "atmel,atecc608b", },
{ }
};
@@ -355,6 +354,7 @@ MODULE_DEVICE_TABLE(of, atmel_ecc_dt_ids);
static const struct i2c_device_id atmel_ecc_id[] = {
{ .name = "atecc508a" },
{ .name = "atecc608a" },
{ .name = "atecc608b" },
{ }
};
drivers/crypto/atmel-sha.c
+19 -2
View File
@@ -422,6 +422,9 @@ static int atmel_sha_init(struct ahash_request *req)
struct atmel_sha_reqctx *ctx = ahash_request_ctx(req);
struct atmel_sha_dev *dd = atmel_sha_find_dev(tctx);
if (!dd)
return -ENODEV;
ctx->dd = dd;
ctx->flags = 0;
@@ -1203,7 +1206,7 @@ static int atmel_sha_finup(struct ahash_request *req)
/*
* final() has to be always called to cleanup resources
* even if udpate() failed, except EINPROGRESS
* even if update() failed, except EINPROGRESS
*/
err2 = atmel_sha_final(req);
@@ -1338,7 +1341,7 @@ static int atmel_sha_done(struct atmel_sha_dev *dd)
return err;
finish:
/* finish curent request */
/* finish current request */
atmel_sha_finish_req(dd->req, err);
return err;
@@ -2383,11 +2386,25 @@ static int atmel_sha_authenc_final_done(struct atmel_sha_dev *dd)
{
struct ahash_request *req = dd->req;
struct atmel_sha_authenc_reqctx *authctx = ahash_request_ctx(req);
atmel_aes_authenc_fn_t cb;
struct atmel_aes_dev *aes_dev;
size_t i, num_words = authctx->digestlen / sizeof(u32);
for (i = 0; i < num_words; ++i)
authctx->digest[i] = atmel_sha_read(dd, SHA_REG_DIGEST(i));
if (!dd->is_async) {
/*
* Return the AES finalizer's status directly for synchronous requests.
* The ahash callback cannot propagate it.
*/
cb = authctx->cb;
aes_dev = authctx->aes_dev;
dd->force_complete = false;
(void)atmel_sha_complete(dd, 0);
return cb(aes_dev, 0, false);
}
return atmel_sha_complete(dd, 0);
}
drivers/crypto/atmel-tdes.c
+43 -71
View File
@@ -308,45 +308,33 @@ static int atmel_tdes_crypt_pdc_stop(struct atmel_tdes_dev *dd)
static int atmel_tdes_buff_init(struct atmel_tdes_dev *dd)
{
int err = -ENOMEM;
dd->buf_in = (void *)__get_free_page(GFP_KERNEL);
dd->buf_out = (void *)__get_free_page(GFP_KERNEL);
dd->buflen = PAGE_SIZE;
dd->buflen &= ~(DES_BLOCK_SIZE - 1);
dd->buflen = PAGE_SIZE & ~(DES_BLOCK_SIZE - 1);
if (!dd->buf_in || !dd->buf_out) {
dev_dbg(dd->dev, "unable to alloc pages.\n");
dev_err(dd->dev, "failed to allocate DMA buffers\n");
goto err_alloc;
}
/* MAP here */
dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in,
dd->buflen, DMA_TO_DEVICE);
err = dma_mapping_error(dd->dev, dd->dma_addr_in);
if (err) {
dev_dbg(dd->dev, "dma %zd bytes error\n", dd->buflen);
goto err_map_in;
}
dd->dma_addr_in = dma_map_single(dd->dev, dd->buf_in, dd->buflen, DMA_TO_DEVICE);
if (dma_mapping_error(dd->dev, dd->dma_addr_in))
goto err_map;
dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out,
dd->buflen, DMA_FROM_DEVICE);
err = dma_mapping_error(dd->dev, dd->dma_addr_out);
if (err) {
dev_dbg(dd->dev, "dma %zd bytes error\n", dd->buflen);
goto err_map_out;
dd->dma_addr_out = dma_map_single(dd->dev, dd->buf_out, dd->buflen, DMA_FROM_DEVICE);
if (dma_mapping_error(dd->dev, dd->dma_addr_out)) {
dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen, DMA_TO_DEVICE);
goto err_map;
}
return 0;
err_map_out:
dma_unmap_single(dd->dev, dd->dma_addr_in, dd->buflen,
DMA_TO_DEVICE);
err_map_in:
err_map:
dev_err(dd->dev, "failed to map %zu bytes for DMA\n", dd->buflen);
err_alloc:
free_page((unsigned long)dd->buf_out);
free_page((unsigned long)dd->buf_in);
return err;
return -ENOMEM;
}
static void atmel_tdes_buff_cleanup(struct atmel_tdes_dev *dd)
@@ -361,18 +349,9 @@ static void atmel_tdes_buff_cleanup(struct atmel_tdes_dev *dd)
static int atmel_tdes_crypt_pdc(struct atmel_tdes_dev *dd,
dma_addr_t dma_addr_in,
dma_addr_t dma_addr_out, int length)
dma_addr_t dma_addr_out)
{
int len32;
dd->dma_size = length;
if (!(dd->flags & TDES_FLAGS_FAST)) {
dma_sync_single_for_device(dd->dev, dma_addr_in, length,
DMA_TO_DEVICE);
}
len32 = DIV_ROUND_UP(length, sizeof(u32));
u32 len32 = DIV_ROUND_UP(dd->dma_size, sizeof(u32));
atmel_tdes_write(dd, TDES_PTCR, TDES_PTCR_TXTDIS|TDES_PTCR_RXTDIS);
atmel_tdes_write(dd, TDES_TPR, dma_addr_in);
@@ -391,46 +370,34 @@ static int atmel_tdes_crypt_pdc(struct atmel_tdes_dev *dd,
static int atmel_tdes_crypt_dma(struct atmel_tdes_dev *dd,
dma_addr_t dma_addr_in,
dma_addr_t dma_addr_out, int length)
dma_addr_t dma_addr_out)
{
struct scatterlist sg[2];
struct dma_async_tx_descriptor *in_desc, *out_desc;
enum dma_slave_buswidth addr_width;
struct scatterlist sg_in, sg_out;
struct dma_async_tx_descriptor *in_desc, *out_desc;
dd->dma_size = length;
if (!(dd->flags & TDES_FLAGS_FAST)) {
dma_sync_single_for_device(dd->dev, dma_addr_in, length,
DMA_TO_DEVICE);
}
addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dd->dma_lch_in.dma_conf.dst_addr_width = addr_width;
dd->dma_lch_out.dma_conf.src_addr_width = addr_width;
dd->dma_lch_in.dma_conf.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dd->dma_lch_out.dma_conf.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
dmaengine_slave_config(dd->dma_lch_in.chan, &dd->dma_lch_in.dma_conf);
dmaengine_slave_config(dd->dma_lch_out.chan, &dd->dma_lch_out.dma_conf);
dd->flags |= TDES_FLAGS_DMA;
sg_init_table(&sg[0], 1);
sg_dma_address(&sg[0]) = dma_addr_in;
sg_dma_len(&sg[0]) = length;
sg_init_table(&sg_in, 1);
sg_dma_address(&sg_in) = dma_addr_in;
sg_dma_len(&sg_in) = dd->dma_size;
sg_init_table(&sg[1], 1);
sg_dma_address(&sg[1]) = dma_addr_out;
sg_dma_len(&sg[1]) = length;
sg_init_table(&sg_out, 1);
sg_dma_address(&sg_out) = dma_addr_out;
sg_dma_len(&sg_out) = dd->dma_size;
in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, &sg[0],
1, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
in_desc = dmaengine_prep_slave_sg(dd->dma_lch_in.chan, &sg_in, 1, DMA_MEM_TO_DEV,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!in_desc)
return -EINVAL;
out_desc = dmaengine_prep_slave_sg(dd->dma_lch_out.chan, &sg[1],
1, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
out_desc = dmaengine_prep_slave_sg(dd->dma_lch_out.chan, &sg_out, 1, DMA_DEV_TO_MEM,
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
if (!out_desc)
return -EINVAL;
@@ -494,13 +461,19 @@ static int atmel_tdes_crypt_start(struct atmel_tdes_dev *dd)
}
dd->total -= count;
dd->dma_size = count;
if (!fast) {
dma_sync_single_for_device(dd->dev, addr_in, dd->dma_size, DMA_TO_DEVICE);
dma_sync_single_for_device(dd->dev, addr_out, dd->dma_size, DMA_FROM_DEVICE);
}
if (dd->caps.has_dma)
err = atmel_tdes_crypt_dma(dd, addr_in, addr_out, count);
err = atmel_tdes_crypt_dma(dd, addr_in, addr_out);
else
err = atmel_tdes_crypt_pdc(dd, addr_in, addr_out, count);
err = atmel_tdes_crypt_pdc(dd, addr_in, addr_out);
if (err && (dd->flags & TDES_FLAGS_FAST)) {
if (err && fast) {
dma_unmap_sg(dd->dev, dd->in_sg, 1, DMA_TO_DEVICE);
dma_unmap_sg(dd->dev, dd->out_sg, 1, DMA_FROM_DEVICE);
}
@@ -660,7 +633,7 @@ static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd)
dd->dma_lch_in.chan = dma_request_chan(dd->dev, "tx");
if (IS_ERR(dd->dma_lch_in.chan)) {
ret = PTR_ERR(dd->dma_lch_in.chan);
goto err_dma_in;
goto err_dma;
}
dd->dma_lch_in.dma_conf.dst_addr = dd->phys_base +
@@ -676,7 +649,8 @@ static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd)
dd->dma_lch_out.chan = dma_request_chan(dd->dev, "rx");
if (IS_ERR(dd->dma_lch_out.chan)) {
ret = PTR_ERR(dd->dma_lch_out.chan);
goto err_dma_out;
dma_release_channel(dd->dma_lch_in.chan);
goto err_dma;
}
dd->dma_lch_out.dma_conf.src_addr = dd->phys_base +
@@ -691,9 +665,7 @@ static int atmel_tdes_dma_init(struct atmel_tdes_dev *dd)
return 0;
err_dma_out:
dma_release_channel(dd->dma_lch_in.chan);
err_dma_in:
err_dma:
dev_err(dd->dev, "no DMA channel available\n");
return ret;
}
@@ -933,7 +905,7 @@ static int atmel_tdes_probe(struct platform_device *pdev)
struct resource *tdes_res;
int err;
tdes_dd = devm_kmalloc(&pdev->dev, sizeof(*tdes_dd), GFP_KERNEL);
tdes_dd = devm_kzalloc(&pdev->dev, sizeof(*tdes_dd), GFP_KERNEL);
if (!tdes_dd)
return -ENOMEM;
drivers/crypto/caam/caamalg_qi.c
+2
View File
@@ -637,6 +637,8 @@ static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
ctx->cdata.keylen = keylen;
ctx->cdata.key_virt = key;
ctx->cdata.key_inline = true;
ctx->cdata.plain_keylen = keylen;
ctx->cdata.key_cmd_opt = 0;
/* skcipher encrypt, decrypt shared descriptors */
cnstr_shdsc_skcipher_encap(ctx->sh_desc_enc, &ctx->cdata, ivsize,
drivers/crypto/caam/caamalg_qi2.c
+16 -3
View File
@@ -26,7 +26,7 @@
#include <crypto/xts.h>
#include <linux/unaligned.h>
#define CAAM_CRA_PRIORITY 2000
#define CAAM_CRA_PRIORITY 100
/* max key is sum of AES_MAX_KEY_SIZE, max split key size */
#define CAAM_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + CTR_RFC3686_NONCE_SIZE + \
@@ -961,6 +961,8 @@ static int skcipher_setkey(struct crypto_skcipher *skcipher, const u8 *key,
ctx->cdata.keylen = keylen;
ctx->cdata.key_virt = key;
ctx->cdata.key_inline = true;
ctx->cdata.plain_keylen = keylen;
ctx->cdata.key_cmd_opt = 0;
/* skcipher_encrypt shared descriptor */
flc = &ctx->flc[ENCRYPT];
@@ -5041,11 +5043,22 @@ static int __cold dpaa2_dpseci_setup(struct fsl_mc_device *ls_dev)
dev_info(dev, "dpseci v%d.%d\n", priv->major_ver, priv->minor_ver);
if (DPSECI_VER(priv->major_ver, priv->minor_ver) > DPSECI_VER(5, 3)) {
err = dpseci_reset(priv->mc_io, 0, ls_dev->mc_handle);
int enabled;
err = dpseci_is_enabled(priv->mc_io, 0, ls_dev->mc_handle,
&enabled);
if (err) {
dev_err(dev, "dpseci_reset() failed\n");
dev_err(dev, "dpseci_is_enabled() failed\n");
goto err_get_vers;
}
if (enabled) {
err = dpseci_reset(priv->mc_io, 0, ls_dev->mc_handle);
if (err) {
dev_err(dev, "dpseci_reset() failed\n");
goto err_get_vers;
}
}
}
err = dpseci_get_attributes(priv->mc_io, 0, ls_dev->mc_handle,
drivers/crypto/caam/caampkc.c
+6
View File
@@ -1033,16 +1033,22 @@ static int caam_rsa_set_priv_key_form(struct caam_rsa_ctx *ctx,
free_dq:
kfree_sensitive(rsa_key->dq);
rsa_key->dq = NULL;
free_dp:
kfree_sensitive(rsa_key->dp);
rsa_key->dp = NULL;
free_tmp2:
kfree_sensitive(rsa_key->tmp2);
rsa_key->tmp2 = NULL;
free_tmp1:
kfree_sensitive(rsa_key->tmp1);
rsa_key->tmp1 = NULL;
free_q:
kfree_sensitive(rsa_key->q);
rsa_key->q = NULL;
free_p:
kfree_sensitive(rsa_key->p);
rsa_key->p = NULL;
return -ENOMEM;
}
drivers/crypto/cavium/cpt/cptpf_main.c
+6 -6
View File
@@ -90,19 +90,19 @@ static void cpt_configure_group(struct cpt_device *cpt, u8 grp,
static void cpt_disable_mbox_interrupts(struct cpt_device *cpt)
{
/* Clear mbox(0) interupts for all vfs */
/* Clear mbox(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1CX(0, 0), ~0ull);
}
static void cpt_disable_ecc_interrupts(struct cpt_device *cpt)
{
/* Clear ecc(0) interupts for all vfs */
/* Clear ecc(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_ECC0_ENA_W1C(0), ~0ull);
}
static void cpt_disable_exec_interrupts(struct cpt_device *cpt)
{
/* Clear exec interupts for all vfs */
/* Clear exec interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_EXEC_ENA_W1C(0), ~0ull);
}
@@ -115,7 +115,7 @@ static void cpt_disable_all_interrupts(struct cpt_device *cpt)
static void cpt_enable_mbox_interrupts(struct cpt_device *cpt)
{
/* Set mbox(0) interupts for all vfs */
/* Set mbox(0) interrupts for all vfs */
cpt_write_csr64(cpt->reg_base, CPTX_PF_MBOX_ENA_W1SX(0, 0), ~0ull);
}
@@ -140,10 +140,10 @@ static int cpt_load_microcode(struct cpt_device *cpt, struct microcode *mcode)
*/
if (mcode->is_ae) {
core = CPT_MAX_SE_CORES; /* start couting from 10 */
total_cores = CPT_MAX_TOTAL_CORES; /* upto 15 */
total_cores = CPT_MAX_TOTAL_CORES; /* up to 15 */
} else {
core = 0; /* start couting from 0 */
total_cores = CPT_MAX_SE_CORES; /* upto 9 */
total_cores = CPT_MAX_SE_CORES; /* up to 9 */
}
/* Point to microcode for each core of the group */
drivers/crypto/cavium/cpt/cptvf_main.c
+2 -2
View File
@@ -417,7 +417,7 @@ static void cptvf_enable_swerr_interrupts(struct cpt_vf *cptvf)
vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,
CPTX_VQX_MISC_ENA_W1S(0, 0));
/* Set mbox(0) interupts for the requested vf */
/* Set mbox(0) interrupts for the requested vf */
vqx_misc_ena.s.swerr = 1;
cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),
vqx_misc_ena.u);
@@ -429,7 +429,7 @@ static void cptvf_enable_mbox_interrupts(struct cpt_vf *cptvf)
vqx_misc_ena.u = cpt_read_csr64(cptvf->reg_base,
CPTX_VQX_MISC_ENA_W1S(0, 0));
/* Set mbox(0) interupts for the requested vf */
/* Set mbox(0) interrupts for the requested vf */
vqx_misc_ena.s.mbox = 1;
cpt_write_csr64(cptvf->reg_base, CPTX_VQX_MISC_ENA_W1S(0, 0),
vqx_misc_ena.u);
drivers/crypto/cavium/cpt/cptvf_mbox.c
+2 -2
View File
@@ -120,7 +120,7 @@ int cptvf_send_vq_size_msg(struct cpt_vf *cptvf)
}
/*
* Communicate VF group required to PF and get the VQ binded to that group
* Communicate VF group required to PF and get the VQ bound to that group
*/
int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf)
{
@@ -139,7 +139,7 @@ int cptvf_send_vf_to_grp_msg(struct cpt_vf *cptvf)
}
/*
* Communicate VF group required to PF and get the VQ binded to that group
* Communicate VF group required to PF and get the VQ bound to that group
*/
int cptvf_send_vf_priority_msg(struct cpt_vf *cptvf)
{
drivers/crypto/cavium/nitrox/nitrox_main.c
+1 -1
View File
@@ -468,7 +468,7 @@ static int nitrox_probe(struct pci_dev *pdev,
err = -EIO;
goto ioremap_err;
}
/* allocate command queus based on cpus, max queues are 64 */
/* allocate command queues based on cpus, max queues are 64 */
ndev->nr_queues = min_t(u32, MAX_PF_QUEUES, num_online_cpus());
ndev->qlen = qlen;
drivers/crypto/ccp/ccp-dev-v3.c
+4
View File
@@ -506,6 +506,8 @@ e_kthread:
kthread_stop(ccp->cmd_q[i].kthread);
sp_free_ccp_irq(ccp->sp, ccp);
if (ccp->use_tasklet)
tasklet_kill(&ccp->irq_tasklet);
e_pool:
for (i = 0; i < ccp->cmd_q_count; i++)
@@ -545,6 +547,8 @@ static void ccp_destroy(struct ccp_device *ccp)
kthread_stop(ccp->cmd_q[i].kthread);
sp_free_ccp_irq(ccp->sp, ccp);
if (ccp->use_tasklet)
tasklet_kill(&ccp->irq_tasklet);
for (i = 0; i < ccp->cmd_q_count; i++)
dma_pool_destroy(ccp->cmd_q[i].dma_pool);
drivers/crypto/ccp/ccp-dev-v5.c
+4
View File
@@ -995,6 +995,8 @@ e_kthread:
e_irq:
sp_free_ccp_irq(ccp->sp, ccp);
if (ccp->use_tasklet)
tasklet_kill(&ccp->irq_tasklet);
e_pool:
for (i = 0; i < ccp->cmd_q_count; i++)
@@ -1046,6 +1048,8 @@ static void ccp5_destroy(struct ccp_device *ccp)
kthread_stop(ccp->cmd_q[i].kthread);
sp_free_ccp_irq(ccp->sp, ccp);
if (ccp->use_tasklet)
tasklet_kill(&ccp->irq_tasklet);
/* Flush the cmd and backlog queue */
while (!list_empty(&ccp->cmd)) {
drivers/crypto/ccp/ccp-dev.c
+1 -1
View File
@@ -30,7 +30,7 @@
#define MAX_CCPS 32
/* Limit CCP use to a specifed number of queues per device */
/* Limit CCP use to a specified number of queues per device */
static unsigned int nqueues;
module_param(nqueues, uint, 0444);
MODULE_PARM_DESC(nqueues, "Number of queues per CCP (minimum 1; default: all available)");
drivers/crypto/ccp/dbc.c
+2 -2
View File
@@ -236,6 +236,8 @@ int dbc_dev_init(struct psp_device *psp)
goto cleanup_mbox;
}
mutex_init(&dbc_dev->ioctl_mutex);
dbc_dev->char_dev.minor = MISC_DYNAMIC_MINOR;
dbc_dev->char_dev.name = "dbc";
dbc_dev->char_dev.fops = &dbc_fops;
@@ -244,8 +246,6 @@ int dbc_dev_init(struct psp_device *psp)
if (ret)
goto cleanup_mbox;
mutex_init(&dbc_dev->ioctl_mutex);
return 0;
cleanup_mbox:
drivers/crypto/ccp/sfs.c
+6 -3
View File
@@ -111,13 +111,13 @@ static long sfs_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
struct sfs_device *sfs_dev;
int ret = 0;
guard(mutex)(&sfs_ioctl_mutex);
if (!psp_master || !psp_master->sfs_data)
return -ENODEV;
sfs_dev = psp_master->sfs_data;
guard(mutex)(&sfs_ioctl_mutex);
switch (cmd) {
case SFSIOCFWVERS:
dev_dbg(sfs_dev->dev, "in SFSIOCFWVERS\n");
@@ -191,8 +191,11 @@ static void sfs_exit(struct kref *ref)
void sfs_dev_destroy(struct psp_device *psp)
{
struct sfs_device *sfs_dev = psp->sfs_data;
struct sfs_device *sfs_dev;
guard(mutex)(&sfs_ioctl_mutex);
sfs_dev = psp->sfs_data;
if (!sfs_dev)
return;
drivers/crypto/ccp/sp-platform.c
+2 -2
View File
@@ -40,8 +40,8 @@ static const struct sp_dev_vdata dev_vdata[] = {
};
static const struct acpi_device_id sp_acpi_match[] = {
{ "AMDI0C00", (kernel_ulong_t)&dev_vdata[0] },
{ },
{ .id = "AMDI0C00", .driver_data = (kernel_ulong_t)&dev_vdata[0] },
{ }
};
MODULE_DEVICE_TABLE(acpi, sp_acpi_match);
drivers/crypto/ccree/cc_aead.c
+2 -2
View File
@@ -226,8 +226,8 @@ static void cc_aead_complete(struct device *dev, void *cc_req, int err)
goto done;
if (areq_ctx->gen_ctx.op_type == DRV_CRYPTO_DIRECTION_DECRYPT) {
if (memcmp(areq_ctx->mac_buf, areq_ctx->icv_virt_addr,
ctx->authsize) != 0) {
if (crypto_memneq(areq_ctx->mac_buf, areq_ctx->icv_virt_addr,
ctx->authsize)) {
dev_dbg(dev, "Payload authentication failure, (auth-size=%d, cipher=%d)\n",
ctx->authsize, ctx->cipher_mode);
/* In case of payload authentication failure, MUST NOT
drivers/crypto/ccree/cc_buffer_mgr.c
+2 -2
View File
@@ -717,7 +717,7 @@ static void cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata,
}
} else { /* Contig. ICV */
sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
/*Should hanlde if the sg is not contig.*/
/*Should handle if the sg is not contig.*/
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
(*src_last_bytes - authsize);
areq_ctx->icv_virt_addr = sg_virt(sg) +
@@ -749,7 +749,7 @@ static void cc_prepare_aead_data_mlli(struct cc_drvdata *drvdata,
} else { /* Contig. ICV */
sg = &areq_ctx->src_sgl[areq_ctx->src.nents - 1];
/*Should hanlde if the sg is not contig.*/
/*Should handle if the sg is not contig.*/
areq_ctx->icv_dma_addr = sg_dma_address(sg) +
(*src_last_bytes - authsize);
areq_ctx->icv_virt_addr = sg_virt(sg) +
drivers/crypto/ccree/cc_pm.c
+1 -7
View File
@@ -66,13 +66,7 @@ const struct dev_pm_ops ccree_pm = {
int cc_pm_get(struct device *dev)
{
int rc = pm_runtime_get_sync(dev);
if (rc < 0) {
pm_runtime_put_noidle(dev);
return rc;
}
return 0;
return pm_runtime_resume_and_get(dev);
}
void cc_pm_put_suspend(struct device *dev)
drivers/crypto/chelsio/chcr_algo.c
+1 -1
View File
@@ -1605,7 +1605,7 @@ static struct sk_buff *create_hash_wr(struct ahash_request *req,
req_ctx->hctx_wr.dma_addr = 0;
}
chcr_add_hash_src_ent(req, ulptx, param);
/* Request upto max wr size */
/* Request up to max wr size */
temp = param->kctx_len + DUMMY_BYTES + (req_ctx->hctx_wr.imm ?
(param->sg_len + param->bfr_len) : 0);
atomic_inc(&adap->chcr_stats.digest_rqst);
drivers/crypto/gemini/sl3516-ce-cipher.c
+1 -2
View File
@@ -331,13 +331,12 @@ int sl3516_ce_cipher_init(struct crypto_tfm *tfm)
crypto_tfm_alg_driver_name(&sktfm->base),
crypto_tfm_alg_driver_name(crypto_skcipher_tfm(op->fallback_tfm)));
err = pm_runtime_get_sync(op->ce->dev);
err = pm_runtime_resume_and_get(op->ce->dev);
if (err < 0)
goto error_pm;
return 0;
error_pm:
pm_runtime_put_noidle(op->ce->dev);
crypto_free_skcipher(op->fallback_tfm);
return err;
}
drivers/crypto/gemini/sl3516-ce-rng.c
+2 -4
View File
@@ -24,11 +24,9 @@ static int sl3516_ce_rng_read(struct hwrng *rng, void *buf, size_t max, bool wai
ce->hwrng_stat_bytes += max;
#endif
err = pm_runtime_get_sync(ce->dev);
if (err < 0) {
pm_runtime_put_noidle(ce->dev);
err = pm_runtime_resume_and_get(ce->dev);
if (err < 0)
return err;
}
while (read < max) {
*data = readl(ce->base + IPSEC_RAND_NUM_REG);
drivers/crypto/hisilicon/Kconfig
-14
View File
@@ -1,19 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
config CRYPTO_DEV_HISI_SEC
tristate "Support for Hisilicon SEC crypto block cipher accelerator"
select CRYPTO_SKCIPHER
select CRYPTO_ALGAPI
select CRYPTO_LIB_DES
select SG_SPLIT
depends on ARM64 || COMPILE_TEST
depends on HAS_IOMEM
help
Support for Hisilicon SEC Engine in Hip06 and Hip07
To compile this as a module, choose M here: the module
will be called hisi_sec.
config CRYPTO_DEV_HISI_SEC2
tristate "Support for HiSilicon SEC2 crypto block cipher accelerator"
select CRYPTO_SKCIPHER
drivers/crypto/hisilicon/Makefile
-1
View File
@@ -1,6 +1,5 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CRYPTO_DEV_HISI_HPRE) += hpre/
obj-$(CONFIG_CRYPTO_DEV_HISI_SEC) += sec/
obj-$(CONFIG_CRYPTO_DEV_HISI_SEC2) += sec2/
obj-$(CONFIG_CRYPTO_DEV_HISI_QM) += hisi_qm.o
hisi_qm-objs = qm.o sgl.o debugfs.o
drivers/crypto/hisilicon/hpre/hpre.h
-1
View File
@@ -70,7 +70,6 @@ struct hpre_debug {
struct hpre {
struct hisi_qm qm;
struct hpre_debug debug;
unsigned long status;
};
enum hpre_alg_type {
drivers/crypto/hisilicon/hpre/hpre_crypto.c
+13 -15
View File
@@ -21,19 +21,15 @@ struct hpre_ctx;
#define HPRE_CRYPTO_ALG_PRI 1000
#define HPRE_ALIGN_SZ 64
#define HPRE_BITS_2_BYTES_SHIFT 3
#define HPRE_RSA_512BITS_KSZ 64
#define HPRE_RSA_1536BITS_KSZ 192
#define HPRE_CRT_PRMS 5
#define HPRE_CRT_Q 2
#define HPRE_CRT_P 3
#define HPRE_CRT_INV 4
#define HPRE_DH_G_FLAG 0x02
#define HPRE_TRY_SEND_TIMES 100
#define HPRE_INVLD_REQ_ID (-1)
#define HPRE_SQE_ALG_BITS 5
#define HPRE_SQE_DONE_SHIFT 30
#define HPRE_DH_MAX_P_SZ 512
#define HPRE_DFX_SEC_TO_US 1000000
#define HPRE_DFX_US_TO_NS 1000
@@ -56,7 +52,6 @@ struct hpre_ctx;
#define HPRE_DRV_RSA_MASK_CAP BIT(0)
#define HPRE_DRV_DH_MASK_CAP BIT(1)
#define HPRE_DRV_ECDH_MASK_CAP BIT(2)
#define HPRE_DRV_X25519_MASK_CAP BIT(5)
static DEFINE_MUTEX(hpre_algs_lock);
static unsigned int hpre_available_devs;
@@ -135,9 +130,9 @@ struct hpre_asym_request {
struct kpp_request *dh;
struct kpp_request *ecdh;
} areq;
int err;
hpre_cb cb;
struct timespec64 req_time;
u32 flags;
};
static inline unsigned int hpre_align_sz(void)
@@ -186,6 +181,7 @@ static int hpre_prepare_dma_buf(struct hpre_asym_request *hpre_req,
struct scatterlist *data, unsigned int len,
int is_src, dma_addr_t *tmp)
{
gfp_t gfp = hpre_req->flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : GFP_ATOMIC;
struct hpre_ctx *ctx = hpre_req->ctx;
struct device *dev = ctx->dev;
void *ptr;
@@ -195,7 +191,7 @@ static int hpre_prepare_dma_buf(struct hpre_asym_request *hpre_req,
if (unlikely(shift < 0))
return -EINVAL;
ptr = dma_alloc_coherent(dev, ctx->key_sz, tmp, GFP_ATOMIC);
ptr = dma_alloc_coherent(dev, ctx->key_sz, tmp, gfp);
if (unlikely(!ptr))
return -ENOMEM;
@@ -419,6 +415,7 @@ static int hpre_msg_request_set(struct hpre_ctx *ctx, void *req, bool is_rsa)
h_req = PTR_ALIGN(tmp, hpre_align_sz());
h_req->cb = hpre_rsa_cb;
h_req->areq.rsa = akreq;
h_req->flags = akreq->base.flags;
msg = &h_req->req;
memset(msg, 0, sizeof(*msg));
} else {
@@ -433,6 +430,7 @@ static int hpre_msg_request_set(struct hpre_ctx *ctx, void *req, bool is_rsa)
h_req = PTR_ALIGN(tmp, hpre_align_sz());
h_req->cb = hpre_dh_cb;
h_req->areq.dh = kreq;
h_req->flags = kreq->base.flags;
msg = &h_req->req;
memset(msg, 0, sizeof(*msg));
msg->key = cpu_to_le64(ctx->dh.dma_xa_p);
@@ -720,7 +718,7 @@ static void hpre_dh_exit_tfm(struct crypto_kpp *tfm)
static void hpre_rsa_drop_leading_zeros(const char **ptr, size_t *len)
{
while (!**ptr && *len) {
while (*len && !**ptr) {
(*ptr)++;
(*len)--;
}
@@ -1407,8 +1405,6 @@ static void hpre_ecdh_hw_data_clr_all(struct hpre_ctx *ctx,
if (unlikely(dma_mapping_error(dev, dma)))
return;
if (req->dst)
dma_free_coherent(dev, ctx->key_sz << 1, req->dst, dma);
if (dst)
dma_unmap_single(dev, dma, ctx->key_sz << 1, DMA_FROM_DEVICE);
}
@@ -1452,13 +1448,14 @@ static int hpre_ecdh_msg_request_set(struct hpre_ctx *ctx,
if (req->dst_len < ctx->key_sz << 1) {
req->dst_len = ctx->key_sz << 1;
return -EINVAL;
return -EOVERFLOW;
}
tmp = kpp_request_ctx(req);
h_req = PTR_ALIGN(tmp, hpre_align_sz());
h_req->cb = hpre_ecdh_cb;
h_req->areq.ecdh = req;
h_req->flags = req->base.flags;
msg = &h_req->req;
memset(msg, 0, sizeof(*msg));
msg->in = cpu_to_le64(DMA_MAPPING_ERROR);
@@ -1477,6 +1474,7 @@ static int hpre_ecdh_msg_request_set(struct hpre_ctx *ctx,
static int hpre_ecdh_src_data_init(struct hpre_asym_request *hpre_req,
struct scatterlist *data, unsigned int len)
{
gfp_t gfp = hpre_req->flags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL : GFP_ATOMIC;
struct hpre_sqe *msg = &hpre_req->req;
struct hpre_ctx *ctx = hpre_req->ctx;
struct device *dev = ctx->dev;
@@ -1490,7 +1488,7 @@ static int hpre_ecdh_src_data_init(struct hpre_asym_request *hpre_req,
if (unlikely(shift < 0))
return -EINVAL;
ptr = dma_alloc_coherent(dev, ctx->key_sz << 2, &dma, GFP_KERNEL);
ptr = dma_alloc_coherent(dev, ctx->key_sz << 2, &dma, gfp);
if (unlikely(!ptr))
return -ENOMEM;
@@ -1512,13 +1510,13 @@ static int hpre_ecdh_dst_data_init(struct hpre_asym_request *hpre_req,
struct device *dev = ctx->dev;
dma_addr_t dma;
if (unlikely(!data || !sg_is_last(data) || len != ctx->key_sz << 1)) {
dev_err(dev, "data or data length is illegal!\n");
if (unlikely(!data || !sg_is_last(data))) {
dev_err(dev, "data is illegal!\n");
return -EINVAL;
}
hpre_req->dst = NULL;
dma = dma_map_single(dev, sg_virt(data), len, DMA_FROM_DEVICE);
dma = dma_map_single(dev, sg_virt(data), ctx->key_sz << 1, DMA_FROM_DEVICE);
if (unlikely(dma_mapping_error(dev, dma))) {
dev_err(dev, "dma map data err!\n");
return -ENOMEM;
drivers/crypto/hisilicon/hpre/hpre_main.c
+16 -33
View File
@@ -16,7 +16,6 @@
#define CAP_FILE_PERMISSION 0444
#define HPRE_CTRL_CNT_CLR_CE_BIT BIT(0)
#define HPRE_CTRL_CNT_CLR_CE 0x301000
#define HPRE_FSM_MAX_CNT 0x301008
#define HPRE_VFG_AXQOS 0x30100c
#define HPRE_VFG_AXCACHE 0x301010
#define HPRE_RDCHN_INI_CFG 0x301014
@@ -41,7 +40,6 @@
#define HPRE_HAC_INT_SET 0x301500
#define HPRE_AXI_ERROR_MASK GENMASK(21, 10)
#define HPRE_RNG_TIMEOUT_NUM 0x301A34
#define HPRE_CORE_INT_ENABLE 0
#define HPRE_RDCHN_INI_ST 0x301a00
#define HPRE_CLSTR_BASE 0x302000
#define HPRE_CORE_EN_OFFSET 0x04
@@ -61,8 +59,6 @@
#define HPRE_CORE_ENB (HPRE_CLSTR_BASE + HPRE_CORE_EN_OFFSET)
#define HPRE_CORE_INI_CFG (HPRE_CLSTR_BASE + HPRE_CORE_INI_CFG_OFFSET)
#define HPRE_CORE_INI_STATUS (HPRE_CLSTR_BASE + HPRE_CORE_INI_STATUS_OFFSET)
#define HPRE_HAC_ECC1_CNT 0x301a04
#define HPRE_HAC_ECC2_CNT 0x301a08
#define HPRE_HAC_SOURCE_INT 0x301600
#define HPRE_CLSTR_ADDR_INTRVL 0x1000
#define HPRE_CLUSTER_INQURY 0x100
@@ -381,6 +377,14 @@ static const char *hpre_channel_name[HPRE_MAX_CHANNEL_NUM] = {
static const struct hisi_qm_err_ini hpre_err_ini;
static inline u8 hpre_get_clusters_num(struct hisi_qm *qm)
{
u32 cap = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
return (cap >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
}
bool hpre_check_alg_support(struct hisi_qm *qm, u32 alg)
{
u32 cap_val;
@@ -557,15 +561,12 @@ static int hpre_set_cluster(struct hisi_qm *qm)
struct device *dev = &qm->pdev->dev;
u32 cluster_core_mask;
unsigned long offset;
u32 hpre_core_info;
u8 clusters_num;
u32 val = 0;
int ret, i;
cluster_core_mask = qm->cap_tables.dev_cap_table[HPRE_CORE_EN].cap_val;
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
clusters_num = hpre_get_clusters_num(qm);
for (i = 0; i < clusters_num; i++) {
offset = i * HPRE_CLSTR_ADDR_INTRVL;
@@ -659,7 +660,6 @@ static void hpre_enable_clock_gate(struct hisi_qm *qm)
{
unsigned long offset;
u8 clusters_num, i;
u32 hpre_core_info;
u32 val;
if (qm->ver < QM_HW_V3)
@@ -673,9 +673,7 @@ static void hpre_enable_clock_gate(struct hisi_qm *qm)
val |= HPRE_PEH_CFG_AUTO_GATE_EN;
writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
clusters_num = hpre_get_clusters_num(qm);
for (i = 0; i < clusters_num; i++) {
offset = (unsigned long)i * HPRE_CLSTR_ADDR_INTRVL;
val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
@@ -692,7 +690,6 @@ static void hpre_disable_clock_gate(struct hisi_qm *qm)
{
unsigned long offset;
u8 clusters_num, i;
u32 hpre_core_info;
u32 val;
if (qm->ver < QM_HW_V3)
@@ -706,9 +703,7 @@ static void hpre_disable_clock_gate(struct hisi_qm *qm)
val &= ~HPRE_PEH_CFG_AUTO_GATE_EN;
writel(val, qm->io_base + HPRE_PEH_CFG_AUTO_GATE);
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
clusters_num = hpre_get_clusters_num(qm);
for (i = 0; i < clusters_num; i++) {
offset = (unsigned long)i * HPRE_CLSTR_ADDR_INTRVL;
val = readl(qm->io_base + offset + HPRE_CLUSTER_DYN_CTL);
@@ -782,14 +777,11 @@ static int hpre_set_user_domain_and_cache(struct hisi_qm *qm)
static void hpre_cnt_regs_clear(struct hisi_qm *qm)
{
unsigned long offset;
u32 hpre_core_info;
u8 clusters_num;
int i;
/* clear clusterX/cluster_ctrl */
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
clusters_num = hpre_get_clusters_num(qm);
for (i = 0; i < clusters_num; i++) {
offset = HPRE_CLSTR_BASE + i * HPRE_CLSTR_ADDR_INTRVL;
writel(0x0, qm->io_base + offset + HPRE_CLUSTER_INQURY);
@@ -1072,13 +1064,10 @@ static int hpre_cluster_debugfs_init(struct hisi_qm *qm)
char buf[HPRE_DBGFS_VAL_MAX_LEN];
struct debugfs_regset32 *regset;
struct dentry *tmp_d;
u32 hpre_core_info;
u8 clusters_num;
int i, ret;
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
clusters_num = hpre_get_clusters_num(qm);
for (i = 0; i < clusters_num; i++) {
ret = snprintf(buf, HPRE_DBGFS_VAL_MAX_LEN, "cluster%d", i);
if (ret >= HPRE_DBGFS_VAL_MAX_LEN)
@@ -1234,8 +1223,8 @@ static int hpre_pre_store_cap_reg(struct hisi_qm *qm)
return -EINVAL;
}
qm->cap_tables.dev_cap_table = hpre_cap;
qm->cap_tables.dev_cap_size = size;
qm->cap_tables.dev_cap_table = hpre_cap;
return 0;
}
@@ -1308,13 +1297,10 @@ static int hpre_show_last_regs_init(struct hisi_qm *qm)
int com_dfx_regs_num = ARRAY_SIZE(hpre_com_dfx_regs);
struct qm_debug *debug = &qm->debug;
void __iomem *io_base;
u32 hpre_core_info;
u8 clusters_num;
int i, j, idx;
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
clusters_num = hpre_get_clusters_num(qm);
debug->last_words = kcalloc(cluster_dfx_regs_num * clusters_num +
com_dfx_regs_num, sizeof(unsigned int), GFP_KERNEL);
if (!debug->last_words)
@@ -1354,7 +1340,6 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
struct qm_debug *debug = &qm->debug;
struct pci_dev *pdev = qm->pdev;
void __iomem *io_base;
u32 hpre_core_info;
u8 clusters_num;
int i, j, idx;
u32 val;
@@ -1370,9 +1355,7 @@ static void hpre_show_last_dfx_regs(struct hisi_qm *qm)
hpre_com_dfx_regs[i].name, debug->last_words[i], val);
}
hpre_core_info = qm->cap_tables.dev_cap_table[HPRE_CORE_INFO].cap_val;
clusters_num = (hpre_core_info >> hpre_basic_info[HPRE_CLUSTER_NUM_CAP].shift) &
hpre_basic_info[HPRE_CLUSTER_NUM_CAP].mask;
clusters_num = hpre_get_clusters_num(qm);
for (i = 0; i < clusters_num; i++) {
io_base = qm->io_base + hpre_cluster_offsets[i];
for (j = 0; j < cluster_dfx_regs_num; j++) {
drivers/crypto/hisilicon/qm.c
+1 -1
View File
@@ -5743,8 +5743,8 @@ static int qm_pre_store_caps(struct hisi_qm *qm)
i, qm->cap_ver);
}
qm->cap_tables.qm_cap_table = qm_cap;
qm->cap_tables.qm_cap_size = size;
qm->cap_tables.qm_cap_table = qm_cap;
return 0;
}
drivers/crypto/hisilicon/sec/Makefile
-3
View File
@@ -1,3 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
obj-$(CONFIG_CRYPTO_DEV_HISI_SEC) += hisi_sec.o
hisi_sec-y = sec_algs.o sec_drv.o
drivers/crypto/hisilicon/sec/sec_algs.c
-1122
View File
File diff suppressed because it is too large. Load diff
drivers/crypto/hisilicon/sec/sec_drv.c
-1307
View File
File diff suppressed because it is too large. Load diff
drivers/crypto/hisilicon/sec/sec_drv.h
-428
View File
@@ -1,428 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2016-2017 HiSilicon Limited. */
#ifndef _SEC_DRV_H_
#define _SEC_DRV_H_
#include <crypto/algapi.h>
#include <linux/kfifo.h>
#define SEC_MAX_SGE_NUM 64
#define SEC_HW_RING_NUM 3
#define SEC_CMD_RING 0
#define SEC_OUTORDER_RING 1
#define SEC_DBG_RING 2
/* A reasonable length to balance memory use against flexibility */
#define SEC_QUEUE_LEN 512
#define SEC_MAX_SGE_NUM 64
struct sec_bd_info {
#define SEC_BD_W0_T_LEN_M GENMASK(4, 0)
#define SEC_BD_W0_T_LEN_S 0
#define SEC_BD_W0_C_WIDTH_M GENMASK(6, 5)
#define SEC_BD_W0_C_WIDTH_S 5
#define SEC_C_WIDTH_AES_128BIT 0
#define SEC_C_WIDTH_AES_8BIT 1
#define SEC_C_WIDTH_AES_1BIT 2
#define SEC_C_WIDTH_DES_64BIT 0
#define SEC_C_WIDTH_DES_8BIT 1
#define SEC_C_WIDTH_DES_1BIT 2
#define SEC_BD_W0_C_MODE_M GENMASK(9, 7)
#define SEC_BD_W0_C_MODE_S 7
#define SEC_C_MODE_ECB 0
#define SEC_C_MODE_CBC 1
#define SEC_C_MODE_CTR 4
#define SEC_C_MODE_CCM 5
#define SEC_C_MODE_GCM 6
#define SEC_C_MODE_XTS 7
#define SEC_BD_W0_SEQ BIT(10)
#define SEC_BD_W0_DE BIT(11)
#define SEC_BD_W0_DAT_SKIP_M GENMASK(13, 12)
#define SEC_BD_W0_DAT_SKIP_S 12
#define SEC_BD_W0_C_GRAN_SIZE_19_16_M GENMASK(17, 14)
#define SEC_BD_W0_C_GRAN_SIZE_19_16_S 14
#define SEC_BD_W0_CIPHER_M GENMASK(19, 18)
#define SEC_BD_W0_CIPHER_S 18
#define SEC_CIPHER_NULL 0
#define SEC_CIPHER_ENCRYPT 1
#define SEC_CIPHER_DECRYPT 2
#define SEC_BD_W0_AUTH_M GENMASK(21, 20)
#define SEC_BD_W0_AUTH_S 20
#define SEC_AUTH_NULL 0
#define SEC_AUTH_MAC 1
#define SEC_AUTH_VERIF 2
#define SEC_BD_W0_AI_GEN BIT(22)
#define SEC_BD_W0_CI_GEN BIT(23)
#define SEC_BD_W0_NO_HPAD BIT(24)
#define SEC_BD_W0_HM_M GENMASK(26, 25)
#define SEC_BD_W0_HM_S 25
#define SEC_BD_W0_ICV_OR_SKEY_EN_M GENMASK(28, 27)
#define SEC_BD_W0_ICV_OR_SKEY_EN_S 27
/* Multi purpose field - gran size bits for send, flag for recv */
#define SEC_BD_W0_FLAG_M GENMASK(30, 29)
#define SEC_BD_W0_C_GRAN_SIZE_21_20_M GENMASK(30, 29)
#define SEC_BD_W0_FLAG_S 29
#define SEC_BD_W0_C_GRAN_SIZE_21_20_S 29
#define SEC_BD_W0_DONE BIT(31)
u32 w0;
#define SEC_BD_W1_AUTH_GRAN_SIZE_M GENMASK(21, 0)
#define SEC_BD_W1_AUTH_GRAN_SIZE_S 0
#define SEC_BD_W1_M_KEY_EN BIT(22)
#define SEC_BD_W1_BD_INVALID BIT(23)
#define SEC_BD_W1_ADDR_TYPE BIT(24)
#define SEC_BD_W1_A_ALG_M GENMASK(28, 25)
#define SEC_BD_W1_A_ALG_S 25
#define SEC_A_ALG_SHA1 0
#define SEC_A_ALG_SHA256 1
#define SEC_A_ALG_MD5 2
#define SEC_A_ALG_SHA224 3
#define SEC_A_ALG_HMAC_SHA1 8
#define SEC_A_ALG_HMAC_SHA224 10
#define SEC_A_ALG_HMAC_SHA256 11
#define SEC_A_ALG_HMAC_MD5 12
#define SEC_A_ALG_AES_XCBC 13
#define SEC_A_ALG_AES_CMAC 14
#define SEC_BD_W1_C_ALG_M GENMASK(31, 29)
#define SEC_BD_W1_C_ALG_S 29
#define SEC_C_ALG_DES 0
#define SEC_C_ALG_3DES 1
#define SEC_C_ALG_AES 2
u32 w1;
#define SEC_BD_W2_C_GRAN_SIZE_15_0_M GENMASK(15, 0)
#define SEC_BD_W2_C_GRAN_SIZE_15_0_S 0
#define SEC_BD_W2_GRAN_NUM_M GENMASK(31, 16)
#define SEC_BD_W2_GRAN_NUM_S 16
u32 w2;
#define SEC_BD_W3_AUTH_LEN_OFFSET_M GENMASK(9, 0)
#define SEC_BD_W3_AUTH_LEN_OFFSET_S 0
#define SEC_BD_W3_CIPHER_LEN_OFFSET_M GENMASK(19, 10)
#define SEC_BD_W3_CIPHER_LEN_OFFSET_S 10
#define SEC_BD_W3_MAC_LEN_M GENMASK(24, 20)
#define SEC_BD_W3_MAC_LEN_S 20
#define SEC_BD_W3_A_KEY_LEN_M GENMASK(29, 25)
#define SEC_BD_W3_A_KEY_LEN_S 25
#define SEC_BD_W3_C_KEY_LEN_M GENMASK(31, 30)
#define SEC_BD_W3_C_KEY_LEN_S 30
#define SEC_KEY_LEN_AES_128 0
#define SEC_KEY_LEN_AES_192 1
#define SEC_KEY_LEN_AES_256 2
#define SEC_KEY_LEN_DES 1
#define SEC_KEY_LEN_3DES_3_KEY 1
#define SEC_KEY_LEN_3DES_2_KEY 3
u32 w3;
/* W4,5 */
union {
u32 authkey_addr_lo;
u32 authiv_addr_lo;
};
union {
u32 authkey_addr_hi;
u32 authiv_addr_hi;
};
/* W6,7 */
u32 cipher_key_addr_lo;
u32 cipher_key_addr_hi;
/* W8,9 */
u32 cipher_iv_addr_lo;
u32 cipher_iv_addr_hi;
/* W10,11 */
u32 data_addr_lo;
u32 data_addr_hi;
/* W12,13 */
u32 mac_addr_lo;
u32 mac_addr_hi;
/* W14,15 */
u32 cipher_destin_addr_lo;
u32 cipher_destin_addr_hi;
};
enum sec_mem_region {
SEC_COMMON = 0,
SEC_SAA,
SEC_NUM_ADDR_REGIONS
};
#define SEC_NAME_SIZE 64
#define SEC_Q_NUM 16
/**
* struct sec_queue_ring_cmd - store information about a SEC HW cmd ring
* @used: Local counter used to cheaply establish if the ring is empty.
* @lock: Protect against simultaneous adjusting of the read and write pointers.
* @vaddr: Virtual address for the ram pages used for the ring.
* @paddr: Physical address of the dma mapped region of ram used for the ring.
* @callback: Callback function called on a ring element completing.
*/
struct sec_queue_ring_cmd {
atomic_t used;
struct mutex lock;
struct sec_bd_info *vaddr;
dma_addr_t paddr;
void (*callback)(struct sec_bd_info *resp, void *ctx);
};
struct sec_debug_bd_info;
struct sec_queue_ring_db {
struct sec_debug_bd_info *vaddr;
dma_addr_t paddr;
};
struct sec_out_bd_info;
struct sec_queue_ring_cq {
struct sec_out_bd_info *vaddr;
dma_addr_t paddr;
};
struct sec_dev_info;
enum sec_cipher_alg {
SEC_C_DES_ECB_64,
SEC_C_DES_CBC_64,
SEC_C_3DES_ECB_192_3KEY,
SEC_C_3DES_ECB_192_2KEY,
SEC_C_3DES_CBC_192_3KEY,
SEC_C_3DES_CBC_192_2KEY,
SEC_C_AES_ECB_128,
SEC_C_AES_ECB_192,
SEC_C_AES_ECB_256,
SEC_C_AES_CBC_128,
SEC_C_AES_CBC_192,
SEC_C_AES_CBC_256,
SEC_C_AES_CTR_128,
SEC_C_AES_CTR_192,
SEC_C_AES_CTR_256,
SEC_C_AES_XTS_128,
SEC_C_AES_XTS_256,
SEC_C_NULL,
};
/**
* struct sec_alg_tfm_ctx - hardware specific tranformation context
* @cipher_alg: Cipher algorithm enabled include encryption mode.
* @key: Key storage if required.
* @pkey: DMA address for the key storage.
* @req_template: Request template to save time on setup.
* @queue: The hardware queue associated with this tfm context.
* @lock: Protect key and pkey to ensure they are consistent
* @auth_buf: Current context buffer for auth operations.
* @backlog: The backlog queue used for cases where our buffers aren't
* large enough.
*/
struct sec_alg_tfm_ctx {
enum sec_cipher_alg cipher_alg;
u8 *key;
dma_addr_t pkey;
struct sec_bd_info req_template;
struct sec_queue *queue;
struct mutex lock;
u8 *auth_buf;
struct list_head backlog;
};
/**
* struct sec_request - data associate with a single crypto request
* @elements: List of subparts of this request (hardware size restriction)
* @num_elements: The number of subparts (used as an optimization)
* @lock: Protect elements of this structure against concurrent change.
* @tfm_ctx: hardware specific context.
* @len_in: length of in sgl from upper layers
* @len_out: length of out sgl from upper layers
* @dma_iv: initialization vector - phsyical address
* @err: store used to track errors across subelements of this request.
* @req_base: pointer to base element of associate crypto context.
* This is needed to allow shared handling skcipher, ahash etc.
* @cb: completion callback.
* @backlog_head: list head to allow backlog maintenance.
*
* The hardware is limited in the maximum size of data that it can
* process from a single BD. Typically this is fairly large (32MB)
* but still requires the complexity of splitting the incoming
* skreq up into a number of elements complete with appropriate
* iv chaining.
*/
struct sec_request {
struct list_head elements;
int num_elements;
struct mutex lock;
struct sec_alg_tfm_ctx *tfm_ctx;
int len_in;
int len_out;
dma_addr_t dma_iv;
int err;
struct crypto_async_request *req_base;
void (*cb)(struct sec_bd_info *resp, struct crypto_async_request *req);
struct list_head backlog_head;
};
/**
* struct sec_request_el - A subpart of a request.
* @head: allow us to attach this to the list in the sec_request
* @req: hardware block descriptor corresponding to this request subpart
* @in: hardware sgl for input - virtual address
* @dma_in: hardware sgl for input - physical address
* @sgl_in: scatterlist for this request subpart
* @out: hardware sgl for output - virtual address
* @dma_out: hardware sgl for output - physical address
* @sgl_out: scatterlist for this request subpart
* @sec_req: The request which this subpart forms a part of
* @el_length: Number of bytes in this subpart. Needed to locate
* last ivsize chunk for iv chaining.
*/
struct sec_request_el {
struct list_head head;
struct sec_bd_info req;
struct sec_hw_sgl *in;
dma_addr_t dma_in;
struct scatterlist *sgl_in;
struct sec_hw_sgl *out;
dma_addr_t dma_out;
struct scatterlist *sgl_out;
struct sec_request *sec_req;
size_t el_length;
};
/**
* struct sec_queue - All the information about a HW queue
* @dev_info: The parent SEC device to which this queue belongs.
* @task_irq: Completion interrupt for the queue.
* @name: Human readable queue description also used as irq name.
* @ring: The several HW rings associated with one queue.
* @regs: The iomapped device registers
* @queue_id: Index of the queue used for naming and resource selection.
* @in_use: Flag to say if the queue is in use.
* @expected: The next expected element to finish assuming we were in order.
* @uprocessed: A bitmap to track which OoO elements are done but not handled.
* @softqueue: A software queue used when chaining requirements prevent direct
* use of the hardware queues.
* @havesoftqueue: A flag to say we have a queues - as we may need one for the
* current mode.
* @queuelock: Protect the soft queue from concurrent changes to avoid some
* potential loss of data races.
* @shadow: Pointers back to the shadow copy of the hardware ring element
* need because we can't store any context reference in the bd element.
*/
struct sec_queue {
struct sec_dev_info *dev_info;
int task_irq;
char name[SEC_NAME_SIZE];
struct sec_queue_ring_cmd ring_cmd;
struct sec_queue_ring_cq ring_cq;
struct sec_queue_ring_db ring_db;
void __iomem *regs;
u32 queue_id;
bool in_use;
int expected;
DECLARE_BITMAP(unprocessed, SEC_QUEUE_LEN);
DECLARE_KFIFO_PTR(softqueue, typeof(struct sec_request_el *));
bool havesoftqueue;
spinlock_t queuelock;
void *shadow[SEC_QUEUE_LEN];
};
/**
* struct sec_hw_sge: Track each of the 64 element SEC HW SGL entries
* @buf: The IOV dma address for this entry.
* @len: Length of this IOV.
* @pad: Reserved space.
*/
struct sec_hw_sge {
dma_addr_t buf;
unsigned int len;
unsigned int pad;
};
/**
* struct sec_hw_sgl: One hardware SGL entry.
* @next_sgl: The next entry if we need to chain dma address. Null if last.
* @entry_sum_in_chain: The full count of SGEs - only matters for first SGL.
* @entry_sum_in_sgl: The number of SGEs in this SGL element.
* @flag: Unused in skciphers.
* @serial_num: Unsued in skciphers.
* @cpuid: Currently unused.
* @data_bytes_in_sgl: Count of bytes from all SGEs in this SGL.
* @next: Virtual address used to stash the next sgl - useful in completion.
* @reserved: A reserved field not currently used.
* @sge_entries: The (up to) 64 Scatter Gather Entries, representing IOVs.
* @node: Currently unused.
*/
struct sec_hw_sgl {
dma_addr_t next_sgl;
u16 entry_sum_in_chain;
u16 entry_sum_in_sgl;
u32 flag;
u64 serial_num;
u32 cpuid;
u32 data_bytes_in_sgl;
struct sec_hw_sgl *next;
u64 reserved;
struct sec_hw_sge sge_entries[SEC_MAX_SGE_NUM];
u8 node[16];
};
struct dma_pool;
/**
* struct sec_dev_info: The full SEC unit comprising queues and processors.
* @sec_id: Index used to track which SEC this is when more than one is present.
* @num_saas: The number of backed processors enabled.
* @regs: iomapped register regions shared by whole SEC unit.
* @dev_lock: Protects concurrent queue allocation / freeing for the SEC.
* @queues: The 16 queues that this SEC instance provides.
* @dev: Device pointer.
* @hw_sgl_pool: DMA pool used to mimise mapping for the scatter gather lists.
*/
struct sec_dev_info {
int sec_id;
int num_saas;
void __iomem *regs[SEC_NUM_ADDR_REGIONS];
struct mutex dev_lock;
int queues_in_use;
struct sec_queue queues[SEC_Q_NUM];
struct device *dev;
struct dma_pool *hw_sgl_pool;
};
int sec_queue_send(struct sec_queue *queue, struct sec_bd_info *msg, void *ctx);
bool sec_queue_can_enqueue(struct sec_queue *queue, int num);
int sec_queue_stop_release(struct sec_queue *queue);
struct sec_queue *sec_queue_alloc_start_safe(void);
bool sec_queue_empty(struct sec_queue *queue);
/* Algorithm specific elements from sec_algs.c */
void sec_alg_callback(struct sec_bd_info *resp, void *ctx);
int sec_algs_register(void);
void sec_algs_unregister(void);
#endif /* _SEC_DRV_H_ */
drivers/crypto/hisilicon/sec2/sec_main.c
+1 -1
View File
@@ -1285,8 +1285,8 @@ static int sec_pre_store_cap_reg(struct hisi_qm *qm)
i, qm->cap_ver);
}
qm->cap_tables.dev_cap_table = sec_cap;
qm->cap_tables.dev_cap_size = size;
qm->cap_tables.dev_cap_table = sec_cap;
return 0;
}
drivers/crypto/hisilicon/zip/dae_main.c
+21 -2
View File
@@ -39,6 +39,8 @@
#define DAE_AM_RETURN_MASK 0x3
#define DAE_AXI_CFG_OFFSET 0x331000
#define DAE_AXI_SHUTDOWN_EN_MASK (BIT(0) | BIT(5))
#define DAE_AUTO_CG_EN_OFFSET 0x331070
#define DAE_AUTO_CG_EN_MASK (~(BIT_ULL(4) | BIT_ULL(18) | BIT_ULL(19)))
struct hisi_dae_hw_error {
u32 int_msk;
@@ -61,6 +63,17 @@ static inline bool dae_is_support(struct hisi_qm *qm)
return false;
}
static void hisi_dae_set_clock_gating(struct hisi_qm *qm, bool enable)
{
if (qm->ver < QM_HW_V5)
return;
if (enable)
writeq(DAE_AUTO_CG_EN_MASK, qm->io_base + DAE_AUTO_CG_EN_OFFSET);
else
writeq(0, qm->io_base + DAE_AUTO_CG_EN_OFFSET);
}
int hisi_dae_set_user_domain(struct hisi_qm *qm)
{
u32 val;
@@ -69,16 +82,22 @@ int hisi_dae_set_user_domain(struct hisi_qm *qm)
if (!dae_is_support(qm))
return 0;
hisi_dae_set_clock_gating(qm, false);
val = readl(qm->io_base + DAE_MEM_START_OFFSET);
val |= DAE_MEM_START_MASK;
writel(val, qm->io_base + DAE_MEM_START_OFFSET);
ret = readl_relaxed_poll_timeout(qm->io_base + DAE_MEM_DONE_OFFSET, val,
val & DAE_MEM_DONE_MASK,
DAE_REG_RD_INTVRL_US, DAE_REG_RD_TMOUT_US);
if (ret)
if (ret) {
pci_err(qm->pdev, "failed to init dae memory!\n");
return ret;
}
return ret;
hisi_dae_set_clock_gating(qm, true);
return 0;
}
int hisi_dae_set_alg(struct hisi_qm *qm)
drivers/crypto/hisilicon/zip/zip_main.c
+1 -1
View File
@@ -1400,8 +1400,8 @@ static int zip_pre_store_cap_reg(struct hisi_qm *qm)
i, qm->cap_ver);
}
qm->cap_tables.dev_cap_table = zip_cap;
qm->cap_tables.dev_cap_size = size;
qm->cap_tables.dev_cap_table = zip_cap;
return 0;
}
drivers/crypto/inside-secure/eip93/eip93-aead.c
+1 -2
View File
@@ -92,7 +92,6 @@ static int eip93_aead_setkey(struct crypto_aead *ctfm, const u8 *key,
struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
struct eip93_crypto_ctx *ctx = crypto_tfm_ctx(tfm);
struct crypto_authenc_keys keys;
struct crypto_aes_ctx aes;
struct sa_record *sa_record = ctx->sa_record;
u32 nonce = 0;
int ret;
@@ -126,7 +125,7 @@ static int eip93_aead_setkey(struct crypto_aead *ctfm, const u8 *key,
break;
case EIP93_ALG_AES:
ret = aes_expandkey(&aes, keys.enckey, keys.enckeylen);
ret = aes_check_keylen(keys.enckeylen);
if (ret)
return ret;
drivers/crypto/inside-secure/eip93/eip93-regs.h
+1 -1
View File
@@ -281,7 +281,7 @@
#define EIP93_SA_CMD_HASH_CRYPT_OFFSET GENMASK(23, 16)
#define EIP93_SA_CMD_BYTE_OFFSET BIT(13) /* 0: CRYPT_OFFSET in 32bit word 1: CRYPT_OFFSET in 8bit bytes */
#define EIP93_SA_CMD_HMAC BIT(12)
#define EIP93_SA_CMD_SSL_MAC BIT(12)
#define EIP93_SA_CMD_SSL_MAC BIT(11)
/* This mask can be either used for ARC4 or AES */
#define EIP93_SA_CMD_CHIPER_MODE GENMASK(9, 8)
/* AES or DES operations */
drivers/crypto/inside-secure/safexcel_cipher.c
+5 -11
View File
@@ -375,7 +375,7 @@ static int safexcel_skcipher_aes_setkey(struct crypto_skcipher *ctfm,
struct crypto_tfm *tfm = crypto_skcipher_tfm(ctfm);
struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
struct safexcel_crypto_priv *priv = ctx->base.priv;
struct crypto_aes_ctx aes;
struct crypto_aes_ctx aes __cleanup(aes_zeroize_ctx);
int ret, i;
ret = aes_expandkey(&aes, key, len);
@@ -396,7 +396,6 @@ static int safexcel_skcipher_aes_setkey(struct crypto_skcipher *ctfm,
ctx->key_len = len;
memzero_explicit(&aes, sizeof(aes));
return 0;
}
@@ -407,7 +406,6 @@ static int safexcel_aead_setkey(struct crypto_aead *ctfm, const u8 *key,
struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
struct safexcel_crypto_priv *priv = ctx->base.priv;
struct crypto_authenc_keys keys;
struct crypto_aes_ctx aes;
int err = -EINVAL, i;
const char *alg;
@@ -438,7 +436,7 @@ static int safexcel_aead_setkey(struct crypto_aead *ctfm, const u8 *key,
goto badkey;
break;
case SAFEXCEL_AES:
err = aes_expandkey(&aes, keys.enckey, keys.enckeylen);
err = aes_check_keylen(keys.enckeylen);
if (unlikely(err))
goto badkey;
break;
@@ -1362,7 +1360,7 @@ static int safexcel_skcipher_aesctr_setkey(struct crypto_skcipher *ctfm,
struct crypto_tfm *tfm = crypto_skcipher_tfm(ctfm);
struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
struct safexcel_crypto_priv *priv = ctx->base.priv;
struct crypto_aes_ctx aes;
struct crypto_aes_ctx aes __cleanup(aes_zeroize_ctx);
int ret, i;
unsigned int keylen;
@@ -1388,7 +1386,6 @@ static int safexcel_skcipher_aesctr_setkey(struct crypto_skcipher *ctfm,
ctx->key_len = keylen;
memzero_explicit(&aes, sizeof(aes));
return 0;
}
@@ -2542,7 +2539,7 @@ static int safexcel_skcipher_aesxts_setkey(struct crypto_skcipher *ctfm,
struct crypto_tfm *tfm = crypto_skcipher_tfm(ctfm);
struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
struct safexcel_crypto_priv *priv = ctx->base.priv;
struct crypto_aes_ctx aes;
struct crypto_aes_ctx aes __cleanup(aes_zeroize_ctx);
int ret, i;
unsigned int keylen;
@@ -2590,7 +2587,6 @@ static int safexcel_skcipher_aesxts_setkey(struct crypto_skcipher *ctfm,
ctx->key_len = keylen << 1;
memzero_explicit(&aes, sizeof(aes));
return 0;
}
@@ -2756,12 +2752,11 @@ static int safexcel_aead_ccm_setkey(struct crypto_aead *ctfm, const u8 *key,
struct crypto_tfm *tfm = crypto_aead_tfm(ctfm);
struct safexcel_cipher_ctx *ctx = crypto_tfm_ctx(tfm);
struct safexcel_crypto_priv *priv = ctx->base.priv;
struct crypto_aes_ctx aes;
struct crypto_aes_ctx aes __cleanup(aes_zeroize_ctx);
int ret, i;
ret = aes_expandkey(&aes, key, len);
if (ret) {
memzero_explicit(&aes, sizeof(aes));
return ret;
}
@@ -2790,7 +2785,6 @@ static int safexcel_aead_ccm_setkey(struct crypto_aead *ctfm, const u8 *key,
else
ctx->hash_alg = CONTEXT_CONTROL_CRYPTO_ALG_XCBC128;
memzero_explicit(&aes, sizeof(aes));
return 0;
}
drivers/crypto/inside-secure/safexcel_hash.c
+4 -2
View File
@@ -1905,7 +1905,7 @@ static int safexcel_cbcmac_setkey(struct crypto_ahash *tfm, const u8 *key,
unsigned int len)
{
struct safexcel_ahash_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
struct crypto_aes_ctx aes;
struct crypto_aes_ctx aes __cleanup(aes_zeroize_ctx);
int ret, i;
ret = aes_expandkey(&aes, key, len);
@@ -1928,7 +1928,6 @@ static int safexcel_cbcmac_setkey(struct crypto_ahash *tfm, const u8 *key,
}
ctx->cbcmac = true;
memzero_explicit(&aes, sizeof(aes));
return 0;
}
@@ -1993,6 +1992,7 @@ static int safexcel_xcbcmac_setkey(struct crypto_ahash *tfm, const u8 *key,
ret = aes_prepareenckey(ctx->aes,
(u8 *)key_tmp + 2 * AES_BLOCK_SIZE,
AES_MIN_KEY_SIZE);
memzero_explicit(key_tmp, sizeof(key_tmp));
if (ret)
return ret;
@@ -2104,6 +2104,8 @@ static int safexcel_cmac_setkey(struct crypto_ahash *tfm, const u8 *key,
}
ctx->cbcmac = false;
memzero_explicit(consts, sizeof(consts));
memzero_explicit(_const, sizeof(_const));
return 0;
}
drivers/crypto/intel/ixp4xx/ixp4xx_crypto.c
+1 -2
View File
@@ -707,8 +707,7 @@ static int register_chain_var(struct crypto_tfm *tfm, u8 xpad, u32 target,
return -EAGAIN;
}
memcpy(pad, key, key_len);
memset(pad + key_len, 0, HMAC_PAD_BLOCKLEN - key_len);
memcpy_and_pad(pad, HMAC_PAD_BLOCKLEN, key, key_len, 0);
for (i = 0; i < HMAC_PAD_BLOCKLEN; i++)
pad[i] ^= xpad;
drivers/crypto/intel/qat/qat_420xx/adf_420xx_hw_data.c
-1
View File
@@ -443,7 +443,6 @@ void adf_init_hw_data_420xx(struct adf_hw_device_data *hw_data, u32 dev_id)
hw_data->enable_error_correction = adf_gen4_enable_error_correction;
hw_data->get_accel_mask = adf_gen4_get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = adf_gen4_get_num_accels;
hw_data->get_num_aes = adf_gen4_get_num_aes;
hw_data->get_sram_bar_id = adf_gen4_get_sram_bar_id;
hw_data->get_etr_bar_id = adf_gen4_get_etr_bar_id;
drivers/crypto/intel/qat/qat_4xxx/adf_4xxx_hw_data.c
-1
View File
@@ -412,7 +412,6 @@ void adf_init_hw_data_4xxx(struct adf_hw_device_data *hw_data, u32 dev_id)
hw_data->enable_error_correction = adf_gen4_enable_error_correction;
hw_data->get_accel_mask = adf_gen4_get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = adf_gen4_get_num_accels;
hw_data->get_num_aes = adf_gen4_get_num_aes;
hw_data->get_sram_bar_id = adf_gen4_get_sram_bar_id;
hw_data->get_etr_bar_id = adf_gen4_get_etr_bar_id;
drivers/crypto/intel/qat/qat_6xxx/adf_6xxx_hw_data.c
-6
View File
@@ -326,11 +326,6 @@ static u32 get_accel_mask(struct adf_hw_device_data *self)
return ADF_GEN6_ACCELERATORS_MASK;
}
static u32 get_num_accels(struct adf_hw_device_data *self)
{
return ADF_GEN6_MAX_ACCELERATORS;
}
static u32 get_num_aes(struct adf_hw_device_data *self)
{
return self ? hweight32(self->ae_mask) : 0;
@@ -1023,7 +1018,6 @@ void adf_init_hw_data_6xxx(struct adf_hw_device_data *hw_data)
hw_data->enable_error_correction = enable_error_correction;
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = get_num_accels;
hw_data->get_num_aes = get_num_aes;
hw_data->get_sram_bar_id = get_sram_bar_id;
hw_data->get_etr_bar_id = get_etr_bar_id;
drivers/crypto/intel/qat/qat_c3xxx/adf_c3xxx_hw_data.c
-1
View File
@@ -129,7 +129,6 @@ void adf_init_hw_data_c3xxx(struct adf_hw_device_data *hw_data)
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_accel_cap = adf_gen2_get_accel_cap;
hw_data->get_num_accels = adf_gen2_get_num_accels;
hw_data->get_num_aes = adf_gen2_get_num_aes;
hw_data->get_sram_bar_id = get_sram_bar_id;
hw_data->get_etr_bar_id = get_etr_bar_id;
drivers/crypto/intel/qat/qat_c3xxxvf/adf_c3xxxvf_hw_data.c
-6
View File
@@ -24,11 +24,6 @@ static u32 get_ae_mask(struct adf_hw_device_data *self)
return ADF_C3XXXIOV_ACCELENGINES_MASK;
}
static u32 get_num_accels(struct adf_hw_device_data *self)
{
return ADF_C3XXXIOV_MAX_ACCELERATORS;
}
static u32 get_num_aes(struct adf_hw_device_data *self)
{
return ADF_C3XXXIOV_MAX_ACCELENGINES;
@@ -80,7 +75,6 @@ void adf_init_hw_data_c3xxxiov(struct adf_hw_device_data *hw_data)
hw_data->disable_iov = adf_vf2pf_notify_shutdown;
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = get_num_accels;
hw_data->get_num_aes = get_num_aes;
hw_data->get_etr_bar_id = get_etr_bar_id;
hw_data->get_misc_bar_id = get_misc_bar_id;
drivers/crypto/intel/qat/qat_c62x/adf_c62x_hw_data.c
-1
View File
@@ -131,7 +131,6 @@ void adf_init_hw_data_c62x(struct adf_hw_device_data *hw_data)
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_accel_cap = adf_gen2_get_accel_cap;
hw_data->get_num_accels = adf_gen2_get_num_accels;
hw_data->get_num_aes = adf_gen2_get_num_aes;
hw_data->get_sram_bar_id = get_sram_bar_id;
hw_data->get_etr_bar_id = get_etr_bar_id;
drivers/crypto/intel/qat/qat_c62xvf/adf_c62xvf_hw_data.c
-6
View File
@@ -24,11 +24,6 @@ static u32 get_ae_mask(struct adf_hw_device_data *self)
return ADF_C62XIOV_ACCELENGINES_MASK;
}
static u32 get_num_accels(struct adf_hw_device_data *self)
{
return ADF_C62XIOV_MAX_ACCELERATORS;
}
static u32 get_num_aes(struct adf_hw_device_data *self)
{
return ADF_C62XIOV_MAX_ACCELENGINES;
@@ -80,7 +75,6 @@ void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data)
hw_data->disable_iov = adf_vf2pf_notify_shutdown;
hw_data->get_accel_mask = get_accel_mask;
hw_data->get_ae_mask = get_ae_mask;
hw_data->get_num_accels = get_num_accels;
hw_data->get_num_aes = get_num_aes;
hw_data->get_etr_bar_id = get_etr_bar_id;
hw_data->get_misc_bar_id = get_misc_bar_id;
drivers/crypto/intel/qat/qat_common/adf_accel_devices.h
-1
View File
@@ -279,7 +279,6 @@ struct adf_hw_device_data {
u32 (*get_misc_bar_id)(struct adf_hw_device_data *self);
u32 (*get_etr_bar_id)(struct adf_hw_device_data *self);
u32 (*get_num_aes)(struct adf_hw_device_data *self);
u32 (*get_num_accels)(struct adf_hw_device_data *self);
void (*get_arb_info)(struct arb_info *arb_csrs_info);
void (*get_admin_info)(struct admin_info *admin_csrs_info);
enum dev_sku_info (*get_sku)(struct adf_hw_device_data *self);
drivers/crypto/intel/qat/qat_common/adf_cfg.c
+38 -46
View File
@@ -1,6 +1,5 @@
// SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only)
/* Copyright(c) 2014 - 2020 Intel Corporation */
#include <linux/mutex.h>
#include <linux/slab.h>
#include <linux/string.h>
#include <linux/list.h>
@@ -9,13 +8,11 @@
#include "adf_cfg.h"
#include "adf_common_drv.h"
static DEFINE_MUTEX(qat_cfg_read_lock);
static void *qat_dev_cfg_start(struct seq_file *sfile, loff_t *pos)
{
struct adf_cfg_device_data *dev_cfg = sfile->private;
mutex_lock(&qat_cfg_read_lock);
down_read(&dev_cfg->lock);
return seq_list_start(&dev_cfg->sec_list, *pos);
}
@@ -43,7 +40,9 @@ static void *qat_dev_cfg_next(struct seq_file *sfile, void *v, loff_t *pos)
static void qat_dev_cfg_stop(struct seq_file *sfile, void *v)
{
mutex_unlock(&qat_cfg_read_lock);
struct adf_cfg_device_data *dev_cfg = sfile->private;
up_read(&dev_cfg->lock);
}
static const struct seq_operations qat_dev_cfg_sops = {
@@ -146,24 +145,6 @@ static void adf_cfg_keyval_add(struct adf_cfg_key_val *new,
list_add_tail(&new->list, &sec->param_head);
}
static void adf_cfg_keyval_remove(const char *key, struct adf_cfg_section *sec)
{
struct list_head *head = &sec->param_head;
struct list_head *list_ptr, *tmp;
list_for_each_prev_safe(list_ptr, tmp, head) {
struct adf_cfg_key_val *ptr =
list_entry(list_ptr, struct adf_cfg_key_val, list);
if (strncmp(ptr->key, key, sizeof(ptr->key)))
continue;
list_del(list_ptr);
kfree(ptr);
break;
}
}
static void adf_cfg_keyval_del_all(struct list_head *head)
{
struct list_head *list_ptr, *tmp;
@@ -272,13 +253,9 @@ int adf_cfg_add_key_value_param(struct adf_accel_dev *accel_dev,
enum adf_cfg_val_type type)
{
struct adf_cfg_device_data *cfg = accel_dev->cfg;
struct adf_cfg_key_val *key_val;
struct adf_cfg_section *section = adf_cfg_sec_find(accel_dev,
section_name);
char temp_val[ADF_CFG_MAX_VAL_LEN_IN_BYTES];
if (!section)
return -EFAULT;
struct adf_cfg_key_val *key_val, *existing;
struct adf_cfg_section *section;
int ret = 0;
key_val = kzalloc_obj(*key_val);
if (!key_val)
@@ -299,7 +276,17 @@ int adf_cfg_add_key_value_param(struct adf_accel_dev *accel_dev,
}
key_val->type = type;
/* Add the key-value pair as below policy:
down_write(&cfg->lock);
section = adf_cfg_sec_find(accel_dev, section_name);
if (!section) {
kfree(key_val);
ret = -ENOENT;
goto unlock;
}
/*
* Add the key-value pair as below policy:
* 1. if the key doesn't exist, add it;
* 2. if the key already exists with a different value then update it
* to the new value (the key is deleted and the newly created
@@ -307,21 +294,21 @@ int adf_cfg_add_key_value_param(struct adf_accel_dev *accel_dev,
* 3. if the key exists with the same value, then return without doing
* anything (the newly created key_val is freed).
*/
down_write(&cfg->lock);
if (!adf_cfg_key_val_get(accel_dev, section_name, key, temp_val)) {
if (strncmp(temp_val, key_val->val, sizeof(temp_val))) {
adf_cfg_keyval_remove(key, section);
} else {
existing = adf_cfg_key_value_find(section, key);
if (existing) {
if (!strncmp(existing->val, key_val->val, sizeof(existing->val))) {
kfree(key_val);
goto out;
goto unlock;
}
list_del(&existing->list);
kfree(existing);
}
adf_cfg_keyval_add(key_val, section);
out:
unlock:
up_write(&cfg->lock);
return 0;
return ret;
}
EXPORT_SYMBOL_GPL(adf_cfg_add_key_value_param);
@@ -339,21 +326,26 @@ EXPORT_SYMBOL_GPL(adf_cfg_add_key_value_param);
int adf_cfg_section_add(struct adf_accel_dev *accel_dev, const char *name)
{
struct adf_cfg_device_data *cfg = accel_dev->cfg;
struct adf_cfg_section *sec = adf_cfg_sec_find(accel_dev, name);
struct adf_cfg_section *sec;
int ret = 0;
if (sec)
return 0;
down_write(&cfg->lock);
if (adf_cfg_sec_find(accel_dev, name))
goto unlock;
sec = kzalloc_obj(*sec);
if (!sec)
return -ENOMEM;
if (!sec) {
ret = -ENOMEM;
goto unlock;
}
strscpy(sec->name, name);
INIT_LIST_HEAD(&sec->param_head);
down_write(&cfg->lock);
list_add_tail(&sec->list, &cfg->sec_list);
unlock:
up_write(&cfg->lock);
return 0;
return ret;
}
EXPORT_SYMBOL_GPL(adf_cfg_section_add);
drivers/crypto/intel/qat/qat_common/adf_dev_mgr.c
+9 -1
View File
@@ -137,6 +137,13 @@ int adf_devmgr_add_dev(struct adf_accel_dev *accel_dev,
mutex_lock(&table_lock);
atomic_set(&accel_dev->ref_count, 0);
mutex_init(&accel_dev->state_lock);
/*
* The VF2PF lock is used to send messages to the PF outside of the
* device up/down cycle, so it must live as long as the accel device.
*/
if (accel_dev->is_vf)
mutex_init(&accel_dev->vf.vf2pf_lock);
/* PF on host or VF on guest - optimized to remove redundant is_vf */
if (!accel_dev->is_vf || !pf) {
@@ -210,7 +217,6 @@ int adf_devmgr_add_dev(struct adf_accel_dev *accel_dev,
map->attached = true;
list_add_tail(&map->list, &vfs_table);
}
mutex_init(&accel_dev->state_lock);
unlock:
mutex_unlock(&table_lock);
return ret;
@@ -257,6 +263,8 @@ void adf_devmgr_rm_dev(struct adf_accel_dev *accel_dev,
}
}
unlock:
if (accel_dev->is_vf)
mutex_destroy(&accel_dev->vf.vf2pf_lock);
mutex_destroy(&accel_dev->state_lock);
list_del(&accel_dev->list);
mutex_unlock(&table_lock);
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.c
-9
View File
@@ -7,15 +7,6 @@
#include "icp_qat_hw.h"
#include <linux/pci.h>
u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self)
{
if (!self || !self->accel_mask)
return 0;
return hweight16(self->accel_mask);
}
EXPORT_SYMBOL_GPL(adf_gen2_get_num_accels);
u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self)
{
if (!self || !self->ae_mask)
drivers/crypto/intel/qat/qat_common/adf_gen2_hw_data.h
-1
View File
@@ -78,7 +78,6 @@
#define ADF_GEN2_SMIAPF1_MASK_OFFSET (0x3A000 + 0x30)
#define ADF_GEN2_SMIA1_MASK 0x1
u32 adf_gen2_get_num_accels(struct adf_hw_device_data *self);
u32 adf_gen2_get_num_aes(struct adf_hw_device_data *self);
void adf_gen2_enable_error_correction(struct adf_accel_dev *accel_dev);
void adf_gen2_cfg_iov_thds(struct adf_accel_dev *accel_dev, bool enable,
drivers/crypto/intel/qat/qat_common/adf_gen4_hw_data.c
-6
View File
@@ -21,12 +21,6 @@ u32 adf_gen4_get_accel_mask(struct adf_hw_device_data *self)
}
EXPORT_SYMBOL_GPL(adf_gen4_get_accel_mask);
u32 adf_gen4_get_num_accels(struct adf_hw_device_data *self)
{
return ADF_GEN4_MAX_ACCELERATORS;
}
EXPORT_SYMBOL_GPL(adf_gen4_get_num_accels);
u32 adf_gen4_get_num_aes(struct adf_hw_device_data *self)
{
if (!self || !self->ae_mask)
Loaded 100 of 144 files, more files were not shown because too many files have changed in this diff. Show more