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Merge tag 'devicetree-for-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

Browse Source 
Pull devicetree updates from Rob Herring:

 - A bunch of improvements in dt-check-style. Fix various bindings based
   on these additional checks.

 - Convert hisilicon,hix5hd2-ir, hisilicon,hi6220-ade,
   hisilicon,hi6220-dsi, hisilicon,hip05-sas-v1, MediaTek RT5650 codecs,
   mediatek,g3dsys, mediatek,mt2701-scpsys, ti,omap-mpu, and
   ti,omap-ocp2scp to DT schema format

 - Add schemas for ST STM32MP2 DWC3 xHCI USB, ST STM32MP25 USB2-FEMTO
   PHY, spacemit,k1-gpu and spacemit,k3-gpu, HiSilicon local bus,
   HiSilicon HIP05 CPLD, SDMC DM2016, and QCom SM7250 and Kuno PDC

 - Various binding updates to fix schema warnings in .dts files

 - Drop obsolete .txt bindings for STM32(MP1) RCC, VExpress hwmon and
   regulator, and mailbox.txt

 - Remove the unused of_overlay_remove_all() function

 - Fixes for of_check_msi_parent()

 - Add "i2c-parent" tracking to fw_devlink

* tag 'devicetree-for-7.4' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (72 commits)
  dt-bindings: usb: dwc3: Document ST STM32MP2 DWC3 xHCI USB controller
  dt-bindings: iommu: Describe MT8195 infra IRQs
  dt-bindings: clock: mediatek: Add MT8516 fallbacks
  dt-bindings: media: Convert hisilicon,hix5hd2-ir to DT schema
  dt-bindings: display: Convert hisilicon,hi6220-ade to DT schema
  dt-bindings: display: Convert hisilicon,hi6220-dsi to DT schema
  dt-bindings: phy: Document ST STM32MP25 USB2-FEMTO PHY
  of: overlay: remove unused of_overlay_remove_all()
  dt-bindings: power: Convert mediatek,mt2701-scpsys to DT schema
  dt-bindings: bus: Add HiSilicon local bus
  dt-bindings: gpu: img,powervr-rogue: add spacemit,k1-gpu and spacemit,k3-gpu
  dt-bindings: interrupt-controller: qcom,pdc: Document SM7250 PDC
  dt-bindings: vendor-prefixes: add Ambarella
  dt-bindings: reset: Drop obsolete STM32(MP1) RCC bindings
  dt-bindings: arm: keystone: ti,sci: Correct reg and mboxes constraints
  dt-bindings: ASoC: Convert MediaTek RT5650 codecs bindings to DT schema
  dt-bindings: scsi: Convert hisilicon,hip05-sas-v1 to DT schema
  of/irq: Stop the MSI walk at the first msi-parent
  of/irq: Fix device node refcount leak in of_check_msi_parent()
  dt-bindings: display: faraday,tve200: Use a level-high interrupt
  ...
This commit is contained in:
Linus Torvalds committed 2026-10-24 20:11:23 -10:00
2 parents 89d2d7bf06 e8ff9af18e
commit 21a7f44fd0
188 files changed
+3233 -1406
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Documentation/devicetree/bindings/arm/arm,cci-400.yaml
+5 -1
View File
@@ -45,7 +45,11 @@ patternProperties:
properties:
compatible:
const: arm,cci-400-ctrl-if
oneOf:
- const: arm,cci-400-ctrl-if
- items:
- const: arm,cci-400-ctrl-if
- const: syscon
interface-type:
enum:
Documentation/devicetree/bindings/arm/arm,coresight-cti.yaml
+1 -1
View File
@@ -308,7 +308,7 @@ examples:
arm,trig-in-sigs = <0 1>;
arm,trig-in-types = <PE_DBGTRIGGER
PE_PMUIRQ>;
arm,trig-out-sigs = <0 1 2 >;
arm,trig-out-sigs = <0 1 2>;
arm,trig-out-types = <PE_EDBGREQ
PE_DBGRESTART
PE_CTIIRQ>;
Documentation/devicetree/bindings/arm/keystone/ti,sci.yaml
+2 -2
View File
@@ -48,7 +48,7 @@ properties:
const: debug_messages
reg:
minItems: 1
maxItems: 1
mbox-names:
description: |
@@ -59,7 +59,7 @@ properties:
- const: tx
mboxes:
minItems: 2
maxItems: 2
ti,host-id:
$ref: /schemas/types.yaml#/definitions/uint32
Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml
+1 -1
View File
@@ -19,7 +19,7 @@ properties:
- enum:
- mediatek,mt2701-audsys
- mediatek,mt6765-audsys
- mediatek,mt6779-audsys
- mediatek,mt6779-audio
- mediatek,mt7622-audsys
- mediatek,mt8167-audsys
- mediatek,mt8173-audsys
Documentation/devicetree/bindings/arm/mediatek/mediatek,g3dsys.txt
-30
View File
@@ -1,30 +0,0 @@
MediaTek g3dsys controller
============================
The MediaTek g3dsys controller provides various clocks and reset controller to
the GPU.
Required Properties:
- compatible: Should be:
- "mediatek,mt2701-g3dsys", "syscon":
for MT2701 SoC
- "mediatek,mt7623-g3dsys", "mediatek,mt2701-g3dsys", "syscon":
for MT7623 SoC
- #clock-cells: Must be 1
- #reset-cells: Must be 1
The g3dsys controller uses the common clk binding from
Documentation/devicetree/bindings/clock/clock-bindings.txt
The available clocks are defined in dt-bindings/clock/mt*-clk.h.
Example:
g3dsys: clock-controller@13000000 {
compatible = "mediatek,mt7623-g3dsys",
"mediatek,mt2701-g3dsys",
"syscon";
reg = <0 0x13000000 0 0x200>;
#clock-cells = <1>;
#reset-cells = <1>;
};
Documentation/devicetree/bindings/arm/omap/mpu.txt
-54
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@@ -1,54 +0,0 @@
* TI - MPU (Main Processor Unit) subsystem
The MPU subsystem contain one or several ARM cores
depending of the version.
The MPU contain CPUs, GIC, L2 cache and a local PRCM.
Required properties:
- compatible : Should be "ti,omap3-mpu" for OMAP3
Should be "ti,omap4-mpu" for OMAP4
Should be "ti,omap5-mpu" for OMAP5
- ti,hwmods: "mpu"
Optional properties:
- sram: Phandle to the ocmcram node
am335x and am437x only:
- pm-sram: Phandles to ocmcram nodes to be used for power management.
First should be type 'protect-exec' for the driver to use to copy
and run PM functions, second should be regular pool to be used for
data region for code. See Documentation/devicetree/bindings/sram/sram.yaml
for more details.
Examples:
- For an OMAP5 SMP system:
mpu {
compatible = "ti,omap5-mpu";
ti,hwmods = "mpu"
};
- For an OMAP4 SMP system:
mpu {
compatible = "ti,omap4-mpu";
ti,hwmods = "mpu";
};
- For an OMAP3 monocore system:
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
};
- For an AM335x system:
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
pm-sram = <&pm_sram_code
&pm_sram_data>;
};
Documentation/devicetree/bindings/arm/ti/ti,omap-mpu.yaml
+58
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@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/arm/ti/ti,omap-mpu.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI MPU (Main Processor Unit) subsystem
maintainers:
- Benoit Cousson <b-cousson@ti.com>
description:
The MPU subsystem contains one or several ARM cores depending on the version.
The MPU contains CPUs, GIC, L2 cache and a local PRCM.
properties:
compatible:
enum:
- ti,omap3-mpu
- ti,omap4-mpu
- ti,omap5-mpu
ti,hwmods:
$ref: /schemas/types.yaml#/definitions/string
description: Name of the hwmod associated with the MPU
const: mpu
deprecated: true
sram:
description: ocmcram node
pm-sram:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: ocmcram nodes for power management. For am335x and am437x.
items:
- items:
- description: ocmcram node of type protect-exec for PM functions
- items:
- description: ocmcram node of regular pool to be used for data region
required:
- compatible
additionalProperties: false
examples:
- |
mpu {
compatible = "ti,omap5-mpu";
ti,hwmods = "mpu";
};
- |
mpu {
compatible = "ti,omap3-mpu";
ti,hwmods = "mpu";
pm-sram = <&pm_sram_code &pm_sram_data>;
};
Documentation/devicetree/bindings/arm/vexpress-config.yaml
+4
View File
@@ -139,6 +139,10 @@ patternProperties:
"^regulator-.+$":
$ref: /schemas/regulator/regulator.yaml#
description:
If regulator-min-microvolt and regulator-max-microvolt do not both
define a range, the supply is treated as fixed and only its voltage
can be read.
properties:
compatible:
const: arm,vexpress-volt
Documentation/devicetree/bindings/bus/hisilicon,hisi-localbus.yaml
+44
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@@ -0,0 +1,44 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/hisilicon,hisi-localbus.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon local bus
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
allOf:
- $ref: /schemas/simple-bus.yaml#
properties:
compatible:
items:
- const: hisilicon,hisi-localbus
- const: simple-bus
reg:
maxItems: 1
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
local-bus@80380000 {
compatible = "hisilicon,hisi-localbus", "simple-bus";
reg = <0x0 0x80380000 0x0 0x10000>;
#address-cells = <2>;
#size-cells = <1>;
ranges = <0 0 0x0 0x90000000 0x08000000>,
<1 0 0x0 0x98000000 0x08000000>;
};
};
Documentation/devicetree/bindings/bus/omap-ocp2scp.txt
-29
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@@ -1,29 +0,0 @@
* OMAP OCP2SCP - ocp interface to scp interface
properties:
- compatible : Should be "ti,am437x-ocp2scp" for AM437x processor
Should be "ti,omap-ocp2scp" for all others
- reg : Address and length of the register set for the device
- #address-cells, #size-cells : Must be present if the device has sub-nodes
- ranges : the child address space are mapped 1:1 onto the parent address space
- ti,hwmods : must be "ocp2scp_usb_phy"
Sub-nodes:
All the devices connected to ocp2scp are described using sub-node to ocp2scp
ocp2scp@4a0ad000 {
compatible = "ti,omap-ocp2scp";
reg = <0x4a0ad000 0x1f>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
ti,hwmods = "ocp2scp_usb_phy";
subnode1 {
...
};
subnode2 {
...
};
};
Documentation/devicetree/bindings/bus/ti,omap-ocp2scp.yaml
+74
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@@ -0,0 +1,74 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/bus/ti,omap-ocp2scp.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: TI OMAP OCP to SCP bus bridge
maintainers:
- Kishon Vijay Abraham I <kishon@ti.com>
properties:
compatible:
oneOf:
- items:
- const: ti,am437x-ocp2scp
- const: ti,omap-ocp2scp
- const: ti,omap-ocp2scp
reg:
maxItems: 1
"#address-cells":
const: 1
"#size-cells":
const: 1
ranges: true
ti,hwmods:
$ref: /schemas/types.yaml#/definitions/string
description: Name of the hwmod associated with the device.
deprecated: true
required:
- compatible
- "#address-cells"
- "#size-cells"
allOf:
- if:
properties:
compatible:
contains:
const: ti,am437x-ocp2scp
then:
properties:
reg: false
else:
required:
- reg
additionalProperties:
type: object
examples:
- |
ocp2scp@4a0ad000 {
compatible = "ti,omap-ocp2scp";
reg = <0x4a0ad000 0x1f>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
phy@80 {
compatible = "ti,omap-usb2";
reg = <0x80 0x58>;
ctrl-module = <&omap_control_usb2phy>;
clocks = <&usb_phy_cm_clk32k>;
clock-names = "wkupclk";
#phy-cells = <0>;
};
};
Documentation/devicetree/bindings/clock/mediatek,apmixedsys.yaml
+1 -1
View File
@@ -26,7 +26,6 @@ properties:
- mediatek,mt7988-apmixedsys
- mediatek,mt8135-apmixedsys
- mediatek,mt8173-apmixedsys
- mediatek,mt8516-apmixedsys
- items:
- const: mediatek,mt7623-apmixedsys
- const: mediatek,mt2701-apmixedsys
@@ -42,6 +41,7 @@ properties:
- mediatek,mt7629-apmixedsys
- mediatek,mt8167-apmixedsys
- mediatek,mt8183-apmixedsys
- mediatek,mt8516-apmixedsys
- const: syscon
reg:
Documentation/devicetree/bindings/clock/mediatek,topckgen.yaml
+1 -1
View File
@@ -23,7 +23,6 @@ properties:
- mediatek,mt7622-topckgen
- mediatek,mt8135-topckgen
- mediatek,mt8173-topckgen
- mediatek,mt8516-topckgen
- items:
- const: mediatek,mt7623-topckgen
- const: mediatek,mt2701-topckgen
@@ -43,6 +42,7 @@ properties:
- mediatek,mt7988-topckgen
- mediatek,mt8167-topckgen
- mediatek,mt8183-topckgen
- mediatek,mt8516-topckgen
- const: syscon
reg:
Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml
+1 -1
View File
@@ -128,7 +128,7 @@ examples:
cvcc12-supply = <&v1v2_hdmi>;
#sound-dai-cells = <0>;
sil,i2s-data-lanes = < 0 1 2 >;
sil,i2s-data-lanes = <0 1 2>;
clocks = <&mclk>;
clock-names = "mclk";
Documentation/devicetree/bindings/display/hisilicon/dw-dsi.txt
-72
View File
@@ -1,72 +0,0 @@
Device-Tree bindings for DesignWare DSI Host Controller v1.20a driver
A DSI Host Controller resides in the middle of display controller and external
HDMI converter or panel.
Required properties:
- compatible: value should be "hisilicon,hi6220-dsi".
- reg: physical base address and length of dsi controller's registers.
- clocks: contains APB clock phandle + clock-specifier pair.
- clock-names: should be "pclk".
- ports: contains DSI controller input and output sub port.
The input port connects to ADE output port with the reg value "0".
The output port with the reg value "1", it could connect to panel or
any other bridge endpoints.
See Documentation/devicetree/bindings/graph.txt for more device graph info.
A example of HiKey board hi6220 SoC and board specific DT entry:
Example:
SoC specific:
dsi: dsi@f4107800 {
compatible = "hisilicon,hi6220-dsi";
reg = <0x0 0xf4107800 0x0 0x100>;
clocks = <&media_ctrl HI6220_DSI_PCLK>;
clock-names = "pclk";
status = "disabled";
ports {
#address-cells = <1>;
#size-cells = <0>;
/* 0 for input port */
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ade_out>;
};
};
};
};
Board specific:
&dsi {
status = "ok";
ports {
/* 1 for output port */
port@1 {
reg = <1>;
dsi_out0: endpoint@0 {
remote-endpoint = <&adv7533_in>;
};
};
};
};
&i2c2 {
...
adv7533: adv7533@39 {
...
port {
adv7533_in: endpoint {
remote-endpoint = <&dsi_out0>;
};
};
};
};
Documentation/devicetree/bindings/display/hisilicon/hisi-ade.txt
-64
View File
@@ -1,64 +0,0 @@
Device-Tree bindings for hisilicon ADE display controller driver
ADE (Advanced Display Engine) is the display controller which grab image
data from memory, do composition, do post image processing, generate RGB
timing stream and transfer to DSI.
Required properties:
- compatible: value should be "hisilicon,hi6220-ade".
- reg: physical base address and length of the ADE controller's registers.
- hisilicon,noc-syscon: ADE NOC QoS syscon.
- resets: The ADE reset controller node.
- interrupt: the ldi vblank interrupt number used.
- clocks: a list of phandle + clock-specifier pairs, one for each entry
in clock-names.
- clock-names: should contain:
"clk_ade_core" for the ADE core clock.
"clk_codec_jpeg" for the media NOC QoS clock, which use the same clock with
jpeg codec.
"clk_ade_pix" for the ADE pixel clock.
- assigned-clocks: Should contain "clk_ade_core" and "clk_codec_jpeg" clocks'
phandle + clock-specifier pairs.
- assigned-clock-rates: clock rates, one for each entry in assigned-clocks.
The rate of "clk_ade_core" could be "360000000" or "180000000";
The rate of "clk_codec_jpeg" could be or less than "1440000000".
These rate values could be configured according to performance and power
consumption.
- port: the output port. This contains one endpoint subnode, with its
remote-endpoint set to the phandle of the connected DSI input endpoint.
See Documentation/devicetree/bindings/graph.txt for more device graph info.
Optional properties:
- dma-coherent: Present if dma operations are coherent.
A example of HiKey board hi6220 SoC specific DT entry:
Example:
ade: ade@f4100000 {
compatible = "hisilicon,hi6220-ade";
reg = <0x0 0xf4100000 0x0 0x7800>;
reg-names = "ade_base";
hisilicon,noc-syscon = <&medianoc_ade>;
resets = <&media_ctrl MEDIA_ADE>;
interrupts = <0 115 4>; /* ldi interrupt */
clocks = <&media_ctrl HI6220_ADE_CORE>,
<&media_ctrl HI6220_CODEC_JPEG>,
<&media_ctrl HI6220_ADE_PIX_SRC>;
/*clock name*/
clock-names = "clk_ade_core",
"clk_codec_jpeg",
"clk_ade_pix";
assigned-clocks = <&media_ctrl HI6220_ADE_CORE>,
<&media_ctrl HI6220_CODEC_JPEG>;
assigned-clock-rates = <360000000>, <288000000>;
dma-coherent;
port {
ade_out: endpoint {
remote-endpoint = <&dsi_in>;
};
};
};
Documentation/devicetree/bindings/display/hisilicon/hisilicon,hi6220-ade.yaml
+95
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@@ -0,0 +1,95 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/hisilicon/hisilicon,hi6220-ade.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Hisilicon ADE Display Controller
maintainers:
- Xinliang Liu <z.liuxinliang@hisilicon.com>
description:
ADE (Advanced Display Engine) is the display controller which grab image
data from memory, do composition, do post image processing, generate RGB
timing stream and transfer to DSI.
properties:
compatible:
const: hisilicon,hi6220-ade
reg:
maxItems: 1
reg-names:
items:
- const: ade_base
clocks:
maxItems: 3
clock-names:
items:
- const: clk_ade_core
- const: clk_codec_jpeg
- const: clk_ade_pix
dma-coherent: true
interrupts:
items:
- description: LDI vblank interrupt specifier.
resets:
maxItems: 1
hisilicon,noc-syscon:
description: ADE NOC QoS syscon.
$ref: /schemas/types.yaml#/definitions/phandle
port:
$ref: /schemas/graph.yaml#/properties/port
description: Output port containing an endpoint subnode.
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- interrupts
- resets
- hisilicon,noc-syscon
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/hi6220-clock.h>
#include <dt-bindings/reset/hisi,hi6220-resets.h>
bus {
#address-cells = <2>;
#size-cells = <2>;
ade@f4100000 {
compatible = "hisilicon,hi6220-ade";
reg = <0x0 0xf4100000 0x0 0x7800>;
reg-names = "ade_base";
clocks = <&media_ctrl HI6220_ADE_CORE>,
<&media_ctrl HI6220_CODEC_JPEG>,
<&media_ctrl HI6220_ADE_PIX_SRC>;
clock-names = "clk_ade_core", "clk_codec_jpeg", "clk_ade_pix";
dma-coherent;
interrupts = <0 115 4>;
resets = <&media_ctrl MEDIA_ADE>;
hisilicon,noc-syscon = <&medianoc_ade>;
port {
endpoint {
remote-endpoint = <&dsi_in>;
};
};
};
};
Documentation/devicetree/bindings/display/hisilicon/hisilicon,hi6220-dsi.yaml
+68
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@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/hisilicon/hisilicon,hi6220-dsi.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon DesignWare DSI Host Controller
maintainers:
- Xinliang Liu <z.liuxinliang@hisilicon.com>
properties:
compatible:
const: hisilicon,hi6220-dsi
reg:
maxItems: 1
clocks:
maxItems: 1
clock-names:
items:
- const: pclk
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
description: Input port, connects to ADE output endpoint.
$ref: /schemas/graph.yaml#/properties/port
port@1:
description: Output port, connects to panel or bridge endpoints.
$ref: /schemas/graph.yaml#/properties/port
required:
- compatible
- reg
- clocks
- clock-names
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/hi6220-clock.h>
dsi@f4107800 {
compatible = "hisilicon,hi6220-dsi";
reg = <0xf4107800 0x100>;
clocks = <&media_ctrl HI6220_DSI_PCLK>;
clock-names = "pclk";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
dsi_in: endpoint {
remote-endpoint = <&ade_out>;
};
};
};
};
Documentation/devicetree/bindings/display/mediatek/mediatek,hdmi-ddc.yaml
+7 -4
View File
@@ -15,10 +15,13 @@ description: |
properties:
compatible:
enum:
- mediatek,mt7623-hdmi-ddc
- mediatek,mt8167-hdmi-ddc
- mediatek,mt8173-hdmi-ddc
oneOf:
- const: mediatek,mt8173-hdmi-ddc
- items:
- enum:
- mediatek,mt7623-hdmi-ddc
- mediatek,mt8167-hdmi-ddc
- const: mediatek,mt8173-hdmi-ddc
reg:
maxItems: 1
Documentation/devicetree/bindings/dts-coding-style.rst
+3 -2
View File
@@ -135,8 +135,9 @@ The above-described ordering follows this approach:
3. Status is the last information to annotate that device node is or is not
finished (board resources are needed).
The individual properties inside each group shall use natural sort order by
the property name.
The individual properties inside each group shall use usually natural sort
order by the property name, with exceptions of logical grouping of properties,
e.g. supplies.
Example::
Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.yaml
+2 -4
View File
@@ -18,11 +18,9 @@ description: |
which can create the interprocessor communication (IPC) between the
CPU and BPMP.
This node is a mailbox consumer. See the following files for details
of the mailbox subsystem, and the specifiers implemented by the
relevant provider(s):
This node is a mailbox consumer. See the following file for details
of the mailbox specifiers implemented by the relevant provider(s):
- .../mailbox/mailbox.txt
- .../mailbox/nvidia,tegra186-hsp.yaml
This node is a clock, power domain, and reset provider. See the
Documentation/devicetree/bindings/gpio/delta,tn48m-gpio.yaml
+1 -1
View File
@@ -14,7 +14,7 @@ description: |
details see ../mfd/delta,tn48m-cpld.yaml.
Delta TN48M has an onboard Lattice CPLD that is used as an GPIO expander.
It provides 12 pins in total, they are input-only or ouput-only type.
It provides 12 pins in total, they are input-only or output-only type.
properties:
compatible:
Documentation/devicetree/bindings/gpu/arm,mali-utgard.yaml
+24 -1
View File
@@ -112,7 +112,13 @@ properties:
maxItems: 1
resets:
maxItems: 1
minItems: 1
maxItems: 2
reset-names:
items:
- const: ao_g3d
- const: media_g3d
operating-points-v2: true
@@ -130,6 +136,23 @@ required:
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: hisilicon,hi6220-mali
then:
properties:
resets:
minItems: 2
required:
- reset-names
else:
properties:
resets:
maxItems: 1
reset-names: false
- if:
properties:
compatible:
Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+14 -3
View File
@@ -37,6 +37,12 @@ properties:
- const: img,img-rogue
- items:
- enum:
- spacemit,k1-gpu
- const: img,img-bxe-2-32
- const: img,img-rogue
- items:
- enum:
- spacemit,k3-gpu
- thead,th1520-gpu
- const: img,img-bxm-4-64
- const: img,img-rogue
@@ -102,6 +108,8 @@ allOf:
compatible:
contains:
enum:
- spacemit,k1-gpu
- spacemit,k3-gpu
- ti,am62-gpu
- ti,am62p-gpu
- ti,j721s2-gpu
@@ -162,13 +170,16 @@ allOf:
properties:
compatible:
contains:
const: thead,th1520-gpu
enum:
- spacemit,k1-gpu
- spacemit,k3-gpu
- thead,th1520-gpu
then:
properties:
power-domains:
items:
- description: The single, unified power domain for the GPU on the
TH1520 SoC, integrating all internal IP power domains.
- description: The single, unified power domain for the GPU,
integrating all internal IP power domains.
power-domain-names: false
required:
- power-domains
Documentation/devicetree/bindings/hwmon/adi,ltc2991.yaml
+1 -1
View File
@@ -49,7 +49,7 @@ patternProperties:
shunt-resistor-micro-ohms:
description:
The value of curent sense resistor in micro ohms. Pin configuration is
The value of current sense resistor in micro ohms. Pin configuration is
set for differential input pair.
adi,temperature-enable:
Documentation/devicetree/bindings/hwmon/vexpress.txt
-23
View File
@@ -1,23 +0,0 @@
Versatile Express hwmon sensors
-------------------------------
Requires node properties:
- "compatible" value : one of
"arm,vexpress-volt"
"arm,vexpress-amp"
"arm,vexpress-temp"
"arm,vexpress-power"
"arm,vexpress-energy"
- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
(see Documentation/devicetree/bindings/arm/vexpress-config.yaml
for more details)
Optional node properties:
- label : string describing the monitored value
Example:
energy@0 {
compatible = "arm,vexpress-energy";
arm,vexpress-sysreg,func = <13 0>;
label = "A15 Jcore";
};
Documentation/devicetree/bindings/i2c/xlnx,xps-iic-2.00.a.yaml
+2 -2
View File
@@ -52,8 +52,8 @@ examples:
axi_iic_0: i2c@40800000 {
compatible = "xlnx,xps-iic-2.00.a";
clocks = <&clkc 15>;
interrupts = < 1 2 >;
reg = < 0x40800000 0x10000 >;
interrupts = <1 2>;
reg = <0x40800000 0x10000>;
#size-cells = <0>;
#address-cells = <1>;
Documentation/devicetree/bindings/iio/light/upisemi,us5182.yaml
+1 -1
View File
@@ -69,7 +69,7 @@ examples:
light-sensor@39 {
compatible = "upisemi,usd5182";
reg = <0x39>;
upisemi,glass-coef = < 1000 >;
upisemi,glass-coef = <1000>;
upisemi,dark-ths = /bits/ 16 <170 200 512 512 800 2000 4000 8000>;
upisemi,upper-dark-gain = /bits/ 8 <0x00>;
upisemi,lower-dark-gain = /bits/ 8 <0x16>;
Documentation/devicetree/bindings/input/matrix-keymap.yaml
+1 -2
View File
@@ -41,8 +41,7 @@ examples:
- |
keypad {
/* ... */
linux,keymap = < 0x00030012
0x0102003a >;
linux,keymap = <0x00030012 0x0102003a>;
keypad,num-rows = <2>;
keypad,num-columns = <8>;
};
Documentation/devicetree/bindings/input/ti,tca8418.yaml
+10 -11
View File
@@ -46,16 +46,15 @@ examples:
interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
keypad,num-rows = <4>;
keypad,num-columns = <4>;
linux,keymap = < MATRIX_KEY(0x00, 0x01, BTN_0)
MATRIX_KEY(0x00, 0x00, BTN_1)
MATRIX_KEY(0x01, 0x01, BTN_2)
MATRIX_KEY(0x01, 0x00, BTN_3)
MATRIX_KEY(0x02, 0x00, BTN_4)
MATRIX_KEY(0x00, 0x03, BTN_5)
MATRIX_KEY(0x00, 0x02, BTN_6)
MATRIX_KEY(0x01, 0x03, BTN_7)
MATRIX_KEY(0x01, 0x02, BTN_8)
MATRIX_KEY(0x02, 0x02, BTN_9)
>;
linux,keymap = <MATRIX_KEY(0x00, 0x01, BTN_0)
MATRIX_KEY(0x00, 0x00, BTN_1)
MATRIX_KEY(0x01, 0x01, BTN_2)
MATRIX_KEY(0x01, 0x00, BTN_3)
MATRIX_KEY(0x02, 0x00, BTN_4)
MATRIX_KEY(0x00, 0x03, BTN_5)
MATRIX_KEY(0x00, 0x02, BTN_6)
MATRIX_KEY(0x01, 0x03, BTN_7)
MATRIX_KEY(0x01, 0x02, BTN_8)
MATRIX_KEY(0x02, 0x02, BTN_9)>;
};
};
Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml
+4 -3
View File
@@ -12,8 +12,9 @@ maintainers:
description:
This binding specifies what properties must be available in the device tree
representation of an Open PIC compliant interrupt controller. This binding is
based on the binding defined for Open PIC in [1] and is a superset of that
binding.
based on the binding defined for Open PIC in the Devicetree Specification
(available from https://www.devicetree.org/specifications/) and is a superset
of that binding.
properties:
compatible:
@@ -24,7 +25,7 @@ properties:
- const: chrp,open-pic
device_type:
const: open-pci
const: open-pic
deprecated: true
reg:
Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml
+2
View File
@@ -30,6 +30,7 @@ properties:
- qcom,glymur-pdc
- qcom,hawi-pdc
- qcom,kaanapali-pdc
- qcom,kuno-pdc
- qcom,maili-pdc
- qcom,milos-pdc
- qcom,nord-pdc
@@ -50,6 +51,7 @@ properties:
- qcom,sdx75-pdc
- qcom,sm4450-pdc
- qcom,sm6350-pdc
- qcom,sm7250-pdc
- qcom,sm8150-pdc
- qcom,sm8250-pdc
- qcom,sm8350-pdc
Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+17 -1
View File
@@ -100,7 +100,10 @@ properties:
maxItems: 1
interrupts:
maxItems: 1
minItems: 1
maxItems: 5
description:
A single interrupt or one interrupt per bank.
clocks:
items:
@@ -155,6 +158,19 @@ required:
- '#iommu-cells'
allOf:
- if:
properties:
compatible:
contains:
const: mediatek,mt8195-iommu-infra
then:
properties:
interrupts:
minItems: 5
else:
properties:
interrupts:
maxItems: 1
- if:
properties:
compatible:
Documentation/devicetree/bindings/mailbox/allwinner,sun6i-a31-msgbox.yaml
-3
View File
@@ -17,9 +17,6 @@ description: |
hold four 32-bit messages; when a FIFO is full, clients must wait before
attempting more transmissions.
Refer to ./mailbox.txt for generic information about mailbox device-tree
bindings.
properties:
compatible:
oneOf:
Documentation/devicetree/bindings/mailbox/altera-mailbox.txt
+6 -6
View File
@@ -31,12 +31,12 @@ Example:
Mailbox client
===============
"mboxes" and the optional "mbox-names" (please see
Documentation/devicetree/bindings/mailbox/mailbox.txt for details). Each value
of the mboxes property should contain a phandle to the mailbox controller
device node and second argument is the channel index. It must be 0 (hardware
support only one channel).The equivalent "mbox-names" property value can be
used to give a name to the communication channel to be used by the client user.
The common mailbox binding properties "mboxes" and the optional "mbox-names"
can be used. Each value of the mboxes property should contain a phandle to
the mailbox controller device node and second argument is the channel index.
It must be 0 (hardware support only one channel). The equivalent "mbox-names"
property value can be used to give a name to the communication channel to be
used by the client user.
Example:
mclient0: mclient0@400 {
Documentation/devicetree/bindings/mailbox/mailbox.txt
-60
View File
@@ -1,60 +0,0 @@
* Generic Mailbox Controller and client driver bindings
Generic binding to provide a way for Mailbox controller drivers to
assign appropriate mailbox channel to client drivers.
* Mailbox Controller
Required property:
- #mbox-cells: Must be at least 1. Number of cells in a mailbox
specifier.
Example:
mailbox: mailbox {
...
#mbox-cells = <1>;
};
* Mailbox Client
Required property:
- mboxes: List of phandle and mailbox channel specifiers.
Optional property:
- mbox-names: List of identifier strings for each mailbox channel.
- shmem : List of phandle pointing to the shared memory(SHM) area between the
users of these mailboxes for IPC, one for each mailbox. This shared
memory can be part of any memory reserved for the purpose of this
communication between the mailbox client and the remote.
Example:
pwr_cntrl: power {
...
mbox-names = "pwr-ctrl", "rpc";
mboxes = <&mailbox 0 &mailbox 1>;
};
Example with shared memory(shmem):
sram: sram@50000000 {
compatible = "mmio-sram";
reg = <0x50000000 0x10000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x50000000 0x10000>;
cl_shmem: shmem@0 {
compatible = "client-shmem";
reg = <0x0 0x200>;
};
};
client@2e000000 {
...
mboxes = <&mailbox 0>;
shmem = <&cl_shmem>;
..
};
Documentation/devicetree/bindings/mailbox/ti,omap-mailbox.yaml
+1 -2
View File
@@ -53,8 +53,7 @@ description: |
==============
A device needing to communicate with a target processor device should specify
them using the common mailbox binding properties, "mboxes" and the optional
"mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
for details). Each value of the mboxes property should contain a phandle to
"mbox-names". Each value of the mboxes property should contain a phandle to
the mailbox controller device node and an args specifier that will be the
phandle to the intended sub-mailbox child node to be used for communication.
The equivalent "mbox-names" property value can be used to give a name to the
Documentation/devicetree/bindings/media/amlogic,c3-mipi-csi2.yaml
+2 -2
View File
@@ -96,8 +96,8 @@ examples:
<0x0 0xff01a000 0x0 0x100>;
reg-names = "aphy", "dphy", "host";
power-domains = <&pwrc PWRC_C3_MIPI_ISP_WRAP_ID>;
clocks = <&clkc_periphs CLKID_VAPB>,
<&clkc_periphs CLKID_CSI_PHY0>;
clocks = <&clkc_periphs CLKID_VAPB>,
<&clkc_periphs CLKID_CSI_PHY0>;
clock-names = "vapb", "phy0";
assigned-clocks = <&clkc_periphs CLKID_VAPB>,
<&clkc_periphs CLKID_CSI_PHY0>;
Documentation/devicetree/bindings/media/arm,mali-c55.yaml
+1 -1
View File
@@ -79,7 +79,7 @@ examples:
port {
isp_in: endpoint {
remote-endpoint = <&csi2_rx_out>;
remote-endpoint = <&csi2_rx_out>;
};
};
};
Documentation/devicetree/bindings/media/atmel,isc.yaml
+7 -7
View File
@@ -102,12 +102,12 @@ examples:
clock-output-names = "isc-mck";
port {
isc_0: endpoint {
remote-endpoint = <&ov7740_0>;
hsync-active = <1>;
vsync-active = <0>;
pclk-sample = <1>;
bus-width = <8>;
};
isc_0: endpoint {
remote-endpoint = <&ov7740_0>;
hsync-active = <1>;
vsync-active = <0>;
pclk-sample = <1>;
bus-width = <8>;
};
};
};
Documentation/devicetree/bindings/media/brcm,bcm2835-unicam.yaml
+5 -5
View File
@@ -117,11 +117,11 @@ examples:
power-domains = <&power RPI_POWER_DOMAIN_UNICAM1>;
brcm,num-data-lanes = <2>;
port {
csi1_ep: endpoint {
remote-endpoint = <&imx219_0>;
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
data-lanes = <1 2>;
};
csi1_ep: endpoint {
remote-endpoint = <&imx219_0>;
bus-type = <MEDIA_BUS_TYPE_CSI2_DPHY>;
data-lanes = <1 2>;
};
};
};
...
Documentation/devicetree/bindings/media/cdns,csi2rx.yaml
+29 -29
View File
@@ -160,50 +160,50 @@ examples:
phy-names = "dphy";
ports {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
port@0 {
reg = <0>;
csi2rx_in_sensor: endpoint {
remote-endpoint = <&sensor_out_csi2rx>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
csi2rx_in_sensor: endpoint {
remote-endpoint = <&sensor_out_csi2rx>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
csi2rx_out_grabber0: endpoint {
remote-endpoint = <&grabber0_in_csi2rx>;
};
csi2rx_out_grabber0: endpoint {
remote-endpoint = <&grabber0_in_csi2rx>;
};
};
port@2 {
reg = <2>;
port@2 {
reg = <2>;
csi2rx_out_grabber1: endpoint {
remote-endpoint = <&grabber1_in_csi2rx>;
};
csi2rx_out_grabber1: endpoint {
remote-endpoint = <&grabber1_in_csi2rx>;
};
};
port@3 {
reg = <3>;
port@3 {
reg = <3>;
csi2rx_out_grabber2: endpoint {
remote-endpoint = <&grabber2_in_csi2rx>;
};
csi2rx_out_grabber2: endpoint {
remote-endpoint = <&grabber2_in_csi2rx>;
};
};
port@4 {
reg = <4>;
port@4 {
reg = <4>;
csi2rx_out_grabber3: endpoint {
remote-endpoint = <&grabber3_in_csi2rx>;
};
csi2rx_out_grabber3: endpoint {
remote-endpoint = <&grabber3_in_csi2rx>;
};
};
};
};
Documentation/devicetree/bindings/media/hisilicon,hix5hd2-ir.yaml
+52
View File
@@ -0,0 +1,52 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/hisilicon,hix5hd2-ir.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon HIX5HD2 IR controller
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
allOf:
- $ref: rc.yaml#
properties:
compatible:
items:
- enum:
- hisilicon,hix5hd2-ir
- hisilicon,hi3796cv300-ir
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
maxItems: 1
hisilicon,power-syscon:
description: Provide correct clocks instead.
$ref: /schemas/types.yaml#/definitions/phandle
deprecated: true
required:
- compatible
- reg
- interrupts
- clocks
unevaluatedProperties: false
examples:
- |
ir@f8001000 {
compatible = "hisilicon,hix5hd2-ir";
reg = <0xf8001000 0x1000>;
interrupts = <0 47 4>;
clocks = <&clock 0>;
linux,rc-map-name = "rc-tivo";
};
Documentation/devicetree/bindings/media/hix5hd2-ir.txt
-26
View File
@@ -1,26 +0,0 @@
Device-Tree bindings for hix5hd2 ir IP
Required properties:
- compatible: Should contain "hisilicon,hix5hd2-ir", or:
- "hisilicon,hi3796cv300-ir" for Hi3796CV300 IR device.
- reg: Base physical address of the controller and length of memory
mapped region.
- interrupts: interrupt-specifier for the sole interrupt generated by
the device. The interrupt specifier format depends on the interrupt
controller parent.
- clocks: clock phandle and specifier pair.
Optional properties:
- linux,rc-map-name: see rc.txt file in the same directory.
- hisilicon,power-syscon: DEPRECATED. Don't use this in new dts files.
Provide correct clocks instead.
Example node:
ir: ir@f8001000 {
compatible = "hisilicon,hix5hd2-ir";
reg = <0xf8001000 0x1000>;
interrupts = <0 47 4>;
clocks = <&clock HIX5HD2_IR_CLOCK>;
linux,rc-map-name = "rc-tivo";
};
Documentation/devicetree/bindings/media/i2c/galaxycore,gc05a2.yaml
+1 -1
View File
@@ -88,7 +88,7 @@ examples:
#size-cells = <0>;
sensor@37 {
compatible = "galaxycore,gc05a2";
compatible = "galaxycore,gc05a2";
reg = <0x37>;
clocks = <&gc05a2_clk>;
Documentation/devicetree/bindings/media/i2c/ovti,ov2680.yaml
+13 -13
View File
@@ -90,22 +90,22 @@ examples:
#size-cells = <0>;
ov2680: camera-sensor@36 {
compatible = "ovti,ov2680";
reg = <0x36>;
clocks = <&osc>;
clock-names = "xvclk";
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
compatible = "ovti,ov2680";
reg = <0x36>;
clocks = <&osc>;
clock-names = "xvclk";
reset-gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
DOVDD-supply = <&sw2_reg>;
DVDD-supply = <&sw2_reg>;
AVDD-supply = <&reg_peri_3p15v>;
DOVDD-supply = <&sw2_reg>;
DVDD-supply = <&sw2_reg>;
AVDD-supply = <&reg_peri_3p15v>;
port {
ov2680_to_mipi: endpoint {
remote-endpoint = <&mipi_from_sensor>;
link-frequencies = /bits/ 64 <330000000>;
};
port {
ov2680_to_mipi: endpoint {
remote-endpoint = <&mipi_from_sensor>;
link-frequencies = /bits/ 64 <330000000>;
};
};
};
};
Documentation/devicetree/bindings/media/i2c/ovti,ov2732.yaml
+3 -3
View File
@@ -94,9 +94,9 @@ examples:
port {
camera_out: endpoint {
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <360000000>;
remote-endpoint = <&mipi_in_camera>;
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <360000000>;
remote-endpoint = <&mipi_in_camera>;
};
};
};
Documentation/devicetree/bindings/media/img,e5010-jpeg-enc.yaml
+11 -11
View File
@@ -61,15 +61,15 @@ examples:
#include <dt-bindings/interrupt-controller/irq.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
jpeg-encoder@fd20000 {
compatible = "img,e5010-jpeg-enc";
reg = <0x00 0xfd20000 0x00 0x100>,
<0x00 0xfd20200 0x00 0x200>;
reg-names = "core", "mmu";
clocks = <&k3_clks 201 0>;
power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
#address-cells = <2>;
#size-cells = <2>;
jpeg-encoder@fd20000 {
compatible = "img,e5010-jpeg-enc";
reg = <0x00 0xfd20000 0x00 0x100>,
<0x00 0xfd20200 0x00 0x200>;
reg-names = "core", "mmu";
clocks = <&k3_clks 201 0>;
power-domains = <&k3_pds 201 TI_SCI_PD_EXCLUSIVE>;
interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
};
};
Documentation/devicetree/bindings/media/mediatek,vcodec-encoder.yaml
+1 -1
View File
@@ -160,7 +160,7 @@ examples:
vcodec_enc_vp8: vcodec@19002000 {
compatible = "mediatek,mt8173-vcodec-enc-vp8";
reg = <0x19002000 0x1000>; /* VENC_LT_SYS */
reg = <0x19002000 0x1000>; /* VENC_LT_SYS */
interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_LOW>;
iommus = <&iommu M4U_PORT_VENC_RCPU_SET2>,
<&iommu M4U_PORT_VENC_REC_FRM_SET2>,
Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml
+2 -2
View File
@@ -106,8 +106,8 @@ examples:
compatible = "mediatek,mt2701-jpgdec";
reg = <0x15004000 0x1000>;
interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clocks = <&imgsys CLK_IMG_JPGDEC_SMI>,
<&imgsys CLK_IMG_JPGDEC>;
clock-names = "jpgdec-smi",
"jpgdec";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml
+1 -1
View File
@@ -93,7 +93,7 @@ examples:
"mediatek,mtk-jpgenc";
reg = <0x1500a000 0x1000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_LOW>;
clocks = <&imgsys CLK_IMG_VENC>;
clocks = <&imgsys CLK_IMG_VENC>;
clock-names = "jpgenc";
power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>;
iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>,
Documentation/devicetree/bindings/media/microchip,csi2dc.yaml
+26 -26
View File
@@ -149,22 +149,22 @@ examples:
clock-names = "pclk", "scck";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>; /* must be 0, first child port */
csi2dc_in: endpoint { /* input from IDI interface */
bus-type = <4>; /* MIPI CSI2 D-PHY */
remote-endpoint = <&csi2host_out>;
};
};
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>; /* must be 0, first child port */
csi2dc_in: endpoint { /* input from IDI interface */
bus-type = <4>; /* MIPI CSI2 D-PHY */
remote-endpoint = <&csi2host_out>;
};
};
port@1 {
reg = <1>; /* must be 1, second child port */
csi2dc_out: endpoint {
remote-endpoint = <&xisc_in>; /* output to sensor controller */
};
};
port@1 {
reg = <1>; /* must be 1, second child port */
csi2dc_out: endpoint {
remote-endpoint = <&xisc_in>; /* output to sensor controller */
};
};
};
};
@@ -181,18 +181,18 @@ examples:
dma-names = "rx";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>; /* must be 0, first child port */
csi2dc_input: endpoint { /* input from IDI interface */
remote-endpoint = <&csi2host_out>;
};
};
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>; /* must be 0, first child port */
csi2dc_input: endpoint { /* input from IDI interface */
remote-endpoint = <&csi2host_out>;
};
};
port@1 {
reg = <1>;
};
port@1 {
reg = <1>;
};
};
};
Documentation/devicetree/bindings/media/microchip,xisc.yaml
+7 -7
View File
@@ -118,12 +118,12 @@ examples:
clock-output-names = "isc-mck";
port {
xisc_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
remote-endpoint = <&csi2dc_out>;
hsync-active = <1>;
vsync-active = <1>;
bus-width = <12>;
};
xisc_in: endpoint {
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
remote-endpoint = <&csi2dc_out>;
hsync-active = <1>;
vsync-active = <1>;
bus-width = <12>;
};
};
};
Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml
+2 -2
View File
@@ -95,7 +95,7 @@ examples:
jpegdec: jpegdec@58400000 {
compatible = "nxp,imx8qxp-jpgdec";
reg = <0x58400000 0x00050000 >;
reg = <0x58400000 0x00050000>;
clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
@@ -111,7 +111,7 @@ examples:
jpegenc: jpegenc@58450000 {
compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
reg = <0x58450000 0x00050000 >;
reg = <0x58450000 0x00050000>;
clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
<&img_jpeg__lpcg IMX_LPCG_CLK_4>;
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
Documentation/devicetree/bindings/media/qcom,msm8996-venus.yaml
+20 -20
View File
@@ -119,26 +119,26 @@ examples:
<&mmcc VIDEO_MAXI_CLK>;
clock-names = "core", "iface", "bus", "mbus";
power-domains = <&mmcc VENUS_GDSC>;
iommus = <&venus_smmu 0x00>,
<&venus_smmu 0x01>,
<&venus_smmu 0x0a>,
<&venus_smmu 0x07>,
<&venus_smmu 0x0e>,
<&venus_smmu 0x0f>,
<&venus_smmu 0x08>,
<&venus_smmu 0x09>,
<&venus_smmu 0x0b>,
<&venus_smmu 0x0c>,
<&venus_smmu 0x0d>,
<&venus_smmu 0x10>,
<&venus_smmu 0x11>,
<&venus_smmu 0x21>,
<&venus_smmu 0x28>,
<&venus_smmu 0x29>,
<&venus_smmu 0x2b>,
<&venus_smmu 0x2c>,
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
iommus = <&venus_smmu 0x00>,
<&venus_smmu 0x01>,
<&venus_smmu 0x0a>,
<&venus_smmu 0x07>,
<&venus_smmu 0x0e>,
<&venus_smmu 0x0f>,
<&venus_smmu 0x08>,
<&venus_smmu 0x09>,
<&venus_smmu 0x0b>,
<&venus_smmu 0x0c>,
<&venus_smmu 0x0d>,
<&venus_smmu 0x10>,
<&venus_smmu 0x11>,
<&venus_smmu 0x21>,
<&venus_smmu 0x28>,
<&venus_smmu 0x29>,
<&venus_smmu 0x2b>,
<&venus_smmu 0x2c>,
<&venus_smmu 0x2d>,
<&venus_smmu 0x31>;
memory-region = <&venus_mem>;
video-decoder {
Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
+13 -13
View File
@@ -302,19 +302,19 @@ examples:
"vfe_lite_cphy_rx",
"vfe_lite_csid";
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 466 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 468 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 359 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 465 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 467 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 469 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 360 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid0",
"csid1",
Documentation/devicetree/bindings/media/raspberrypi,pispbe.yaml
+6 -6
View File
@@ -53,11 +53,11 @@ examples:
#address-cells = <2>;
#size-cells = <2>;
isp@880000 {
compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe";
reg = <0x10 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&firmware_clocks 7>;
iommus = <&iommu2>;
isp@880000 {
compatible = "brcm,bcm2712-pispbe", "raspberrypi,pispbe";
reg = <0x10 0x00880000 0x0 0x4000>;
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&firmware_clocks 7>;
iommus = <&iommu2>;
};
};
Documentation/devicetree/bindings/media/rc.txt
-1
View File
@@ -1 +0,0 @@
This file has been moved to rc.yaml.
Documentation/devicetree/bindings/media/samsung,fimc.yaml
+7 -7
View File
@@ -188,13 +188,13 @@ examples:
/* ... CSIS 1 */
fimc-lite@b90000 {
compatible = "samsung,exynos4212-fimc-lite";
reg = <0xb90000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
clock-names = "flite";
iommus = <&sysmmu_fimc_lite0>;
compatible = "samsung,exynos4212-fimc-lite";
reg = <0xb90000 0x1000>;
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&pd_isp>;
clocks = <&isp_clock CLK_ISP_FIMC_LITE0>;
clock-names = "flite";
iommus = <&sysmmu_fimc_lite0>;
};
/* ... FIMC-LITE 1 */
Documentation/devicetree/bindings/media/st,stm32-dcmi.yaml
+8 -8
View File
@@ -120,14 +120,14 @@ examples:
dma-names = "tx";
port {
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
dcmi_0: endpoint {
remote-endpoint = <&ov5640_0>;
bus-type = <MEDIA_BUS_TYPE_PARALLEL>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <1>;
};
};
};
Documentation/devicetree/bindings/media/st,stm32-dcmipp.yaml
+7 -7
View File
@@ -120,13 +120,13 @@ examples:
clocks = <&rcc DCMIPP_K>;
port {
endpoint {
remote-endpoint = <&mipid02_2>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <0>;
};
endpoint {
remote-endpoint = <&mipid02_2>;
bus-width = <8>;
hsync-active = <0>;
vsync-active = <0>;
pclk-sample = <0>;
};
};
};
Documentation/devicetree/bindings/media/ti,cal.yaml
+24 -24
View File
@@ -136,17 +136,17 @@ examples:
ti,camerrx-control = <&scm_conf 0xE94>;
ports {
#address-cells = <1>;
#size-cells = <0>;
#address-cells = <1>;
#size-cells = <0>;
csi2_0: port@0 {
reg = <0>;
csi2_phy0: endpoint {
remote-endpoint = <&csi2_cam0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
csi2_0: port@0 {
reg = <0>;
csi2_phy0: endpoint {
remote-endpoint = <&csi2_cam0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
@@ -156,21 +156,21 @@ examples:
#size-cells = <0>;
camera-sensor@3c {
compatible = "ovti,ov5640";
reg = <0x3c>;
AVDD-supply = <&reg_2p8v>;
DOVDD-supply = <&reg_1p8v>;
DVDD-supply = <&reg_1p5v>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
compatible = "ovti,ov5640";
reg = <0x3c>;
AVDD-supply = <&reg_2p8v>;
DOVDD-supply = <&reg_1p8v>;
DVDD-supply = <&reg_1p5v>;
clocks = <&clk_ov5640_fixed>;
clock-names = "xclk";
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2_phy0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
port {
csi2_cam0: endpoint {
remote-endpoint = <&csi2_phy0>;
clock-lanes = <0>;
data-lanes = <1 2>;
};
};
};
};
Documentation/devicetree/bindings/mfd/ti,tps65910.yaml
+1 -1
View File
@@ -214,7 +214,7 @@ examples:
compatible = "ti,tps65910";
reg = <0x2d>;
interrupt-parent = <&intc>;
interrupts = < 0 118 0x04 >;
interrupts = <0 118 0x04>;
#gpio-cells = <2>;
gpio-controller;
Documentation/devicetree/bindings/mux/reg-mux.yaml
+1 -1
View File
@@ -22,7 +22,7 @@ properties:
reg: true
'#mux-control-cells':
const: 1
enum: [ 0, 1 ]
mux-reg-masks:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
Documentation/devicetree/bindings/nvmem/zii,rave-sp-eeprom.yaml
+1 -1
View File
@@ -27,7 +27,7 @@ properties:
$ref: /schemas/types.yaml#/definitions/string
description:
Unique EEPROM identifier describing its function in the
system. Will be used as created NVMEM deivce's name.
system. Will be used as created NVMEM device's name.
required:
- compatible
Documentation/devicetree/bindings/pci/hisilicon,kirin-pcie.yaml
+2 -2
View File
@@ -160,7 +160,7 @@ examples:
reg = <0x2800 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
reset-gpios = <&gpio27 4 0 >;
reset-gpios = <&gpio27 4 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
@@ -170,7 +170,7 @@ examples:
reg = <0x03800 0 0 0 0>;
compatible = "pciclass,0604";
device_type = "pci";
reset-gpios = <&gpio25 2 0 >;
reset-gpios = <&gpio25 2 0>;
#address-cells = <3>;
#size-cells = <2>;
ranges;
Documentation/devicetree/bindings/phy/st,stm32-usb2phy.yaml
+68
View File
@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/phy/st,stm32-usb2phy.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 MPU High-Speed USB PHY
description:
USB2 PHY block in STM32 is attached to USB 2.0 Host controller and
USB 2.0 side of DWC3 DRD controller, and provides the USB LS/FS/HS
connectivity. Both PHYs are the FEMTO-PHY, but their configuration
bits in the system control register are different for each variant.
maintainers:
- Fabrice Gasnier <fabrice.gasnier@foss.st.com>
- Marek Vasut <marex@nabladev.com>
- Pankaj Dev <pankaj.dev@st.com>
properties:
compatible:
enum:
- st,stm32mp25-usb2phy1
- st,stm32mp25-usb2phy2
reg:
maxItems: 1
clocks:
maxItems: 1
resets:
maxItems: 1
vdd33-supply:
description: Phandle to regulator providing 3V3 power supply to the USB2 HS PHY
"#clock-cells":
const: 1
"#phy-cells":
const: 0
required:
- compatible
- reg
- clocks
- resets
- vdd33-supply
- "#clock-cells"
- "#phy-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
usb-phy@2400 {
compatible = "st,stm32mp25-usb2phy1";
reg = <0x2400 0x24>;
#phy-cells = <0>;
#clock-cells = <1>;
clocks = <&rcc CK_KER_USB2PHY1>;
resets = <&rcc USB2PHY1_R>;
vdd33-supply = <&vdd33usb>;
};
Documentation/devicetree/bindings/pinctrl/sunplus,sp7021-pinctrl.yaml
+1 -1
View File
@@ -339,7 +339,7 @@ examples:
sdcard-pins {
function = "SD_CARD";
groups = "SD_CARD";
sunplus,pins = < SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0) >;
sunplus,pins = <SPPCTL_IOPAD(91, SPPCTL_PCTL_G_GPIO, 0, 0)>;
};
hdmi_A_tx1-pins {
Documentation/devicetree/bindings/power/mediatek,mt2701-scpsys.yaml
+184
View File
@@ -0,0 +1,184 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/power/mediatek,mt2701-scpsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek SCPSYS
maintainers:
- Matthias Brugger <matthias.bgg@gmail.com>
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
description: >
The System Control Processor System (SCPSYS) has several power management
related tasks in the system. The tasks include thermal measurement, dynamic
voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
domain control.
It provides the power domains defined in:
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt7622-power.h
- include/dt-bindings/power/mt7623a-power.h
properties:
compatible:
oneOf:
- enum:
- mediatek,mt7623a-scpsys
- mediatek,mt6797-scpsys
- items:
- enum:
- mediatek,mt2701-scpsys
- mediatek,mt2712-scpsys
- mediatek,mt7622-scpsys
- const: syscon
- items:
- const: mediatek,mt7623-scpsys
- const: mediatek,mt2701-scpsys
- const: syscon
- items:
- const: mediatek,mt7629-scpsys
- const: mediatek,mt7622-scpsys
'#power-domain-cells':
description: Always 1
const: 1
reg:
maxItems: 1
interrupts:
maxItems: 4
clocks:
minItems: 1
maxItems: 20
clock-names:
minItems: 1
maxItems: 6
items:
enum:
- mm
- mfg
- ethif
- venc
- jpgdec
- audio
- vdec
- hif_sel
vdec-supply: true
venc-supply: true
isp-supply: true
mm-supply: true
audio-supply: true
usb-supply: true
mfg_async-supply: true
mfg-supply: true
infracfg:
description: Infrastructure configuration controller phandle
$ref: /schemas/types.yaml#/definitions/phandle
required:
- compatible
- '#power-domain-cells'
- reg
- infracfg
- clocks
- clock-names
additionalProperties: false
allOf:
- if:
properties:
compatible:
contains:
const: mediatek,mt2701-scpsys
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: mm
- const: mfg
- const: ethif
- if:
properties:
compatible:
contains:
const: mediatek,mt7623a-scpsys
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: ethif
- if:
properties:
compatible:
contains:
const: mediatek,mt2712-scpsys
then:
properties:
clocks:
minItems: 6
clock-names:
items:
- const: mm
- const: mfg
- const: venc
- const: jpgdec
- const: audio
- const: vdec
- if:
properties:
compatible:
contains:
const: mediatek,mt7622-scpsys
then:
properties:
clocks:
maxItems: 1
clock-names:
items:
- const: hif_sel
- if:
properties:
compatible:
contains:
const: mediatek,mt6797-scpsys
then:
properties:
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: mfg
- const: mm
- const: vdec
examples:
- |
#include <dt-bindings/clock/mt2701-clk.h>
power-controller@10006000 {
#power-domain-cells = <1>;
compatible = "mediatek,mt2701-scpsys", "syscon";
reg = <0x10006000 0x1000>;
infracfg = <&infracfg>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&topckgen CLK_TOP_MFG_SEL>,
<&topckgen CLK_TOP_ETHIF_SEL>;
clock-names = "mm", "mfg", "ethif";
};
Documentation/devicetree/bindings/power/reset/xlnx,zynqmp-power.yaml
+3 -6
View File
@@ -27,12 +27,9 @@ properties:
mailbox controller device node and an args specifier
that will be the phandle to the intended sub-mailbox
child node to be used for communication. See
Documentation/devicetree/bindings/mailbox/mailbox.txt
for more details about the generic mailbox controller
and client driver bindings. Also see
Documentation/devicetree/bindings/mailbox/ \
xlnx,zynqmp-ipi-mailbox.txt for typical controller that
is used to communicate with this System controllers.
Documentation/devicetree/bindings/mailbox/xlnx,zynqmp-ipi-mailbox.yaml
for typical controller that is used to communicate with
this System controllers.
items:
- description: tx channel
- description: rx channel
Documentation/devicetree/bindings/regulator/vexpress.txt
-32
View File
@@ -1,32 +0,0 @@
Versatile Express voltage regulators
------------------------------------
Requires node properties:
- "compatible" value: "arm,vexpress-volt"
- "arm,vexpress-sysreg,func" when controlled via vexpress-sysreg
(see Documentation/devicetree/bindings/arm/vexpress-config.yaml
for more details)
Required regulator properties:
- "regulator-name"
- "regulator-always-on"
Optional regulator properties:
- "regulator-min-microvolt"
- "regulator-max-microvolt"
See Documentation/devicetree/bindings/regulator/regulator.txt
for more details about the regulator properties.
When no "regulator-[min|max]-microvolt" properties are defined,
the device is treated as fixed (or rather "read-only") regulator.
Example:
volt@0 {
compatible = "arm,vexpress-volt";
arm,vexpress-sysreg,func = <2 0>;
regulator-name = "Cores";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1050000>;
regulator-always-on;
};
Documentation/devicetree/bindings/reset/st,stm32-rcc.txt
-6
View File
@@ -1,6 +0,0 @@
STMicroelectronics STM32 Peripheral Reset Controller
====================================================
The RCC IP is both a reset and a clock controller.
Please see Documentation/devicetree/bindings/clock/st,stm32-rcc.yaml
Documentation/devicetree/bindings/reset/st,stm32mp1-rcc.txt
-6
View File
@@ -1,6 +0,0 @@
STMicroelectronics STM32MP1 Peripheral Reset Controller
=======================================================
The RCC IP is both a reset and a clock controller.
Please see Documentation/devicetree/bindings/clock/st,stm32mp1-rcc.yaml
Documentation/devicetree/bindings/scsi/hisilicon,hip05-sas-v1.yaml
+158
View File
@@ -0,0 +1,158 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/scsi/hisilicon,hip05-sas-v1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon SAS controller
maintainers:
- Xingui Yang <yangxingui@huawei.com>
properties:
compatible:
items:
- enum:
- hisilicon,hip05-sas-v1
- hisilicon,hip06-sas-v2
- hisilicon,hip07-sas-v2
reg:
minItems: 1
items:
- description: SAS registers
- description: CPLD SGPIO control registers
clocks:
minItems: 1
maxItems: 2
dma-coherent: true
interrupts:
description: >
Interrupt specifiers for PHY, SATA, and completion queues; ordering and
number depend on controller version.
For v1 hw: Interrupts for phys, completion queues, and fatal
sources; the interrupts are ordered in 3 groups, as follows:
- Phy interrupts - Each phy has 3 interrupt sources:
- broadcast
- phyup
- abnormal
The phy interrupts are ordered into groups of 3 per phy
(broadcast, phyup, and abnormal) in increasing order.
- Completion queue interrupts - each completion queue has 1 interrupt
source.
- Fatal interrupts - the fatal interrupts are ordered as follows:
- ECC
- AXI bus
For v2 hw: Interrupts for phys, Sata, and completion queues;
the interrupts are ordered in 3 groups, as follows:
- Phy interrupts - Each controller has 2 phy interrupts:
- phy up/down
- channel interrupt
- Sata interrupts - Each phy on the controller has 1 Sata interrupt.
- Completion queue interrupts - each completion queue has 1 interrupt
source
minItems: 58
maxItems: 128
ctrl-reset-reg:
description: Offset to controller reset register in SAS syscon region.
$ref: /schemas/types.yaml#/definitions/uint32
ctrl-reset-sts-reg:
description: Offset to controller reset status register in SAS syscon region.
$ref: /schemas/types.yaml#/definitions/uint32
ctrl-clock-ena-reg:
description: Offset to controller clock enable register in SAS syscon region.
$ref: /schemas/types.yaml#/definitions/uint32
hip06-sas-v2-quirk-amt:
description:
Indicates that the v2 controller has the "am-max-transmissions" limitation.
type: boolean
hisilicon,sas-syscon:
description: Phandle of syscon used for SAS control.
$ref: /schemas/types.yaml#/definitions/phandle
hisilicon,signal-attenuation:
description:
De-emphasis, preshoot, and boost attenuation readings for the board,
used to calculate signal attenuation (y = (x-10000)/10000).
$ref: /schemas/types.yaml#/definitions/uint32-array
minItems: 3
maxItems: 3
items:
minimum: 7600
maximum: 12400
phy-count:
description: Number of PHYs accessible by the controller.
$ref: /schemas/types.yaml#/definitions/uint32
queue-count:
description: Number of delivery and completion queues in the controller.
$ref: /schemas/types.yaml#/definitions/uint32
sas-addr:
description: SAS address, array of 8 bytes representing host SAS address.
$ref: /schemas/types.yaml#/definitions/uint8-array
minItems: 8
maxItems: 8
required:
- compatible
- reg
- interrupts
- ctrl-reset-reg
- ctrl-reset-sts-reg
- ctrl-clock-ena-reg
- hisilicon,sas-syscon
- phy-count
- queue-count
- sas-addr
additionalProperties: false
examples:
- |
sas@c1000000 {
compatible = "hisilicon,hip05-sas-v1";
reg = <0xc1000000 0x10000>;
dma-coherent;
interrupts = <259 4>, <263 4>, <264 4>, /* phy0 */
<269 4>, <273 4>, <274 4>, /* phy1 */
<279 4>, <283 4>, <284 4>, /* phy2 */
<289 4>, <293 4>, <294 4>, /* phy3 */
<299 4>, <303 4>, <304 4>, /* phy4 */
<309 4>, <313 4>, <314 4>, /* phy5 */
<319 4>, <323 4>, <324 4>, /* phy6 */
<329 4>, <333 4>, <334 4>, /* phy7 */
<336 1>, <337 1>, <338 1>, /* cq0-2 */
<339 1>, <340 1>, <341 1>, /* cq3-5 */
<342 1>, <343 1>, <344 1>, /* cq6-8 */
<345 1>, <346 1>, <347 1>, /* cq9-11 */
<348 1>, <349 1>, <350 1>, /* cq12-14 */
<351 1>, <352 1>, <353 1>, /* cq15-17 */
<354 1>, <355 1>, <356 1>, /* cq18-20 */
<357 1>, <358 1>, <359 1>, /* cq21-23 */
<360 1>, <361 1>, <362 1>, /* cq24-26 */
<363 1>, <364 1>, <365 1>, /* cq27-29 */
<366 1>, <367 1>, /* cq30-31 */
<376 4>, /* fatal ecc */
<381 4>; /* fatal axi */
ctrl-reset-reg = <0xa60>;
ctrl-reset-sts-reg = <0x5a30>;
ctrl-clock-ena-reg = <0x338>;
hisilicon,sas-syscon = <&pcie_sas>;
queue-count = <32>;
phy-count = <8>;
sas-addr = [50 01 88 20 16 00 00 0a];
};
Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
-98
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@@ -1,98 +0,0 @@
* HiSilicon SAS controller
The HiSilicon SAS controller supports SAS/SATA.
Main node required properties:
- compatible : value should be as follows:
(a) "hisilicon,hip05-sas-v1" for v1 hw in hip05 chipset
(b) "hisilicon,hip06-sas-v2" for v2 hw in hip06 chipset
(c) "hisilicon,hip07-sas-v2" for v2 hw in hip07 chipset
- sas-addr : array of 8 bytes for host SAS address
- reg : Contains two regions. The first is the address and length of the SAS
register. The second is the address and length of CPLD register for
SGPIO control. The second is optional, and should be set only when
we use a CPLD for directly attached disk LED control.
- hisilicon,sas-syscon: phandle of syscon used for sas control
- ctrl-reset-reg : offset to controller reset register in ctrl reg
- ctrl-reset-sts-reg : offset to controller reset status register in ctrl reg
- ctrl-clock-ena-reg : offset to controller clock enable register in ctrl reg
- queue-count : number of delivery and completion queues in the controller
- phy-count : number of phys accessible by the controller
- interrupts : For v1 hw: Interrupts for phys, completion queues, and fatal
sources; the interrupts are ordered in 3 groups, as follows:
- Phy interrupts
- Completion queue interrupts
- Fatal interrupts
Phy interrupts : Each phy has 3 interrupt sources:
- broadcast
- phyup
- abnormal
The phy interrupts are ordered into groups of 3 per phy
(broadcast, phyup, and abnormal) in increasing order.
Completion queue interrupts : each completion queue has 1
interrupt source.
The interrupts are ordered in increasing order.
Fatal interrupts : the fatal interrupts are ordered as follows:
- ECC
- AXI bus
For v2 hw: Interrupts for phys, Sata, and completion queues;
the interrupts are ordered in 3 groups, as follows:
- Phy interrupts
- Sata interrupts
- Completion queue interrupts
Phy interrupts : Each controller has 2 phy interrupts:
- phy up/down
- channel interrupt
Sata interrupts : Each phy on the controller has 1 Sata
interrupt. The interrupts are ordered in increasing
order.
Completion queue interrupts : each completion queue has 1
interrupt source. The interrupts are ordered in
increasing order.
Optional main node properties:
- hip06-sas-v2-quirk-amt : when set, indicates that the v2 controller has the
"am-max-transmissions" limitation.
- hisilicon,signal-attenuation : array of 3 32-bit values, containing de-emphasis,
preshoot, and boost attenuation readings for the board. They
are used to describe the signal attenuation of the board. These
values' range is 7600 to 12400, and used to represent -24dB to
24dB.
The formula is "y = (x-10000)/10000". For example, 10478
means 4.78dB.
Example:
sas0: sas@c1000000 {
compatible = "hisilicon,hip05-sas-v1";
sas-addr = [50 01 88 20 16 00 00 0a];
reg = <0x0 0xc1000000 0x0 0x10000>;
hisilicon,sas-syscon = <&pcie_sas>;
ctrl-reset-reg = <0xa60>;
ctrl-reset-sts-reg = <0x5a30>;
ctrl-clock-ena-reg = <0x338>;
queue-count = <32>;
phy-count = <8>;
dma-coherent;
interrupt-parent = <&mbigen_dsa>;
interrupts = <259 4>,<263 4>,<264 4>,/* phy0 */
<269 4>,<273 4>,<274 4>,/* phy1 */
<279 4>,<283 4>,<284 4>,/* phy2 */
<289 4>,<293 4>,<294 4>,/* phy3 */
<299 4>,<303 4>,<304 4>,/* phy4 */
<309 4>,<313 4>,<314 4>,/* phy5 */
<319 4>,<323 4>,<324 4>,/* phy6 */
<329 4>,<333 4>,<334 4>,/* phy7 */
<336 1>,<337 1>,<338 1>,/* cq0-2 */
<339 1>,<340 1>,<341 1>,/* cq3-5 */
<342 1>,<343 1>,<344 1>,/* cq6-8 */
<345 1>,<346 1>,<347 1>,/* cq9-11 */
<348 1>,<349 1>,<350 1>,/* cq12-14 */
<351 1>,<352 1>,<353 1>,/* cq15-17 */
<354 1>,<355 1>,<356 1>,/* cq18-20 */
<357 1>,<358 1>,<359 1>,/* cq21-23 */
<360 1>,<361 1>,<362 1>,/* cq24-26 */
<363 1>,<364 1>,<365 1>,/* cq27-29 */
<366 1>,<367 1>/* cq30-31 */
<376 4>,/* fatal ecc */
<381 4>;/* fatal axi */
};
Documentation/devicetree/bindings/soc/hisilicon/hisilicon,hip05-cpld.yaml
+35
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@@ -0,0 +1,35 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/hisilicon/hisilicon,hip05-cpld.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: HiSilicon HIP05 CPLD registers
maintainers:
- Wei Xu <xuwei5@hisilicon.com>
properties:
compatible:
const: hisilicon,hip05-cpld
reg:
maxItems: 1
required:
- compatible
- reg
additionalProperties: false
examples:
- |
local-bus {
#address-cells = <2>;
#size-cells = <1>;
cpld@100000000 {
compatible = "hisilicon,hip05-cpld";
reg = <0x1 0x0 0x100>;
};
};
Documentation/devicetree/bindings/soc/mediatek/mediatek,mt2701-g3dsys.yaml
+58
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@@ -0,0 +1,58 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/soc/mediatek/mediatek,mt2701-g3dsys.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek G3D System Controller
maintainers:
- Sean Wang <sean.wang@mediatek.com>
- Ryder Lee <ryder.lee@mediatek.com>
description: |
The MediaTek G3D system controller provides clocks and reset control
for the GPU subsystem on MediaTek SoCs.
properties:
compatible:
oneOf:
- items:
- const: mediatek,mt2701-g3dsys
- const: syscon
- items:
- const: mediatek,mt7623-g3dsys
- const: mediatek,mt2701-g3dsys
- const: syscon
reg:
maxItems: 1
"#clock-cells":
const: 1
"#reset-cells":
const: 1
required:
- compatible
- reg
- "#clock-cells"
- "#reset-cells"
additionalProperties: false
examples:
- |
soc {
#address-cells = <2>;
#size-cells = <2>;
g3dsys: syscon@13000000 {
compatible = "mediatek,mt7623-g3dsys",
"mediatek,mt2701-g3dsys",
"syscon";
reg = <0 0x13000000 0 0x200>;
#clock-cells = <1>;
#reset-cells = <1>;
};
};
Documentation/devicetree/bindings/soc/mediatek/scpsys.txt
-79
View File
@@ -1,79 +0,0 @@
MediaTek SCPSYS
===============
The System Control Processor System (SCPSYS) has several power management
related tasks in the system. The tasks include thermal measurement, dynamic
voltage frequency scaling (DVFS), interrupt filter and lowlevel sleep control.
The System Power Manager (SPM) inside the SCPSYS is for the MTCMOS power
domain control.
The driver implements the Generic PM domain bindings described in
power/power-domain.yaml. It provides the power domains defined in
- include/dt-bindings/power/mt8173-power.h
- include/dt-bindings/power/mt6797-power.h
- include/dt-bindings/power/mt6765-power.h
- include/dt-bindings/power/mt2701-power.h
- include/dt-bindings/power/mt2712-power.h
- include/dt-bindings/power/mt7622-power.h
Required properties:
- compatible: Should be one of:
- "mediatek,mt2701-scpsys"
- "mediatek,mt2712-scpsys"
- "mediatek,mt6735-scpsys"
- "mediatek,mt6765-scpsys"
- "mediatek,mt6797-scpsys"
- "mediatek,mt7622-scpsys"
- "mediatek,mt7623-scpsys", "mediatek,mt2701-scpsys": For MT7623 SoC
- "mediatek,mt7623a-scpsys": For MT7623A SoC
- "mediatek,mt7629-scpsys", "mediatek,mt7622-scpsys": For MT7629 SoC
- "mediatek,mt8173-scpsys"
- #power-domain-cells: Must be 1
- reg: Address range of the SCPSYS unit
- infracfg: must contain a phandle to the infracfg controller
- clock, clock-names: clocks according to the common clock binding.
These are clocks which hardware needs to be
enabled before enabling certain power domains.
Required clocks for MT2701 or MT7623: "mm", "mfg", "ethif"
Required clocks for MT2712: "mm", "mfg", "venc", "jpgdec", "audio", "vdec"
Required clocks for MT6765: MUX: "mm", "mfg"
CG: "mm-0", "mm-1", "mm-2", "mm-3", "isp-0",
"isp-1", "cam-0", "cam-1", "cam-2",
"cam-3","cam-4"
Required clocks for MT6797: "mm", "mfg", "vdec"
Required clocks for MT7622 or MT7629: "hif_sel"
Required clocks for MT7623A: "ethif"
Required clocks for MT8173: "mm", "mfg", "venc", "venc_lt"
Optional properties:
- vdec-supply: Power supply for the vdec power domain
- venc-supply: Power supply for the venc power domain
- isp-supply: Power supply for the isp power domain
- mm-supply: Power supply for the mm power domain
- venc_lt-supply: Power supply for the venc_lt power domain
- audio-supply: Power supply for the audio power domain
- usb-supply: Power supply for the usb power domain
- mfg_async-supply: Power supply for the mfg_async power domain
- mfg_2d-supply: Power supply for the mfg_2d power domain
- mfg-supply: Power supply for the mfg power domain
Example:
scpsys: scpsys@10006000 {
#power-domain-cells = <1>;
compatible = "mediatek,mt8173-scpsys";
reg = <0 0x10006000 0 0x1000>;
infracfg = <&infracfg>;
clocks = <&clk26m>,
<&topckgen CLK_TOP_MM_SEL>;
<&topckgen CLK_TOP_VENC_SEL>,
<&topckgen CLK_TOP_VENC_LT_SEL>;
clock-names = "mfg", "mm", "venc", "venc_lt";
};
Example consumer:
afe: mt8173-afe-pcm@11220000 {
compatible = "mediatek,mt8173-afe-pcm";
power-domains = <&scpsys MT8173_POWER_DOMAIN_AUDIO>;
};
Documentation/devicetree/bindings/soc/nuvoton/nuvoton,npcm-gcr.yaml
+11 -7
View File
@@ -17,13 +17,17 @@ description:
properties:
compatible:
items:
- enum:
- nuvoton,wpcm450-gcr
- nuvoton,npcm750-gcr
- nuvoton,npcm845-gcr
- const: syscon
- const: simple-mfd
oneOf:
- items:
- enum:
- nuvoton,npcm845-gcr
- const: syscon
- items:
- enum:
- nuvoton,wpcm450-gcr
- nuvoton,npcm750-gcr
- const: syscon
- const: simple-mfd
reg:
maxItems: 1
Documentation/devicetree/bindings/soc/qcom/qcom,aoss-qmp.yaml
+1 -1
View File
@@ -71,7 +71,7 @@ properties:
maxItems: 1
description:
Reference to the mailbox representing the outgoing doorbell in APCS for
this client, as described in mailbox/mailbox.txt
this client.
"#clock-cells":
const: 0
Documentation/devicetree/bindings/sound/mediatek,mt8173-rt5650.yaml
+73
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@@ -0,0 +1,73 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/sound/mediatek,mt8173-rt5650.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8173 with RT5650 codecs and HDMI via I2S
maintainers:
- Ariel D'Alessandro <ariel.dalessandro@collabora.com>
properties:
compatible:
const: mediatek,mt8173-rt5650
reg:
maxItems: 1
interrupts:
maxItems: 1
mediatek,audio-codec:
$ref: /schemas/types.yaml#/definitions/phandle-array
description:
The phandles of rt5650 codecs and of the HDMI encoder node.
minItems: 2
mediatek,platform:
$ref: /schemas/types.yaml#/definitions/phandle
description:
The phandle of MT8173 ASoC platform.
mediatek,mclk:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
The MCLK source.
0: external oscillator, MCLK = 12.288M
1: internal source from mt8173, MCLK = sampling rate * 256
codec-capture:
description: Subnode of rt5650 codec capture.
type: object
properties:
sound-dai:
maxItems: 1
description: phandle of the CPU DAI
additionalProperties: false
required:
- compatible
- mediatek,audio-codec
- mediatek,platform
additionalProperties: false
examples:
- |
sound {
compatible = "mediatek,mt8173-rt5650";
mediatek,audio-codec = <&rt5650 &hdmi0>;
mediatek,platform = <&afe>;
pinctrl-names = "default";
pinctrl-0 = <&aud_i2s2>;
mediatek,mclk = <1>;
codec-capture {
sound-dai = <&rt5650 1>;
};
};
...
Documentation/devicetree/bindings/sound/mt8173-rt5650.txt
-31
View File
@@ -1,31 +0,0 @@
MT8173 with RT5650 CODECS and HDMI via I2S
Required properties:
- compatible : "mediatek,mt8173-rt5650"
- mediatek,audio-codec: the phandles of rt5650 codecs
and of the hdmi encoder node
- mediatek,platform: the phandle of MT8173 ASoC platform
Optional subnodes:
- codec-capture : the subnode of rt5650 codec capture
Required codec-capture subnode properties:
- sound-dai: audio codec dai name on capture path
<&rt5650 0> : Default setting. Connect rt5650 I2S1 for capture. (dai_name = rt5645-aif1)
<&rt5650 1> : Connect rt5650 I2S2 for capture. (dai_name = rt5645-aif2)
- mediatek,mclk: the MCLK source
0 : external oscillator, MCLK = 12.288M
1 : internal source from mt8173, MCLK = sampling rate*256
Example:
sound {
compatible = "mediatek,mt8173-rt5650";
mediatek,audio-codec = <&rt5650 &hdmi0>;
mediatek,platform = <&afe>;
mediatek,mclk = <0>;
codec-capture {
sound-dai = <&rt5650 1>;
};
};
Documentation/devicetree/bindings/spi/aspeed,ast2600-fmc.yaml
+3 -3
View File
@@ -62,21 +62,21 @@ examples:
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
flash@0 {
reg = < 0 >;
reg = <0>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
};
flash@1 {
reg = < 1 >;
reg = <1>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
};
flash@2 {
reg = < 2 >;
reg = <2>;
compatible = "jedec,spi-nor";
spi-max-frequency = <50000000>;
spi-rx-bus-width = <2>;
Documentation/devicetree/bindings/thermal/thermal-idle.yaml
+1 -1
View File
@@ -137,7 +137,7 @@ examples:
cooling-maps {
map0 {
trip = <&cpu_alert1>;
cooling-device = <&cpu_b0_therm 0 15 >,
cooling-device = <&cpu_b0_therm 0 15>,
<&cpu_b1_therm 0 15>;
};
Documentation/devicetree/bindings/trivial-devices.yaml
+3 -1
View File
@@ -188,7 +188,7 @@ properties:
- injoinic,ip5306
# Inspur Power System power supply unit version 1
- inspur,ipsps1
# Intel common redudant power supply crps185
# Intel common redundant power supply crps185
- intel,crps185
# Intersil ISL29028 Ambient Light and Proximity Sensor
- isil,isl29028
@@ -414,6 +414,8 @@ properties:
- samsung,24ad0xd1
# Samsung Exynos SoC SATA PHY I2C device
- samsung,exynos-sataphy-i2c
# SDMC 1024bit EEPROM + 128bit OTP memory for key
- sdmc,dm2016
# Semtech sx1301 baseband processor
- semtech,sx1301
# Sensirion multi-pixel gas sensor with I2C interface
Documentation/devicetree/bindings/usb/st,stm32mp25-dwc3.yaml
+97
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@@ -0,0 +1,97 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/usb/st,stm32mp25-dwc3.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: STMicroelectronics STM32 MPU DWC3 USB SoC controller
description:
The STM32 MPU DWC3 USB SoC controller block supports both
Host(SS/HS/FS/LS) and Device(SS/HS/FS) mode operation
maintainers:
- Fabrice Gasnier <fabrice.gasnier@foss.st.com>
- Marek Vasut <marex@nabladev.com>
allOf:
- $ref: snps,dwc3-common.yaml#
properties:
compatible:
const: st,stm32mp25-dwc3
reg:
maxItems: 1
access-controllers:
maxItems: 1
clocks:
minItems: 3
maxItems: 3
clock-names:
items:
- const: ref
- const: bus_early
- const: suspend
interrupts:
maxItems: 1
resets:
maxItems: 1
over-current-active-low:
type: boolean
description: Over-Current signal polarity is active-low
st,syscfg:
$ref: /schemas/types.yaml#/definitions/phandle-array
description: Phandle to system configuration controller.
items:
- items:
- description: phandle to syscfg
- description: USB3DR control offset within syscfg
st,enable-port-power-control:
type: boolean
description: Enable Host-Mode Port Power Control (bit-3 of capability param HCCPARAMS)
st,vbusen-active-low:
type: boolean
description: VBUS-ENABLE signal polarity is active-low
required:
- compatible
- reg
- clocks
- clock-names
- interrupts
- phys
- phy-names
- resets
- st,syscfg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/clock/st,stm32mp25-rcc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/reset/st,stm32mp25-rcc.h>
usb@48300000 {
compatible = "st,stm32mp25-dwc3";
reg = <0x48300000 0x100000>;
clocks = <&rcc CK_KER_USB2PHY2>, <&rcc CK_BUS_USB3DR>, <&rcc CK_KER_USB2PHY2>;
clock-names = "ref", "bus_early", "suspend";
interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
phys = <&usb2_phy>, <&usb3_phy>;
phy-names = "usb2-phy", "usb3-phy";
resets = <&rcc USB3DR_R>;
over-current-active-low;
st,syscfg = <&syscfg 0x4800>;
st,vbusen-active-low;
};
Documentation/devicetree/bindings/vendor-prefixes.yaml
+2
View File
@@ -114,6 +114,8 @@ patternProperties:
description: Amarula Solutions
"^amazon,.*":
description: Amazon.com, Inc.
"^ambarella,.*":
description: Ambarella, Inc.
"^amcc,.*":
description: Applied Micro Circuits Corporation (APM, formally AMCC)
"^amd,.*":
Documentation/devicetree/of_unittest.rst
+1 -1
View File
@@ -125,7 +125,7 @@ Figure 1: Generic structure of un-flattened device tree
Before executing OF unittest, it is required to attach the test data to
machine's device tree (if present). So, when selftest_data_add() is called,
machine's device tree (if present). So, when unittest_data_add() is called,
at first it reads the flattened device tree data linked into the kernel image
via the following kernel symbols::
Documentation/devicetree/overlay-notes.rst
-4
View File
@@ -115,10 +115,6 @@ The API is quite easy to use.
previously created via the call to of_overlay_fdt_apply(). Removal of an
overlay changeset that is stacked by another will not be permitted.
Finally, if you need to remove all overlays in one-go, just call
of_overlay_remove_all() which will remove every single one in the correct
order.
There is the option to register notifiers that get called on
overlay operations. See of_overlay_notifier_register/unregister and
enum of_overlay_notify_action for details.
Documentation/translations/zh_CN/devicetree/overlay-notes.rst
-3
View File
@@ -116,9 +116,6 @@ DT中的适当位置。在这种情况下，可以提供目标路径。通过标
2) 调用of_overlay_remove()来删除和清理先前通过调用of_overlay_fdt_apply()
而创建的覆盖变更集。不允许删除一个被另一个覆盖的覆盖变化集。
最后，如果你需要一次性删除所有的覆盖，只需调用of_overlay_remove_all()，
它将以正确的顺序删除每一个覆盖。
你可以选择注册在覆盖操作中被调用的通知器。详见
of_overlay_notifier_register/unregister和enum of_overlay_notify_action。
MAINTAINERS
+3 -1
View File
@@ -12085,7 +12085,7 @@ HISILICON SAS Controller
M: Xingui Yang <yangxingui@huawei.com>
S: Supported
W: http://www.hisilicon.com
F: Documentation/devicetree/bindings/scsi/hisilicon-sas.txt
F: Documentation/devicetree/bindings/scsi/hisilicon,hip05-sas-v1.yaml
F: drivers/scsi/hisi_sas/
HISILICON SECURITY ENGINE V2 DRIVER (SEC2)
@@ -20834,6 +20834,8 @@ F: Documentation/devicetree/
F: Documentation/process/maintainer-devicetree.rst
F: arch/*/boot/dts/
F: include/dt-bindings/
F: scripts/dtc/dt-check-style
F: scripts/dtc/dt-style-selftest/
OPENCOMPUTE PTP CLOCK DRIVER
M: Vadim Fedorenko <vadim.fedorenko@linux.dev>
drivers/of/fdt_address.c
+1 -1
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@@ -172,7 +172,7 @@ static u64 __init fdt_translate_address(const void *blob, int node_offset)
goto bail;
bus = &of_busses[0];
/* Cound address cells & copy address locally */
/* Count address cells & copy address locally */
bus->count_cells(blob, parent, &na, &ns);
if (!OF_CHECK_COUNTS(na, ns)) {
pr_err("Bad cell count for %s\n",
drivers/of/irq.c
+22 -17
View File
@@ -767,34 +767,27 @@ err:
}
}
static int of_check_msi_parent(struct device_node *dev_node, struct device_node **msi_node)
static int of_check_msi_parent(struct device_node *dev_node, struct device_node **msi_node,
struct of_phandle_args *msi_spec)
{
struct of_phandle_args msi_spec;
int ret;
/*
* An msi-parent phandle with a missing or == 0 #msi-cells
* property identifies a 1:1 ID translation mapping.
*
* Set the msi controller node if the firmware matches this
* condition.
* @msi_spec keeps a reference to the target node whenever the
* phandle parses, -EINVAL included, and the caller releases it.
*/
ret = of_parse_phandle_with_optional_args(dev_node, "msi-parent", "#msi-cells",
0, &msi_spec);
0, msi_spec);
if (ret)
return ret;
if ((*msi_node && *msi_node != msi_spec.np) || msi_spec.args_count != 0)
ret = -EINVAL;
if ((*msi_node && *msi_node != msi_spec->np) || msi_spec->args_count != 0)
return -EINVAL;
if (!ret) {
/* Return with a node reference held */
*msi_node = msi_spec.np;
return 0;
}
of_node_put(msi_spec.np);
return ret;
return 0;
}
/**
@@ -808,7 +801,9 @@ static int of_check_msi_parent(struct device_node *dev_node, struct device_node
* @id_in: Device ID.
*
* Walk up the device hierarchy looking for devices with a "msi-map"
* or "msi-parent" property. If found, apply the mapping to @id_in.
* or "msi-parent" property. If found, apply the mapping to @id_in. With
* @msi_np non-NULL, a device declaring an msi-parent ends the walk, usable
* or not.
*
* Returns: The mapped MSI id.
*/
@@ -823,6 +818,7 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in)
*/
for (parent_dev = dev; parent_dev; parent_dev = parent_dev->parent) {
struct of_phandle_args msi_spec = {};
int ret;
if (!of_map_msi_id(parent_dev->of_node, id_in, msi_np, &msi_spec)) {
if (msi_spec.np) {
@@ -837,8 +833,17 @@ u32 of_msi_xlate(struct device *dev, struct device_node **msi_np, u32 id_in)
break;
}
/* -ENODEV: msi-map absent → check for msi-parent */
if (msi_np && !of_check_msi_parent(parent_dev->of_node, msi_np))
if (!msi_np)
continue;
ret = of_check_msi_parent(parent_dev->of_node, msi_np, &msi_spec);
if (msi_spec.np) {
/* A declared msi-parent names the controller, usable or not */
if (!ret && !*msi_np)
*msi_np = of_node_get(msi_spec.np);
of_node_put(msi_spec.np);
break;
}
}
return id_out;
}
drivers/of/overlay.c
-23
View File
@@ -1282,26 +1282,3 @@ out:
return ret;
}
EXPORT_SYMBOL_GPL(of_overlay_remove);
/**
* of_overlay_remove_all() - Reverts and frees all overlay changesets
*
* Removes all overlays from the system in the correct order.
*
* Return: 0 on success, or a negative error number
*/
int of_overlay_remove_all(void)
{
struct overlay_changeset *ovcs, *ovcs_n;
int ret;
/* the tail of list is guaranteed to be safe to remove */
list_for_each_entry_safe_reverse(ovcs, ovcs_n, &ovcs_list, ovcs_list) {
ret = of_overlay_remove(&ovcs->id);
if (ret)
return ret;
}
return 0;
}
EXPORT_SYMBOL_GPL(of_overlay_remove_all);
drivers/of/property.c
+20 -3
View File
@@ -74,7 +74,7 @@ bool of_graph_is_present(const struct device_node *node)
struct device_node *port __free(device_node) = of_get_child_by_name(node, "port");
return !!port;
return port;
}
EXPORT_SYMBOL(of_graph_is_present);
@@ -1471,6 +1471,22 @@ static struct device_node *parse_gpio_compat(struct device_node *np,
return sup_args.np;
}
static struct device_node *parse_i2c_parent(struct device_node *np,
const char *prop_name, int index)
{
if (strcmp(prop_name, "i2c-parent"))
return NULL;
/* tc9563 (pci1179,0623) is <phandle addr>; every other user is bare phandles */
if (of_device_is_compatible(np, "pci1179,0623")) {
if (index)
return NULL;
return of_parse_phandle(np, prop_name, 0);
}
return of_parse_phandle(np, prop_name, index);
}
static struct device_node *parse_interrupts(struct device_node *np,
const char *prop_name, int index)
{
@@ -1562,6 +1578,7 @@ static const struct supplier_bindings of_supplier_bindings[] = {
{ .parse_prop = parse_resets, },
{ .parse_prop = parse_leds, },
{ .parse_prop = parse_backlight, },
{ .parse_prop = parse_i2c_parent, },
{ .parse_prop = parse_panel, },
{ .parse_prop = parse_msi_parent, },
{ .parse_prop = parse_pses, },
@@ -1659,12 +1676,12 @@ static bool of_is_fwnode_add_links_supported(void)
return true;
if (is_supported != -1)
return !!is_supported;
return is_supported;
is_supported = !((match_property_by_path("/soc", "compatible", "intel,ce4100-cp") >= 0) ||
(match_property_by_path("/", "architecture", "OLPC") >= 0));
return !!is_supported;
return is_supported;
}
static int of_fwnode_add_links(struct fwnode_handle *fwnode)
include/dt-bindings/clock/agilex-clock.h
+1
View File
@@ -44,6 +44,7 @@
/* Gate clocks */
#define AGILEX_MPU_CLK 30
/* Legacy ABI ID; do not use in new DTs, use AGILEX_MPU_CCU_CLK */
#define AGILEX_MPU_L2RAM_CLK 31
#define AGILEX_MPU_PERIPH_CLK 32
#define AGILEX_L4_MAIN_CLK 33
include/linux/of.h
-6
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@@ -1837,7 +1837,6 @@ struct of_overlay_notify_data {
int of_overlay_fdt_apply(const void *overlay_fdt, u32 overlay_fdt_size,
int *ovcs_id, const struct device_node *target_base);
int of_overlay_remove(int *ovcs_id);
int of_overlay_remove_all(void);
int of_overlay_notifier_register(struct notifier_block *nb);
int of_overlay_notifier_unregister(struct notifier_block *nb);
@@ -1855,11 +1854,6 @@ static inline int of_overlay_remove(int *ovcs_id)
return -ENOTSUPP;
}
static inline int of_overlay_remove_all(void)
{
return -ENOTSUPP;
}
static inline int of_overlay_notifier_register(struct notifier_block *nb)
{
return 0;
scripts/dtc/dt-check-style
+560 -412
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scripts/dtc/dt-style-selftest/bad/dts-blank-lines.dts
+37
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@@ -0,0 +1,37 @@
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
/dts-v1/;
/ {
compatible = "example,test-board";
#address-cells = <1>;
#size-cells = <1>;
interrupt-controller@10000 {
compatible = "example,intc";
reg = <0x10000 0x1000>;
clocks = <1 2 3>,
/* Comment is not a blank line */
<4 5 6>,
/* Comment is not a blank line */
<7 8 9>;
interrupts = <1>;
/* Comment is not a blank line */
qcom,calibration-variant = "foo";
};
interrupt-controller@20000 {
compatible = "example,intc";
reg = <0x20000 0x1000>;
};
};
scripts/dtc/dt-style-selftest/bad/dts-child-name-order.dtso
+33
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@@ -0,0 +1,33 @@
// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
/dts-v1/;
/plugin/;
&{/} {
#address-cells = <1>;
#size-cells = <1>;
pmu {
compatible = "example,pmu";
/* Include labels to be sure they do not affect sorting */
foo: foo {
label = "foo";
};
label_bar: bar {
label = "bar";
};
};
memory@a0000000 {
device_type = "memory";
reg = <0x0 0xa0000000 0x0 0x0>;
};
pmu-2 {
compatible = "example,pmu";
/* Just reference labels to avoid strict warnings */
example,foo = <&foo>, <&label_bar>;
};
};
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