Ali Cheraghi
65b95b0af4
add unskip_spirv_tests.zig tool
2026-09-18 16:36:24 +03:30
Ali Cheraghi
d95c7db6ec
test: skip failing behavior tests for spirv
2026-08-26 08:13:06 +03:30
Guy Fischman
a72236ae8e
compiler: lower array-to-vector coercion in the backend
2026-08-15 10:38:52 +02:00
Jacob Young
3b8913a321
llvm: enable passing tests
...
Closes #10875
Closes #12396
Closes #20680
Closes #25734
Closes #30854
Closes #35519
2026-07-27 14:44:41 -04:00
Jacob Young
092f019be9
llvm: implement placeholder powerpc64le c abi logic
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This was honestly easier than disabling most of the tests.
2026-07-27 14:43:52 -04:00
Jacob Young
b425e68694
llvm: update for compiler_rt abi changes
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Closes #12602
Closes #21234
Closes #35899
Closes #36127
2026-07-27 14:38:34 -04:00
Jacob Young
865f329e4f
cbe: update for compiler_rt abi changes
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* `tools/generate_c_size_and_align_checks.zig`: superceded by any cbe
output artifact
* `cTypePreferredAlignment`: no uses, if brought back, cbe should be
updated to verify `__alignof`
Closes #19991
Closes #20881
Closes #35523
2026-07-27 14:35:12 -04:00
f810faa828
compiler: implement @divCeil builtin
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Co-authored-by: riverbl <94326797+riverbl@users.noreply.github.com >
Co-authored-by: Ratakor <ratakor@disroot.org >
2026-07-06 20:13:46 +02:00
Ali Cheraghi
827c3d528c
test: unskip 72 passing behavior tests for spirv backend
2026-07-05 14:47:00 +03:30
Andrew Kelley
f6cd4971e2
separate @splat tests into their own behavior tests
...
and remove usage of expectEqual
2026-07-02 17:26:58 -07:00
Ali Cheraghi
bae68c8a45
test: unskip passing behavior tests for spirv backend
2026-06-28 18:25:43 +02:00
Matthew Lugg
664c1d0198
cbe: disable some failing tests
2026-06-24 10:20:56 +01:00
Matthew Lugg
2fcac141e7
tests: update for new @bitCast semantics
2026-06-24 10:20:56 +01:00
Ali Cheraghi
65e74dfbda
@extern: add flat decoration
2026-06-18 13:38:58 +02:00
Ali Cheraghi
4653794852
spirv: implement switch with ranges and loop_switch_br switch_dispatch
2026-06-18 13:38:58 +02:00
Ali Cheraghi
9115f88386
test: skip failing/crashing behavior tests for spirv backend
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tested with `-target spirv64-vulkan` and `-mcpu vulkan_v1_2+float16+variable_pointers+float64+int64`
2026-06-14 09:11:59 +02:00
Kendall Condon
65819004f3
workaround surfaced backend bugs
...
self-hosted wasm workaround provided by pavelverigo in #31991
powerpc workarounds provided by alexrp in #31991
2026-05-25 18:38:01 -07:00
Alex Rønne Petersen
0d4f3cc675
re-enable some tests on RISC-V that no longer fail
...
Miscompilations appear to have been fixed with LLVM 22.
closes https://github.com/ziglang/zig/issues/24299
closes https://github.com/ziglang/zig/issues/24300
closes https://github.com/ziglang/zig/issues/24301
closes https://github.com/ziglang/zig/issues/25083
2026-05-21 20:37:11 +02:00
Alex Rønne Petersen
91bcdbec34
behavior: re-enable vector reduce operation on sparc64
...
closes https://github.com/ziglang/zig/issues/23719
2026-05-18 21:39:32 +02:00
Alex Rønne Petersen
72966e2a7b
disable some tests that fail on x86_64-macos
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These might be Rosetta 2 bugs, but I have no way to actually check since we no
longer have any native x86_64-macos CI machines.
2026-05-09 08:49:34 +02:00
Alex Rønne Petersen
1af476d5d8
behavior: re-enable a bunch of behavior tests that now pass
...
closes https://github.com/ziglang/zig/issues/9660
closes https://github.com/ziglang/zig/issues/21050
closes https://github.com/ziglang/zig/issues/21090
closes https://github.com/ziglang/zig/issues/21091
2026-04-25 21:54:48 +02:00
Pavel Verigo
22945fbbdc
stage2-wasm: vector, std tests
2026-04-22 00:19:46 +02:00
Pavel Verigo
bf58a3bc08
stage2_wasm: revival, enabling tests
2025-12-07 07:21:15 +01:00
Jacob Young
07c3f9ef8e
x86_64: fix bool vector init register clobber
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Closes #25439
2025-10-03 12:18:53 -04:00
Andrew Kelley
01132e0cf8
remove behavior test that depended on std.zig.c_translation
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behavior tests may not depend on this namespace.
2025-09-24 20:01:19 -07:00
Andrew Kelley
ed7ff0b693
allow some test cases to regress
...
tracked by #24061 - these should be re-enabled once that is solved.
2025-09-20 18:33:01 -07:00
Andrew Kelley
2ba03e98c8
disable failing stage2_aarch64 behavior tests
2025-09-20 18:33:01 -07:00
Jacob Young
2fdf0e29b3
aarch64: enable fixed behavior
2025-09-20 18:33:00 -07:00
Andrew Kelley
426af68b7d
compiler: require comptime vector indexes
2025-09-20 18:33:00 -07:00
Jacob Young
1a0a9d7d59
x86_64: fix strictness edge cases in +|
...
Closes #25145
2025-09-10 21:01:13 -04:00
Andrew Kelley
5701617b27
wasm backend: disable failing behavior tests
2025-09-07 20:11:37 -07:00
Luna Schwalbe
63ab0c0302
Reenable vector tests for armeb/thumbeb
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https://github.com/ziglang/zig/issues/22060 has been fixed by upstream.
2025-09-04 16:23:18 +02:00
Alex Rønne Petersen
2cb412ff1b
test: re-enable a bunch of vector behavior tests on hexagon
2025-08-30 06:36:41 +02:00
Jacob Young
5060ab99c9
aarch64: add new from scratch self-hosted backend
2025-07-22 19:43:47 -07:00
Alex Rønne Petersen
1f2e3b39ae
test: Disable vector division operators on RISC-V with vector support
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https://github.com/ziglang/zig/issues/24301
2025-07-01 23:03:15 +02:00
Jacob Young
1f98c98fff
x86_64: increase passing test coverage on windows
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Now that codegen has no references to linker state this is much easier.
Closes #24153
2025-06-19 18:41:12 -04:00
Ali Cheraghi
872f68c9cb
rename spirv backend name
...
`stage2_spirv64` -> `stage2_spirv`
2025-06-16 13:22:19 +03:30
Daniel Kongsgaard
5e3c0b7af7
Allow more operators on bool vectors ( #24131 )
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* Sema: allow binary operations and boolean not on vectors of bool
* langref: Clarify use of operators on vectors (`and` and `or` not allowed)
closes #24093
2025-06-12 15:16:23 -07:00
Danielkonge
f4c7290bc5
test: Enable some working vector tests
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Closes #12827 .
2025-06-11 22:29:51 +02:00
Alex Rønne Petersen
9d534790eb
std.Target: Introduce Cpu convenience functions for feature tests.
...
Before:
* std.Target.arm.featureSetHas(target.cpu.features, .has_v7)
* std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov })
* std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory })
After:
* target.cpu.has(.arm, .has_v7)
* target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov })
* target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-06-05 06:12:00 +02:00
Jacob Young
2543e2d97c
x86_64: implement integer @divFloor and @mod
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Closes #24039
2025-06-02 22:45:15 -04:00
Jacob Young
9edfccb9a7
Legalize: implement scalarization of overflow intrinsics
2025-06-01 08:24:01 +01:00
Jacob Young
ec579aa0f3
Legalize: implement scalarization of @shuffle
2025-06-01 08:24:01 +01:00
Jacob Young
b483defc5a
Legalize: implement scalarization of binary operations
2025-05-31 18:54:28 -04:00
Jacob Young
9f9e7e398f
x86_64: implement strict float @reduce(.Max)
2025-05-28 15:10:22 -04:00
Jacob Young
1f6f8b0ffe
x86_64: implement integer @reduce(.Add)
2025-05-28 15:10:22 -04:00
Jacob Young
a4eabd3979
x86_64: implement vector_store_elem
2025-05-17 20:31:25 -04:00
Jacob Young
a3b0c242b0
x86_64: rewrite @splat
2025-05-17 18:00:17 -04:00
Jacob Young
96e35b3652
x86_64: rewrite vector -|
2025-05-17 02:08:41 -04:00
Jacob Young
6d68a494c8
x86_64: rewrite vector +|
2025-05-17 02:08:41 -04:00
Ali Cheraghi