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Author SHA1 Message Date
Brian Ferri 25cafe0b34 spirv: fix vector casts, packed field pointers and debug names of comptime-known values (#37040)
I'm writing a small numeric library whose kernels run on the CPU, on CUDA and on Vulkan through the self-hosted SPIR-V backend, and I was making them generic over the float type. `f64` needs its own `exp` and `log` on the GPU, so I wrote them as polynomial series, and the `f64` Vulkan module stopped validating. This fixes the three backend bugs underneath that, and a crash I ran into after merging master.

The series take floats apart with `@bitCast` on vectors. Between vectors of the same length this reaches the Vulkan/OpenGL fallback in `bitCast`, which stores the source into a function variable of the destination type:

```zig
export fn main() callconv(.{ .spirv_kernel = .{ .x = 1, .y = 1, .z = 1 } }) void {
    var x: @Vector(2, f32) = .{ 1, 2 };
    _ = &x;
    const bits: @Vector(2, i32) = @bitCast(x);
    _ = bits;
}
```

```
$ zig build-exe -fno-llvm -target spirv64-vulkan -mcpu vulkan_v1_2 bitcast.zig -femit-bin=bitcast.spv
$ spirv-val --target-env vulkan1.2 bitcast.spv
error: line 45: OpStore Pointer <id> '36[%36]'s type does not match Object <id> '29[%29]'s type.
```

An elementwise vector bitcast is now a scalar `bitCast` per lane, the way `buildConvert` and friends already unroll vectors. Going through the scalar path also normalizes lanes of strange integers: a single `OpBitcast` on the whole vector validates for `@Vector(n, u3)` to `@Vector(n, i3)`, but leaves lanes that don't compare equal to the negative values they should hold.

The series also convert between integer and float lanes. A vector of one lane, or of more than four without `vector16`, is an array in SPIR-V, and `airFloatFromInt` and `airIntFromFloat` emitted a single `OpConvert*` with that array as its result type:

```zig
export fn main() callconv(.{ .spirv_kernel = .{ .x = 1, .y = 1, .z = 1 } }) void {
    var x: @Vector(1, i32) = .{1};
    _ = &x;
    const y: @Vector(1, f32) = @floatFromInt(x);
    _ = y;
}
```

```
$ spirv-val --target-env vulkan1.2 convert.spv
error: line 40: Expected float scalar or vector type as Result Type: ConvertSToF
  %y = OpConvertSToF %_arr_f32_u32_1 %26
```

`@floatCast` and `@intCast` already go through `buildConvert`, which unrolls the vector; these two now do as well, with `buildConvert` picking the int/float conversion opcodes.

The coefficients sit in a comptime array that the series take as a comptime slice, and that alone fails to compile, although nothing reads the slice at runtime:

```zig
const weights = [_]f32{ 1, 2, 3 };

inline fn first(comptime w: []const f32) f32 {
    return w[0];
}

export fn main() callconv(.{ .spirv_kernel = .{ .x = 1, .y = 1, .z = 1 } }) void {
    var x: f32 = first(&weights);
    _ = &x;
}
```

```
$ zig build-exe -fno-llvm -target spirv64-vulkan -mcpu vulkan_v1_2 dbgvar.zig -femit-bin=dbgvar.spv
dbgvar.zig:7:8: error: TODO (SPIR-V): pointer to constant 'dbgvar.weights'
```

It appears `airDbgVar` lowers the operand only to attach an `OpName` to it, and a pointer to a non-extern constant is still a TODO. A comptime-known value has no runtime variable of its own to name, so `airDbgVar` now leaves interned operands alone. The same thing held back 58 of the behavior tests skipped on SPIR-V, and the test commit un-skips them.

After merging master, four of those tests crashed the compiler in `structFieldPtr`, which has `unreachable` for packed containers since ebb8683ef1 ([#36996](https://codeberg.org/ziglang/zig/pulls/36996)):

```zig
const Flags = packed struct { a: bool, b: bool };

export fn main() callconv(.{ .spirv_kernel = .{ .x = 1, .y = 1, .z = 1 } }) void {
    var flags: Flags = .{ .a = true, .b = false };
    const b = &flags.b;
    b.* = true;
}
```

```
thread 3961624 panic: reached unreachable code
src/codegen/spirv/CodeGen.zig:6906:27: 0x4767157 in structFieldPtr (main.zig)
            .@"packed" => unreachable,
```

My reading is that the `unreachable` holds for the pointer derivations it was written for, since `constantPtr` now turns packed pointers into pointers to their host integer first, but `airStructFieldPtr` and `airStructFieldPtrIndex` still pass packed structs through. A pointer to a packed field is a bit-pointer into the struct's own host integer, so it is the struct pointer: that is what the old code computed, and what the C backend now does with `.begin`. Packed unions get back the TODO error they had before. I may be missing a plan for packed field pointers here, and I'm happy to change it if so. The commit also un-skips three packed tests that crash on master the same way. I suppose nothing caught this because those tests are skipped on SPIR-V and the `spirv64-vulkan` behavior target is commented out in `test/tests.zig`.

I ran the behavior tests through `tools/unskip_spirv_tests.zig` and [zig-spirv-test-executor](https://github.com/Snektron/zig-spirv-test-executor) on a Radeon 680M, and the new and un-skipped tests on an RTX 4060 as well. Every fix has tests that fail on master and pass with it; the vector ones compare lane by lane, since `expectEqual` on vectors doesn't compile for SPIR-V yet. Running each behavior file whole, nothing that passes on master fails. Five more skips already pass on master without these changes, so I left them out, but I can add them. The new vector tests copy the aarch64, arm, sparc64 and riscv64 skips of the tests around them, which I couldn't check.

Reviewed-on: https://codeberg.org/ziglang/zig/pulls/37040
Reviewed-by: Ali Cheraghi <alichraghi@noreply.codeberg.org>
2026-10-04 11:50:49 +02:00
Ali Cheraghi 65b95b0af4 add unskip_spirv_tests.zig tool 2026-09-18 16:36:24 +03:30
Ali Cheraghi d95c7db6ec test: skip failing behavior tests for spirv 2026-08-26 08:13:06 +03:30
rpkak de207594e4 InternPool: don't differentiate between positive and negative zero for ints (#36451)
Added a test, which fails on master.

Reviewed-on: https://codeberg.org/ziglang/zig/pulls/36451
Reviewed-by: mlugg <mlugg@mlugg.co.uk>
2026-08-11 10:22:28 +02:00
Jacob Young b425e68694 llvm: update for compiler_rt abi changes
Closes #12602
Closes #21234
Closes #35899
Closes #36127
2026-07-27 14:38:34 -04:00
Jacob Young 865f329e4f cbe: update for compiler_rt abi changes
* `tools/generate_c_size_and_align_checks.zig`: superceded by any cbe
   output artifact
 * `cTypePreferredAlignment`: no uses, if brought back, cbe should be
   updated to verify `__alignof`

Closes #19991
Closes #20881
Closes #35523
2026-07-27 14:35:12 -04:00
f810faa828 compiler: implement @divCeil builtin
Co-authored-by: riverbl <94326797+riverbl@users.noreply.github.com>
Co-authored-by: Ratakor <ratakor@disroot.org>
2026-07-06 20:13:46 +02:00
Ali Cheraghi 827c3d528c test: unskip 72 passing behavior tests for spirv backend 2026-07-05 14:47:00 +03:30
Ali Cheraghi bae68c8a45 test: unskip passing behavior tests for spirv backend 2026-06-28 18:25:43 +02:00
Ali Cheraghi 65e74dfbda @extern: add flat decoration 2026-06-18 13:38:58 +02:00
Ali Cheraghi 508cbec694 spirv: implement tuple types 2026-06-18 13:38:58 +02:00
Ali Cheraghi a5fbbb8305 spirv: composite integers
composite integers (wider than usize) are represented in as `[N]u32` arrays.
however, no operations were implemented before.
following operations are implemented:

- bitwise (and, or, xor, not)
- comparison (eq/neq)
- add/sub/mul/shl/shr
- `@abs`, `@intCast`

this removes 36 SPIR-V behavior test skips.

also fixed `derivePtr` to use `OpAccessChain` instead of `OpBitcast`
for array pointer casts (e.g. `*[100]u8` to `*u8`) in logical addressing
mode, where pointer bitcasts are not valid.
2026-06-18 13:38:58 +02:00
Ali Cheraghi 9115f88386 test: skip failing/crashing behavior tests for spirv backend
tested with `-target spirv64-vulkan` and `-mcpu vulkan_v1_2+float16+variable_pointers+float64+int64`
2026-06-14 09:11:59 +02:00
Linus Groh 991f56fd6b std.meta: Remove Int in favor of @Int 2026-05-03 21:42:06 +01:00
Matthew Lugg 213c4fc25f lib,test: remove uses of i0
In preparation for its removal, as accepted in
https://github.com/ziglang/zig/issues/1593.
2026-04-30 08:57:51 +01:00
Alex Rønne Petersen 1af476d5d8 behavior: re-enable a bunch of behavior tests that now pass
closes https://github.com/ziglang/zig/issues/9660
closes https://github.com/ziglang/zig/issues/21050
closes https://github.com/ziglang/zig/issues/21090
closes https://github.com/ziglang/zig/issues/21091
2026-04-25 21:54:48 +02:00
Alex Rønne Petersen a0ad35d0ba Revert "test: disable some vector ctz/clz behavior tests on LoongArch with LSX"
This reverts commit beb25b0430.

The bug was fixed in LLVM 22.
2026-04-25 21:54:48 +02:00
Pavel Verigo 22945fbbdc stage2-wasm: vector, std tests 2026-04-22 00:19:46 +02:00
Andrew Kelley e00b5daa1f Merge pull request 'stage2-wasm: finish bigint support' (#31784) from pavelverigo/zig:wasm-bigint-finish into master
Reviewed-on: https://codeberg.org/ziglang/zig/pulls/31784
Reviewed-by: Andrew Kelley <andrew@ziglang.org>
2026-04-15 23:07:40 +02:00
Mathieu Suen 244f5aafca fixup! Adding unwrapped error multiply regression test 2026-04-10 23:23:33 +02:00
Mathieu Suen 7addae8f7d Adding unwrapped error multiply regression test 2026-04-10 23:23:33 +02:00
Pavel Verigo 5b5f828019 test: skip .stage2_c for > 128 bits tests + remove skip for x86_64 2026-04-09 00:14:09 +02:00
Pavel Verigo 07e3e50fd2 stage2-wasm: enabling bigint blocked tests + final fixes 2026-04-09 00:14:09 +02:00
Pavel Verigo aa7874657b stage2-wasm: bigint div mod rem 2026-04-09 00:14:09 +02:00
Pavel Verigo df79ea941b stage2-wasm: bigint abs + test min/max 2026-04-09 00:14:09 +02:00
Pavel Verigo 0ebd270d90 stage2-wasm: bigint mulo 2026-04-09 00:14:08 +02:00
Pavel Verigo 58944586be stage2-wasm: bigint support bitops and intcast 2026-04-09 00:14:08 +02:00
Pavel Verigo 557caecaaa stage2-wasm: start big int support 2026-04-02 15:48:43 +02:00
Andrew Kelley 5571c08e66 add behavior test for i96 operations 2026-01-29 19:57:36 +01:00
Jacob Young e1f3fc6ce2 Coff2: create a new linker from scratch 2025-10-02 17:44:52 -04:00
Andrew Kelley 5ec0a7d8a5 coerce vectors to arrays rather than inline for 2025-09-20 18:33:00 -07:00
Andrew Kelley 426af68b7d compiler: require comptime vector indexes 2025-09-20 18:33:00 -07:00
Alex Rønne Petersen beb25b0430 test: disable some vector ctz/clz behavior tests on LoongArch with LSX
https://github.com/llvm/llvm-project/issues/159529
2025-09-18 12:42:24 +02:00
Matthew Lugg 032bbd68a7 Merge pull request #24537 from IOKG04/some-documentation-updates-0
some small langref changes
2025-07-31 02:32:32 +01:00
Jacob Young 3fbdd58a87 aarch64: implement scalar @mod 2025-07-28 22:23:19 -07:00
Rue 5381e7891d Merge branch 'ziglang:master' into some-documentation-updates-0 2025-07-28 14:54:52 +02:00
Jacob Young 5060ab99c9 aarch64: add new from scratch self-hosted backend 2025-07-22 19:43:47 -07:00
IOKG04 84ae54fbe6 @rem() and @mod() take denominator != 0, not just denominator > 0
https://github.com/ziglang/zig/issues/23635

I also added tests for `@rem()` with `denominator < 0` cause there were none before
I hope I added them in the correct place, if not I can change it ofc
2025-07-22 13:35:55 +02:00
Bingwu Zhang e8d6ecb9ce riscv64: skip failing tests 2025-06-28 06:47:09 +08:00
Jacob Young 1f98c98fff x86_64: increase passing test coverage on windows
Now that codegen has no references to linker state this is much easier.

Closes #24153
2025-06-19 18:41:12 -04:00
Ali Cheraghi 872f68c9cb rename spirv backend name
`stage2_spirv64` -> `stage2_spirv`
2025-06-16 13:22:19 +03:30
Jacob Young 5986bdf868 Compilation: enable the x86_64 backend by default for debug builds
Closes #22257
2025-06-06 23:42:14 -07:00
Alex Rønne Petersen 9d534790eb std.Target: Introduce Cpu convenience functions for feature tests.
Before:

* std.Target.arm.featureSetHas(target.cpu.features, .has_v7)
* std.Target.x86.featureSetHasAny(target.cpu.features, .{ .sse, .avx, .cmov })
* std.Target.wasm.featureSetHasAll(target.cpu.features, .{ .atomics, .bulk_memory })

After:

* target.cpu.has(.arm, .has_v7)
* target.cpu.hasAny(.x86, &.{ .sse, .avx, .cmov })
* target.cpu.hasAll(.wasm, &.{ .atomics, .bulk_memory })
2025-06-05 06:12:00 +02:00
Jacob Young 2543e2d97c x86_64: implement integer @divFloor and @mod
Closes #24039
2025-06-02 22:45:15 -04:00
Jacob Young 9edfccb9a7 Legalize: implement scalarization of overflow intrinsics 2025-06-01 08:24:01 +01:00
Jacob Young b483defc5a Legalize: implement scalarization of binary operations 2025-05-31 18:54:28 -04:00
Jacob Young c1e9ef9eaa Legalize: implement scalarization of unary operations 2025-05-31 18:54:28 -04:00
Andrew Kelley 65bd8d52c8 Merge pull request #23061 from pavelverigo/stage2-wasm-misc
stage2-wasm: multiple fixes
2025-04-11 15:56:35 -04:00
Jacob Young c82e1fe880 Merge pull request #23355 from jacobly0/x86_64-rewrite
x86_64: start rewriting overflow operations
2025-04-11 05:21:44 -04:00
Alex Rønne Petersen 382aa48f04 test: Disable a bunch of vector behavior tests for hexagon.
Most of the failures are:

* https://github.com/llvm/llvm-project/issues/118879
* https://github.com/llvm/llvm-project/issues/134659

But some are also miscompilations leading to wrong results. I'm not going to
investigate the latter further until all the backend crashes have been resolved.
2025-04-11 02:28:35 +02:00