diff --git a/lib/compiler/aro/aro/Compilation.zig b/lib/compiler/aro/aro/Compilation.zig index 216b7ecb4d..afd92186df 100644 --- a/lib/compiler/aro/aro/Compilation.zig +++ b/lib/compiler/aro/aro/Compilation.zig @@ -1017,7 +1017,7 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { try w.print("#define __ARM_FEATURE_LDREX 0x{x}\n", .{@as(u4, @bitCast(ldrex))}); } - if (!target.cpu.has(.arm, .strict_align)) { + if (!target.cpu.has(.arm, .no_unaligned_access)) { try define(w, "__ARM_FEATURE_UNALIGNED"); } @@ -1147,7 +1147,7 @@ fn generateSystemDefines(comp: *Compilation, w: *Io.Writer) !void { try define(w, "__ARM_FEATURE_SM3"); try define(w, "__ARM_FEATURE_SM4"); } - if (!target.cpu.has(.aarch64, .strict_align)) { + if (!target.cpu.has(.aarch64, .no_unaligned_access)) { try define(w, "__ARM_FEATURE_UNALIGNED"); } if (target.cpu.hasAll(.aarch64, &.{ .neon, .fullfp16 })) { diff --git a/lib/std/Target/aarch64.zig b/lib/std/Target/aarch64.zig index 6cf169bd76..36b79cac23 100644 --- a/lib/std/Target/aarch64.zig +++ b/lib/std/Target/aarch64.zig @@ -135,6 +135,7 @@ pub const Feature = enum { no_lfi_stores, no_neg_immediates, no_sve_fp_ld1r, + no_unaligned_access, no_zcz_fpr64, nv, occmo, @@ -219,7 +220,6 @@ pub const Feature = enum { ssve_fp8fma, store_pair_suppress, stp_aligned_only, - strict_align, sve, sve2, sve2_aes, @@ -1041,6 +1041,11 @@ pub const all_features = blk: { .description = "Avoid using LD1RX instructions for FP", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.no_unaligned_access)] = .{ + .llvm_name = "strict-align", + .description = "Disallow all unaligned memory access", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.no_zcz_fpr64)] = .{ .llvm_name = "no-zcz-fpr64", .description = "Has no zero-cycle zeroing instructions for FPR64 registers", @@ -1541,11 +1546,6 @@ pub const all_features = blk: { .description = "In order to emit stp, first check if the store will be aligned to 2 * element_size", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.strict_align)] = .{ - .llvm_name = "strict-align", - .description = "Disallow all unaligned memory access", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.sve)] = .{ .llvm_name = "sve", .description = "Enable Scalable Vector Extension (SVE) instructions", @@ -4462,11 +4462,11 @@ pub const cpu = struct { .arith_bcc_fusion, .balance_fp_ops, .max_interleave_factor_4, + .no_unaligned_access, .perfmon, .predictable_select_expensive, .sha2, .store_pair_suppress, - .strict_align, .use_postra_scheduler, .v8_3a, }), diff --git a/lib/std/Target/arm.zig b/lib/std/Target/arm.zig index 9d7810b7db..7872dec8bf 100644 --- a/lib/std/Target/arm.zig +++ b/lib/std/Target/arm.zig @@ -115,6 +115,7 @@ pub const Feature = enum { no_bti_at_return_twice, no_movt, no_neg_immediates, + no_unaligned_access, noarm, nonpipelined_vfp, pacbti, @@ -140,7 +141,6 @@ pub const Feature = enum { slowfpvmlx, soft_float, splat_vfp_neon, - strict_align, thumb2, thumb_mode, trustzone, @@ -904,6 +904,11 @@ pub const all_features = blk: { .description = "Convert immediates and instructions to their negated or complemented equivalent when the immediate does not fit in the encoding.", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.no_unaligned_access)] = .{ + .llvm_name = "strict-align", + .description = "Disallow all unaligned memory access", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.noarm)] = .{ .llvm_name = "noarm", .description = "Does not support ARM mode execution", @@ -1033,11 +1038,6 @@ pub const all_features = blk: { .dont_widen_vmovs, }), }; - result[@backingInt(Feature.strict_align)] = .{ - .llvm_name = "strict-align", - .description = "Disallow all unaligned memory access", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.thumb2)] = .{ .llvm_name = "thumb2", .description = "Enable Thumb2 instructions", @@ -1067,35 +1067,35 @@ pub const all_features = blk: { .llvm_name = null, .description = "ARMv2 architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v2a)] = .{ .llvm_name = null, .description = "ARMv2a architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v3)] = .{ .llvm_name = null, .description = "ARMv3 architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v3m)] = .{ .llvm_name = null, .description = "ARMv3m architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v4)] = .{ .llvm_name = "armv4", .description = "ARMv4 architecture", .dependencies = featureSet(&[_]Feature{ - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v4t)] = .{ @@ -1103,7 +1103,7 @@ pub const all_features = blk: { .description = "ARMv4t architecture", .dependencies = featureSet(&[_]Feature{ .has_v4t, - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v5t)] = .{ @@ -1111,7 +1111,7 @@ pub const all_features = blk: { .description = "ARMv5t architecture", .dependencies = featureSet(&[_]Feature{ .has_v5t, - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v5te)] = .{ @@ -1119,7 +1119,7 @@ pub const all_features = blk: { .description = "ARMv5te architecture", .dependencies = featureSet(&[_]Feature{ .has_v5te, - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v5tej)] = .{ @@ -1127,7 +1127,7 @@ pub const all_features = blk: { .description = "ARMv5tej architecture", .dependencies = featureSet(&[_]Feature{ .has_v5te, - .strict_align, + .no_unaligned_access, }), }; result[@backingInt(Feature.v6)] = .{ @@ -1167,8 +1167,8 @@ pub const all_features = blk: { .db, .has_v6m, .mclass, + .no_unaligned_access, .noarm, - .strict_align, .thumb_mode, }), }; @@ -1179,8 +1179,8 @@ pub const all_features = blk: { .db, .has_v6m, .mclass, + .no_unaligned_access, .noarm, - .strict_align, .thumb_mode, }), }; @@ -1441,8 +1441,8 @@ pub const all_features = blk: { .has_v8m, .hwdiv, .mclass, + .no_unaligned_access, .noarm, - .strict_align, .thumb_mode, }), }; diff --git a/lib/std/Target/bpf.zig b/lib/std/Target/bpf.zig index cc18a9a287..a8bb9abfb3 100644 --- a/lib/std/Target/bpf.zig +++ b/lib/std/Target/bpf.zig @@ -5,8 +5,8 @@ const CpuFeature = std.Target.Cpu.Feature; const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { - allows_misaligned_mem_access, alu32, + unaligned_access, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -18,16 +18,16 @@ pub const all_features = blk: { const len = @typeInfo(Feature).@"enum".field_names.len; std.debug.assert(len <= CpuFeature.Set.needed_bit_count); var result: [len]CpuFeature = undefined; - result[@backingInt(Feature.allows_misaligned_mem_access)] = .{ - .llvm_name = "allows-misaligned-mem-access", - .description = "Allows misaligned memory access", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.alu32)] = .{ .llvm_name = "alu32", .description = "Enable ALU32 instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.unaligned_access)] = .{ + .llvm_name = "allows-misaligned-mem-access", + .description = "Allows misaligned memory access", + .dependencies = featureSet(&[_]Feature{}), + }; const ti = @typeInfo(Feature); for (&result, 0..) |*elem, i| { elem.index = i; diff --git a/lib/std/Target/loongarch.zig b/lib/std/Target/loongarch.zig index 135e4b9ec7..a71d94b64d 100644 --- a/lib/std/Target/loongarch.zig +++ b/lib/std/Target/loongarch.zig @@ -20,7 +20,7 @@ pub const Feature = enum { lsx, lvz, scq, - ual, + unaligned_access, }; pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; @@ -115,7 +115,7 @@ pub const all_features = blk: { .description = "Support sc.q instruction", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.ual)] = .{ + result[@backingInt(Feature.unaligned_access)] = .{ .llvm_name = "ual", .description = "Allow memory accesses to be unaligned", .dependencies = featureSet(&[_]Feature{}), @@ -156,7 +156,7 @@ pub const cpu = struct { .llvm_name = null, .features = featureSet(&[_]Feature{ .@"32bit", - .ual, + .unaligned_access, }), }; pub const la32v1_0: CpuModel = .{ @@ -166,7 +166,7 @@ pub const cpu = struct { .@"32bit", .@"32s", .d, - .ual, + .unaligned_access, }), }; pub const la464: CpuModel = .{ @@ -177,7 +177,7 @@ pub const cpu = struct { .lasx, .lbt, .lvz, - .ual, + .unaligned_access, }), }; pub const la64v1_0: CpuModel = .{ @@ -186,7 +186,7 @@ pub const cpu = struct { .features = featureSet(&[_]Feature{ .@"64bit", .lsx, - .ual, + .unaligned_access, }), }; pub const la64v1_1: CpuModel = .{ @@ -201,7 +201,7 @@ pub const cpu = struct { .ld_seq_sa, .lsx, .scq, - .ual, + .unaligned_access, }), }; pub const la664: CpuModel = .{ @@ -218,7 +218,7 @@ pub const cpu = struct { .ld_seq_sa, .lvz, .scq, - .ual, + .unaligned_access, }), }; }; diff --git a/lib/std/Target/mips.zig b/lib/std/Target/mips.zig index 7c25a4a2db..110cf717ea 100644 --- a/lib/std/Target/mips.zig +++ b/lib/std/Target/mips.zig @@ -47,6 +47,7 @@ pub const Feature = enum { msa, mt, nan2008, + no_unaligned_access, noabicalls, nomadd4, nooddspreg, @@ -55,7 +56,6 @@ pub const Feature = enum { r5900, single_float, soft_float, - strict_align, sym32, use_compact_branches, use_indirect_jump_hazard, @@ -346,6 +346,11 @@ pub const all_features = blk: { .description = "IEEE 754-2008 NaN encoding", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.no_unaligned_access)] = .{ + .llvm_name = "strict-align", + .description = "Disable unaligned load store for r6", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.noabicalls)] = .{ .llvm_name = "noabicalls", .description = "Disable SVR4-style position-independent code", @@ -392,11 +397,6 @@ pub const all_features = blk: { .description = "Does not support floating point instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.strict_align)] = .{ - .llvm_name = "strict-align", - .description = "Disable unaligned load store for r6", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.sym32)] = .{ .llvm_name = "sym32", .description = "Symbols are 32 bit on Mips64", diff --git a/lib/std/Target/powerpc.zig b/lib/std/Target/powerpc.zig index c21cffa239..d1963731b0 100644 --- a/lib/std/Target/powerpc.zig +++ b/lib/std/Target/powerpc.zig @@ -6,7 +6,6 @@ const CpuModel = std.Target.Cpu.Model; pub const Feature = enum { @"64bit_support", - allow_unaligned_fp_access, altivec, booke, bpermd, @@ -68,6 +67,7 @@ pub const Feature = enum { spe, stfiwx, two_const_nr, + unaligned_fp_access, vectors_use_two_units, vsx, }; @@ -86,11 +86,6 @@ pub const all_features = blk: { .description = "Supports 64-bit instructions", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.allow_unaligned_fp_access)] = .{ - .llvm_name = "allow-unaligned-fp-access", - .description = "CPU does not trap on unaligned FP access", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.altivec)] = .{ .llvm_name = "altivec", .description = "Enable Altivec instructions", @@ -483,6 +478,11 @@ pub const all_features = blk: { .description = "Requires two constant Newton-Raphson computation", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.unaligned_fp_access)] = .{ + .llvm_name = "allow-unaligned-fp-access", + .description = "CPU does not trap on unaligned FP access", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.vectors_use_two_units)] = .{ .llvm_name = "vectors-use-two-units", .description = "Vectors use two units", @@ -772,7 +772,6 @@ pub const cpu = struct { .llvm_name = "ppc64le", .features = featureSet(&[_]Feature{ .@"64bit_support", - .allow_unaligned_fp_access, .bpermd, .cmpb, .crypto, @@ -804,6 +803,7 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, }), }; pub const pwr10: CpuModel = .{ @@ -811,7 +811,6 @@ pub const cpu = struct { .llvm_name = "pwr10", .features = featureSet(&[_]Feature{ .@"64bit_support", - .allow_unaligned_fp_access, .bpermd, .cmpb, .crypto, @@ -848,6 +847,7 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, }), }; pub const pwr11: CpuModel = .{ @@ -855,7 +855,6 @@ pub const cpu = struct { .llvm_name = "pwr11", .features = featureSet(&[_]Feature{ .@"64bit_support", - .allow_unaligned_fp_access, .bpermd, .cmpb, .crypto, @@ -892,6 +891,7 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, }), }; pub const pwr3: CpuModel = .{ @@ -995,7 +995,6 @@ pub const cpu = struct { .llvm_name = "pwr7", .features = featureSet(&[_]Feature{ .@"64bit_support", - .allow_unaligned_fp_access, .bpermd, .cmpb, .extdiv, @@ -1016,6 +1015,7 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, .vsx, }), }; @@ -1024,7 +1024,6 @@ pub const cpu = struct { .llvm_name = "pwr8", .features = featureSet(&[_]Feature{ .@"64bit_support", - .allow_unaligned_fp_access, .bpermd, .cmpb, .crypto, @@ -1056,6 +1055,7 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, }), }; pub const pwr9: CpuModel = .{ @@ -1063,7 +1063,6 @@ pub const cpu = struct { .llvm_name = "pwr9", .features = featureSet(&[_]Feature{ .@"64bit_support", - .allow_unaligned_fp_access, .bpermd, .cmpb, .crypto, @@ -1092,6 +1091,7 @@ pub const cpu = struct { .recipprec, .stfiwx, .two_const_nr, + .unaligned_fp_access, .vectors_use_two_units, }), }; diff --git a/lib/std/Target/riscv.zig b/lib/std/Target/riscv.zig index 6ed7fad681..04da4421c7 100644 --- a/lib/std/Target/riscv.zig +++ b/lib/std/Target/riscv.zig @@ -116,8 +116,8 @@ pub const Feature = enum { svpbmt, svrsw60t59b, svvptc, - unaligned_scalar_mem, - unaligned_vector_mem, + unaligned_access, + unaligned_vector_access, v, vl_dependent_latency, vxrm_pipeline_flush, @@ -1151,12 +1151,12 @@ pub const all_features = blk: { .description = "'Svvptc' (Obviating Memory-Management Instructions after Marking PTEs Valid)", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.unaligned_scalar_mem)] = .{ + result[@backingInt(Feature.unaligned_access)] = .{ .llvm_name = "unaligned-scalar-mem", .description = "Has reasonably performant unaligned scalar loads and stores", .dependencies = featureSet(&[_]Feature{}), }; - result[@backingInt(Feature.unaligned_vector_mem)] = .{ + result[@backingInt(Feature.unaligned_vector_access)] = .{ .llvm_name = "unaligned-vector-mem", .description = "Has reasonably performant unaligned vector loads and stores", .dependencies = featureSet(&[_]Feature{}), @@ -2696,8 +2696,8 @@ pub const cpu = struct { .fusion_lui_addi, .i, .m, - .unaligned_scalar_mem, - .unaligned_vector_mem, + .unaligned_access, + .unaligned_vector_access, .za64rs, .zfhmin, .zic64b, @@ -2729,8 +2729,8 @@ pub const cpu = struct { .i, .m, .no_sink_splat_operands, - .unaligned_scalar_mem, - .unaligned_vector_mem, + .unaligned_access, + .unaligned_vector_access, .v, .vxrm_pipeline_flush, .xsifivecdiscarddlone, @@ -2789,8 +2789,8 @@ pub const cpu = struct { .i, .m, .no_sink_splat_operands, - .unaligned_scalar_mem, - .unaligned_vector_mem, + .unaligned_access, + .unaligned_vector_access, .v, .vxrm_pipeline_flush, .za64rs, @@ -2830,8 +2830,8 @@ pub const cpu = struct { .m, .no_sink_splat_operands, .supm, - .unaligned_scalar_mem, - .unaligned_vector_mem, + .unaligned_access, + .unaligned_vector_access, .v, .vxrm_pipeline_flush, .za64rs, @@ -3138,7 +3138,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, + .unaligned_access, .v, .vxrm_pipeline_flush, .xsmtvdotii, @@ -3213,7 +3213,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, + .unaligned_access, .v, .vxrm_pipeline_flush, .xsmtvdot, @@ -3275,7 +3275,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, + .unaligned_access, .v, .vxrm_pipeline_flush, .xsmtvdot, @@ -3459,8 +3459,8 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, - .unaligned_vector_mem, + .unaligned_access, + .unaligned_vector_access, .v, .za64rs, .zawrs, @@ -3645,7 +3645,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, + .unaligned_access, .vxrm_pipeline_flush, .xtheadba, .xtheadbb, @@ -3706,7 +3706,7 @@ pub const cpu = struct { .svinval, .svnapot, .svpbmt, - .unaligned_scalar_mem, + .unaligned_access, .vxrm_pipeline_flush, .xtheadba, .xtheadbb, diff --git a/lib/std/Target/x86.zig b/lib/std/Target/x86.zig index c890b832e7..210ac19012 100644 --- a/lib/std/Target/x86.zig +++ b/lib/std/Target/x86.zig @@ -215,13 +215,13 @@ pub const Feature = enum { sse4_1, sse4_2, sse4a, - sse_unaligned_mem, ssse3, tagged_globals, tbm, tsxldtrk, tuning_fast_imm_vector_shift, uintr, + unaligned_sse_access, use_glm_div_sqrt_costs, use_slm_arith_costs, usermsr, @@ -1424,11 +1424,6 @@ pub const all_features = blk: { .sse3, }), }; - result[@backingInt(Feature.sse_unaligned_mem)] = .{ - .llvm_name = "sse-unaligned-mem", - .description = "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)", - .dependencies = featureSet(&[_]Feature{}), - }; result[@backingInt(Feature.ssse3)] = .{ .llvm_name = "ssse3", .description = "Enable SSSE3 instructions", @@ -1461,6 +1456,11 @@ pub const all_features = blk: { .description = "Has UINTR Instructions", .dependencies = featureSet(&[_]Feature{}), }; + result[@backingInt(Feature.unaligned_sse_access)] = .{ + .llvm_name = "sse-unaligned-mem", + .description = "Allow unaligned memory operands with SSE instructions (this may require setting a configuration bit in the processor)", + .dependencies = featureSet(&[_]Feature{}), + }; result[@backingInt(Feature.use_glm_div_sqrt_costs)] = .{ .llvm_name = "use-glm-div-sqrt-costs", .description = "Use Goldmont specific floating point div/sqrt costs", diff --git a/lib/std/zig/system/linux.zig b/lib/std/zig/system/linux.zig index f1308e5f48..ae5caa4543 100644 --- a/lib/std/zig/system/linux.zig +++ b/lib/std/zig/system/linux.zig @@ -724,10 +724,10 @@ const riscv = struct { // setFeature(&cpu, .experimental_zicfilp, ima_support and set(value, RISCV_HWPROBE.IMA_EXT_0.EXT_ZICFILP)); }, RISCV_HWPROBE.KEY.MISALIGNED_SCALAR_PERF => { - setFeature(&cpu, .unaligned_scalar_mem, value == RISCV_HWPROBE.MISALIGNED_SCALAR.FAST); + setFeature(&cpu, .unaligned_access, value == RISCV_HWPROBE.MISALIGNED_SCALAR.FAST); }, RISCV_HWPROBE.KEY.MISALIGNED_VECTOR_PERF => { - setFeature(&cpu, .unaligned_vector_mem, value == RISCV_HWPROBE.MISALIGNED_VECTOR.FAST); + setFeature(&cpu, .unaligned_vector_access, value == RISCV_HWPROBE.MISALIGNED_VECTOR.FAST); }, RISCV_HWPROBE.KEY.VENDOR_EXT_MIPS_0 => { setFeature(&cpu, .xmipsexectl, ima_support and set(value, RISCV_HWPROBE.MIPS_VENDOR_EXT_XMIPSEXECTL)); diff --git a/lib/std/zig/system/loongarch.zig b/lib/std/zig/system/loongarch.zig index 04a628e4e6..ccbf10b232 100644 --- a/lib/std/zig/system/loongarch.zig +++ b/lib/std/zig/system/loongarch.zig @@ -49,7 +49,7 @@ pub fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu { else std.os.linux.getauxval(std.elf.AT.HWCAP); - setFeature(&cpu, .ual, (hwcap_bits & HWCAP.UAL) != 0); + setFeature(&cpu, .unaligned_access, (hwcap_bits & HWCAP.UAL) != 0); const has_fpu = (hwcap_bits & HWCAP.FPU) != 0; setFeature(&cpu, .f, has_fpu and bit(cfg2, 1)); @@ -62,7 +62,7 @@ pub fn detectNativeCpuAndFeatures(arch: std.Target.Cpu.Arch) ?std.Target.Cpu { setFeature(&cpu, .lam_bh, (hwcap_bits & HWCAP.LAM_BH) != 0); } else { - setFeature(&cpu, .ual, false); + setFeature(&cpu, .unaligned_access, false); setFeature(&cpu, .f, false); setFeature(&cpu, .d, false); diff --git a/src/codegen/loongarch/Select.zig b/src/codegen/loongarch/Select.zig index a764c0776a..0f283145ac 100644 --- a/src/codegen/loongarch/Select.zig +++ b/src/codegen/loongarch/Select.zig @@ -3998,7 +3998,7 @@ pub fn body(isel: *Select, air_body: []const Air.Inst.Index) codegen.Error!void defer dst_vi.value.deref(isel); // TODO unaligned loads - assert(isel.target.cpu.has(.loongarch, .ual)); + assert(isel.target.cpu.has(.loongarch, .unaligned_access)); const ptr_vi = try isel.use(ty_op.operand); const ptr_mat = try ptr_vi.matIntRegZeroExt(isel); _ = try dst_vi.value.defLoad(isel, ptr_mat.reg(), 0, .{ diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig index fc51096c23..ade1fd90ae 100644 --- a/tools/update_cpu_features.zig +++ b/tools/update_cpu_features.zig @@ -441,6 +441,11 @@ const targets = [_]ArchTarget{ .llvm_name = "ampere1b", .flatten = true, }, + + .{ + .llvm_name = "strict-align", + .zig_name = "no_unaligned_access", + }, }, .model_overrides = &.{ .{ @@ -770,47 +775,47 @@ const targets = [_]ArchTarget{ .{ .llvm_name = "armv2", .zig_name = "v2", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv2a", .zig_name = "v2a", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv3", .zig_name = "v3", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv3m", .zig_name = "v3m", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv4", .zig_name = "v4", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv4t", .zig_name = "v4t", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv5t", .zig_name = "v5t", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv5te", .zig_name = "v5te", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv5tej", .zig_name = "v5tej", - .extra_deps = &.{"strict_align"}, + .extra_deps = &.{"no_unaligned_access"}, }, .{ .llvm_name = "armv6", @@ -972,6 +977,10 @@ const targets = [_]ArchTarget{ .llvm_name = "armv9-a", .zig_name = "v9a", }, + .{ + .llvm_name = "strict-align", + .zig_name = "no_unaligned_access", + }, .{ .llvm_name = "v4t", .zig_name = "has_v4t", @@ -1098,22 +1107,22 @@ const targets = [_]ArchTarget{ .{ .zig_name = "v2", .desc = "ARMv2 architecture", - .deps = &.{"strict_align"}, + .deps = &.{"no_unaligned_access"}, }, .{ .zig_name = "v2a", .desc = "ARMv2a architecture", - .deps = &.{"strict_align"}, + .deps = &.{"no_unaligned_access"}, }, .{ .zig_name = "v3", .desc = "ARMv3 architecture", - .deps = &.{"strict_align"}, + .deps = &.{"no_unaligned_access"}, }, .{ .zig_name = "v3m", .desc = "ARMv3m architecture", - .deps = &.{"strict_align"}, + .deps = &.{"no_unaligned_access"}, }, }, .model_overrides = &.{ @@ -1337,6 +1346,11 @@ const targets = [_]ArchTarget{ .llvm_name = "dwarfris", .omit = true, }, + + .{ + .llvm_name = "allows-misaligned-mem-access", + .zig_name = "unaligned_access", + }, }, .model_overrides = &.{ .{ @@ -1905,6 +1919,11 @@ const targets = [_]ArchTarget{ .llvm_name = "relax", .omit = true, }, + + .{ + .llvm_name = "ual", + .zig_name = "unaligned_access", + }, }, .model_overrides = &.{ .{ @@ -1939,7 +1958,7 @@ const targets = [_]ArchTarget{ "32bit", "32s", "d", - "ual", + "unaligned_access", }, }, .{ @@ -1947,7 +1966,7 @@ const targets = [_]ArchTarget{ .zig_name = "la32rv1_0", .features = &.{ "32bit", - "ual", + "unaligned_access", }, }, .{ @@ -1956,7 +1975,7 @@ const targets = [_]ArchTarget{ .features = &.{ "64bit", "lsx", - "ual", + "unaligned_access", }, }, .{ @@ -1971,7 +1990,7 @@ const targets = [_]ArchTarget{ "ld_seq_sa", "lsx", "scq", - "ual", + "unaligned_access", }, }, .{ @@ -2111,6 +2130,12 @@ const targets = [_]ArchTarget{ .name = "Mips", .td_name = "Mips", }, + .feature_overrides = &.{ + .{ + .llvm_name = "strict-align", + .zig_name = "no_unaligned_access", + }, + }, .extra_models = &.{ .{ .llvm_name = null, @@ -2240,6 +2265,10 @@ const targets = [_]ArchTarget{ .llvm_name = "fast-MFLR", .zig_name = "fast_mflr", }, + .{ + .llvm_name = "allow-unaligned-fp-access", + .zig_name = "unaligned_fp_access", + }, }, .model_overrides = &.{ .{ @@ -2678,6 +2707,15 @@ const targets = [_]ArchTarget{ .llvm_name = "experimental-zvzip", .omit = true, }, + + .{ + .llvm_name = "unaligned-scalar-mem", + .zig_name = "unaligned_access", + }, + .{ + .llvm_name = "unaligned-vector-mem", + .zig_name = "unaligned_vector_access", + }, }, .model_overrides = &.{ .{ @@ -3209,6 +3247,10 @@ const targets = [_]ArchTarget{ .llvm_name = "sse4.2", .extra_deps = &.{"crc32"}, }, + .{ + .llvm_name = "sse-unaligned-mem", + .zig_name = "unaligned_sse_access", + }, }, .extra_features = &.{ // Features removed from LLVM