From c7716c12128429739239315bed44e8ba166db970 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20R=C3=B8nne=20Petersen?= Date: Sun, 25 Oct 2026 13:34:10 +0100 Subject: [PATCH] update_cpu_features: populate microblaze data --- lib/std/Target.zig | 4 +- lib/std/Target/microblaze.zig | 301 ++++++++++++++++++++++++++++++++++ tools/update_cpu_features.zig | 256 +++++++++++++++++++++++++++++ 3 files changed, 560 insertions(+), 1 deletion(-) create mode 100644 lib/std/Target/microblaze.zig diff --git a/lib/std/Target.zig b/lib/std/Target.zig index dfaa269901..c231378da4 100644 --- a/lib/std/Target.zig +++ b/lib/std/Target.zig @@ -759,7 +759,7 @@ pub const lanai = @import("Target/lanai.zig"); pub const loongarch = @import("Target/loongarch.zig"); pub const m68k = @import("Target/m68k.zig"); pub const m88k = @import("Target/m88k.zig"); -pub const microblaze = @import("Target/generic.zig"); +pub const microblaze = @import("Target/microblaze.zig"); pub const mips = @import("Target/mips.zig"); pub const msp430 = @import("Target/msp430.zig"); pub const nvptx = @import("Target/nvptx.zig"); @@ -2064,6 +2064,7 @@ pub const Cpu = struct { .loongarch64 => &loongarch.cpu.generic_la64, .m68k => &m68k.cpu.m68000, .m88k => &m88k.cpu.m88000, + .microblaze, .microblazeel => µblaze.cpu.v2_00, .mips, .mipsel => &mips.cpu.mips32, .mips64, .mips64el => &mips.cpu.mips64, .msp430 => &msp430.cpu.msp430, @@ -2132,6 +2133,7 @@ pub const Cpu = struct { .loongarch32 => &loongarch.cpu.la32v1_0, .loongarch64 => &loongarch.cpu.la64v1_0, .m68k => &m68k.cpu.m68030, + .microblaze, .microblazeel => µblaze.cpu.v7_20, .mips => &mips.cpu.mips32r2, .mipsel => switch (os.tag) { .psx => &mips.cpu.r3000a, diff --git a/lib/std/Target/microblaze.zig b/lib/std/Target/microblaze.zig new file mode 100644 index 0000000000..1a0a6844f7 --- /dev/null +++ b/lib/std/Target/microblaze.zig @@ -0,0 +1,301 @@ +//! This file is auto-generated by tools/update_cpu_features.zig. + +const std = @import("../std.zig"); +const CpuFeature = std.Target.Cpu.Feature; +const CpuModel = std.Target.Cpu.Model; + +pub const Feature = enum { + barrel, + div, + fpu, + fpu2, + msr, + mul, + mul64, + pcmp, + pipe3, + pipe8, + reorder, + v10_0, + v7_20, + v8_10, + v8_30, +}; + +pub const featureSet = CpuFeature.FeatureSetFns(Feature).featureSet; +pub const featureSetHas = CpuFeature.FeatureSetFns(Feature).featureSetHas; +pub const featureSetHasAny = CpuFeature.FeatureSetFns(Feature).featureSetHasAny; +pub const featureSetHasAll = CpuFeature.FeatureSetFns(Feature).featureSetHasAll; + +pub const all_features = blk: { + const len = @typeInfo(Feature).@"enum".field_names.len; + std.debug.assert(len <= CpuFeature.Set.needed_bit_count); + var result: [len]CpuFeature = undefined; + result[@backingInt(Feature.barrel)] = .{ + .llvm_name = null, + .description = "Enable barrel shift instructions (C_USE_BARREL)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.div)] = .{ + .llvm_name = null, + .description = "Enable hardware divide instructions (C_USE_DIV)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fpu)] = .{ + .llvm_name = null, + .description = "Enable single-precision floating point instructions (C_USE_FPU >= 1)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.fpu2)] = .{ + .llvm_name = null, + .description = "Enable floating point conversion and square root instructions (C_USE_FPU = 2)", + .dependencies = featureSet(&[_]Feature{ + .fpu, + }), + }; + result[@backingInt(Feature.msr)] = .{ + .llvm_name = null, + .description = "Enable msrset and msrclr instructions (C_USE_MSR_INSTR)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.mul)] = .{ + .llvm_name = null, + .description = "Enable 32-bit multiply instructions (C_USE_HW_MUL >= 1)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.mul64)] = .{ + .llvm_name = null, + .description = "Enable multiply high instructions (C_USE_HW_MUL = 2)", + .dependencies = featureSet(&[_]Feature{ + .mul, + }), + }; + result[@backingInt(Feature.pcmp)] = .{ + .llvm_name = null, + .description = "Enable pattern compare instructions, and clz with v8.10 (C_USE_PCMP_INSTR)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.pipe3)] = .{ + .llvm_name = null, + .description = "Tune for the 3-stage pipeline (C_AREA_OPTIMIZED = 1)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.pipe8)] = .{ + .llvm_name = null, + .description = "Tune for the 8-stage pipeline (C_AREA_OPTIMIZED = 2)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.reorder)] = .{ + .llvm_name = null, + .description = "Enable byte-reversed load/store instructions, and swapb and swaph with v8.30 (C_USE_REORDER_INSTR)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.v10_0)] = .{ + .llvm_name = null, + .description = "Enable MicroBlaze v10.0 instructions (bsefi and bsifi with barrel)", + .dependencies = featureSet(&[_]Feature{ + .v8_30, + }), + }; + result[@backingInt(Feature.v7_20)] = .{ + .llvm_name = null, + .description = "Enable MicroBlaze v7.20 instructions (lwx, swx)", + .dependencies = featureSet(&[_]Feature{}), + }; + result[@backingInt(Feature.v8_10)] = .{ + .llvm_name = null, + .description = "Enable MicroBlaze v8.10 instructions (mbar)", + .dependencies = featureSet(&[_]Feature{ + .v7_20, + }), + }; + result[@backingInt(Feature.v8_30)] = .{ + .llvm_name = null, + .description = "Enable MicroBlaze v8.30 instructions (swapb and swaph with reorder)", + .dependencies = featureSet(&[_]Feature{ + .v8_10, + }), + }; + const ti = @typeInfo(Feature); + for (&result, 0..) |*elem, i| { + elem.index = i; + elem.name = ti.@"enum".field_names[i]; + } + break :blk result; +}; + +pub const cpu = struct { + pub const v10_0: CpuModel = .{ + .name = "v10_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v10_0, + }), + }; + pub const v11_0: CpuModel = .{ + .name = "v11_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v10_0, + }), + }; + pub const v2_00: CpuModel = .{ + .name = "v2_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .pipe3, + }), + }; + pub const v2_10: CpuModel = .{ + .name = "v2_10", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .pipe3, + }), + }; + pub const v3_00: CpuModel = .{ + .name = "v3_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .pipe3, + }), + }; + pub const v4_00: CpuModel = .{ + .name = "v4_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .pipe3, + }), + }; + pub const v5_00: CpuModel = .{ + .name = "v5_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .msr, + .pcmp, + }), + }; + pub const v6_00: CpuModel = .{ + .name = "v6_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const v7_00: CpuModel = .{ + .name = "v7_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const v7_10: CpuModel = .{ + .name = "v7_10", + .llvm_name = null, + .features = featureSet(&[_]Feature{}), + }; + pub const v7_20: CpuModel = .{ + .name = "v7_20", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v7_20, + }), + }; + pub const v7_30: CpuModel = .{ + .name = "v7_30", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v7_20, + }), + }; + pub const v8_00: CpuModel = .{ + .name = "v8_00", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .reorder, + .v7_20, + }), + }; + pub const v8_10: CpuModel = .{ + .name = "v8_10", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .reorder, + .v8_10, + }), + }; + pub const v8_20: CpuModel = .{ + .name = "v8_20", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .reorder, + .v8_10, + }), + }; + pub const v8_30: CpuModel = .{ + .name = "v8_30", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v8_40: CpuModel = .{ + .name = "v8_40", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v8_50: CpuModel = .{ + .name = "v8_50", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_0: CpuModel = .{ + .name = "v9_0", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_1: CpuModel = .{ + .name = "v9_1", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_2: CpuModel = .{ + .name = "v9_2", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_3: CpuModel = .{ + .name = "v9_3", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_4: CpuModel = .{ + .name = "v9_4", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_5: CpuModel = .{ + .name = "v9_5", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; + pub const v9_6: CpuModel = .{ + .name = "v9_6", + .llvm_name = null, + .features = featureSet(&[_]Feature{ + .v8_30, + }), + }; +}; diff --git a/tools/update_cpu_features.zig b/tools/update_cpu_features.zig index 32d6bd8228..6f671855a3 100644 --- a/tools/update_cpu_features.zig +++ b/tools/update_cpu_features.zig @@ -2881,6 +2881,262 @@ const targets = [_]ArchTarget{ }, }, }, + .{ + .zig_name = "microblaze", + .llvm = null, + .extra_features = &.{ + .{ + .zig_name = "barrel", + .desc = "Enable barrel shift instructions (C_USE_BARREL)", + .deps = &.{}, + }, + .{ + .zig_name = "div", + .desc = "Enable hardware divide instructions (C_USE_DIV)", + .deps = &.{}, + }, + .{ + .zig_name = "fpu", + .desc = "Enable single-precision floating point instructions (C_USE_FPU >= 1)", + .deps = &.{}, + }, + .{ + .zig_name = "fpu2", + .desc = "Enable floating point conversion and square root instructions (C_USE_FPU = 2)", + .deps = &.{"fpu"}, + }, + .{ + .zig_name = "msr", + .desc = "Enable msrset and msrclr instructions (C_USE_MSR_INSTR)", + .deps = &.{}, + }, + .{ + .zig_name = "mul", + .desc = "Enable 32-bit multiply instructions (C_USE_HW_MUL >= 1)", + .deps = &.{}, + }, + .{ + .zig_name = "mul64", + .desc = "Enable multiply high instructions (C_USE_HW_MUL = 2)", + .deps = &.{"mul"}, + }, + .{ + .zig_name = "pcmp", + .desc = "Enable pattern compare instructions, and clz with v8.10 (C_USE_PCMP_INSTR)", + .deps = &.{}, + }, + .{ + .zig_name = "pipe3", + .desc = "Tune for the 3-stage pipeline (C_AREA_OPTIMIZED = 1)", + .deps = &.{}, + }, + .{ + .zig_name = "pipe8", + .desc = "Tune for the 8-stage pipeline (C_AREA_OPTIMIZED = 2)", + .deps = &.{}, + }, + .{ + .zig_name = "reorder", + .desc = "Enable byte-reversed load/store instructions, and swapb and swaph with v8.30 (C_USE_REORDER_INSTR)", + .deps = &.{}, + }, + .{ + .zig_name = "v7_20", + .desc = "Enable MicroBlaze v7.20 instructions (lwx, swx)", + .deps = &.{}, + }, + .{ + .zig_name = "v8_10", + .desc = "Enable MicroBlaze v8.10 instructions (mbar)", + .deps = &.{"v7_20"}, + }, + .{ + .zig_name = "v8_30", + .desc = "Enable MicroBlaze v8.30 instructions (swapb and swaph with reorder)", + .deps = &.{"v8_10"}, + }, + .{ + .zig_name = "v10_0", + .desc = "Enable MicroBlaze v10.0 instructions (bsefi and bsifi with barrel)", + .deps = &.{"v8_30"}, + }, + }, + .extra_models = &.{ + .{ + .llvm_name = null, + .zig_name = "v2_00", + .features = &.{ + "pipe3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v2_10", + .features = &.{ + "pipe3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v3_00", + .features = &.{ + "pipe3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v4_00", + .features = &.{ + "pipe3", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v5_00", + .features = &.{ + "msr", + "pcmp", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v6_00", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "v7_00", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "v7_10", + .features = &.{}, + }, + .{ + .llvm_name = null, + .zig_name = "v7_20", + .features = &.{ + "v7_20", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v7_30", + .features = &.{ + "v7_20", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_00", + .features = &.{ + "reorder", + "v7_20", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_10", + .features = &.{ + "reorder", + "v8_10", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_20", + .features = &.{ + "reorder", + "v8_10", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_30", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_40", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v8_50", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_0", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_1", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_2", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_3", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_4", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_5", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v9_6", + .features = &.{ + "v8_30", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v10_0", + .features = &.{ + "v10_0", + }, + }, + .{ + .llvm_name = null, + .zig_name = "v11_0", + .features = &.{ + "v10_0", + }, + }, + }, + }, .{ .zig_name = "msp430", .llvm = .{