mirror of
https://gitlab.com/qemu-project/qemu.git
synced 2026-10-28 14:04:39 +08:00
Brian Cain
e35867b9ca
Implement v83 restricted indirect-control-flow instructions and validate their targets. Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Reviewed-by: Marco Liebel <marco.liebel@oss.qualcomm.com> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
150 lines
4.3 KiB
C
150 lines
4.3 KiB
C
/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*
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* SPDX-License-Identifier: GPL-2.0-or-later
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*/
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#ifndef HEXAGON_GEN_TCG_SYS_H
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#define HEXAGON_GEN_TCG_SYS_H
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/* System mode instructions */
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#define fGEN_TCG_Y2_swi(SHORTCODE) \
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gen_helper_swi(tcg_env, RsV)
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#define fGEN_TCG_Y2_cswi(SHORTCODE) \
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gen_helper_cswi(tcg_env, RsV)
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#define fGEN_TCG_Y2_ciad(SHORTCODE) \
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gen_helper_ciad(tcg_env, RsV)
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#define fGEN_TCG_Y4_siad(SHORTCODE) \
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gen_helper_siad(tcg_env, RsV)
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#define fGEN_TCG_Y2_iassignw(SHORTCODE) \
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gen_helper_iassignw(tcg_env, RsV)
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#define fGEN_TCG_Y2_iassignr(SHORTCODE) \
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gen_helper_iassignr(RdV, tcg_env, RsV)
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#define fGEN_TCG_Y2_getimask(SHORTCODE) \
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gen_helper_getimask(RdV, tcg_env, RsV)
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#define fGEN_TCG_Y2_setimask(SHORTCODE) \
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gen_helper_setimask(tcg_env, PtV, RsV)
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#define fGEN_TCG_Y2_setprio(SHORTCODE) \
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gen_helper_setprio(tcg_env, PtV, RsV)
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#define fGEN_TCG_Y2_crswap0(SHORTCODE) \
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do { \
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TCGv_i32 tmp = tcg_temp_new_i32(); \
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tcg_gen_mov_tl(tmp, RxV); \
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tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP0]); \
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if (ctx->need_commit) { \
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tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \
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} else { \
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tcg_gen_mov_tl(hex_t_sreg[HEX_SREG_SGP0], tmp); \
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} \
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} while (0)
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#define fGEN_TCG_Y4_crswap1(SHORTCODE) \
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do { \
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TCGv_i32 tmp = tcg_temp_new_i32(); \
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tcg_gen_mov_tl(tmp, RxV); \
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tcg_gen_mov_tl(RxV, hex_t_sreg[HEX_SREG_SGP1]); \
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if (ctx->need_commit) { \
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tcg_gen_mov_tl(ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \
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} else { \
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tcg_gen_mov_tl(hex_t_sreg[HEX_SREG_SGP1], tmp); \
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} \
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} while (0)
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#define fGEN_TCG_Y4_crswap10(SHORTCODE) \
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do { \
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TCGv_i64 tmp = tcg_temp_new_i64(); \
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tcg_gen_mov_i64(tmp, RxxV); \
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tcg_gen_concat_i32_i64(RxxV, \
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hex_t_sreg[HEX_SREG_SGP0], \
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hex_t_sreg[HEX_SREG_SGP1]); \
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if (ctx->need_commit) { \
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tcg_gen_extrl_i64_i32( \
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ctx->t_sreg_new_value[HEX_SREG_SGP0], tmp); \
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tcg_gen_extrh_i64_i32( \
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ctx->t_sreg_new_value[HEX_SREG_SGP1], tmp); \
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} else { \
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tcg_gen_extrl_i64_i32(hex_t_sreg[HEX_SREG_SGP0], tmp); \
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tcg_gen_extrh_i64_i32(hex_t_sreg[HEX_SREG_SGP1], tmp); \
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} \
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} while (0)
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#define fGEN_TCG_Y2_wait(SHORTCODE) \
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do { \
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RsV = RsV; \
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gen_helper_wait(tcg_env); \
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} while (0)
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#define fGEN_TCG_Y2_resume(SHORTCODE) \
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do { \
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gen_helper_resume(tcg_env, RsV); \
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} while (0)
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#define fGEN_TCG_Y2_start(SHORTCODE) \
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do { \
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gen_helper_start(tcg_env, RsV); \
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} while (0)
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#define fGEN_TCG_Y2_stop(SHORTCODE) \
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do { \
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RsV = RsV; \
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gen_helper_stop(tcg_env); \
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} while (0)
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#define fGEN_TCG_Y2_tfrscrr(SHORTCODE) \
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tcg_gen_mov_tl(RdV, SsV)
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#define fGEN_TCG_Y2_tfrsrcr(SHORTCODE) \
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tcg_gen_mov_tl(SdV, RsV)
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#define fGEN_TCG_Y4_tfrscpp(SHORTCODE) \
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tcg_gen_mov_i64(RddV, SssV)
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#define fGEN_TCG_Y4_tfrspcp(SHORTCODE) \
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tcg_gen_mov_i64(SddV, RssV)
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#define fGEN_TCG_G4_tfrgcrr(SHORTCODE) \
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tcg_gen_mov_tl(RdV, GsV)
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#define fGEN_TCG_G4_tfrgrcr(SHORTCODE) \
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tcg_gen_mov_tl(GdV, RsV)
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#define fGEN_TCG_G4_tfrgcpp(SHORTCODE) \
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tcg_gen_mov_i64(RddV, GssV)
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#define fGEN_TCG_G4_tfrgpcp(SHORTCODE) \
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tcg_gen_mov_i64(GddV, RssV)
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/*
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* rte (return from exception)
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* Clear the EX bit in SSR
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* Jump to ELR
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*/
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#define fGEN_TCG_J2_rte(SHORTCODE) \
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do { \
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TCGv_i32 cfi = tcg_temp_new_i32(); \
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TCGv_i32 new_ssr = tcg_temp_new_i32(); \
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tcg_gen_extract_i32(cfi, hex_t_sreg[HEX_SREG_SSR], \
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reg_field_info[SSR_CFI].offset, 1); \
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fSET_CFI(cfi); \
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tcg_gen_deposit_tl(new_ssr, hex_t_sreg[HEX_SREG_SSR], \
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tcg_constant_tl(0), \
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reg_field_info[SSR_EX].offset, \
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reg_field_info[SSR_EX].width); \
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tcg_gen_deposit_tl(new_ssr, new_ssr, tcg_constant_tl(0), \
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reg_field_info[SSR_CFI].offset, 1); \
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gen_log_sreg_write(ctx, HEX_SREG_SSR, new_ssr); \
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gen_jumpr(ctx, hex_t_sreg[HEX_SREG_ELR]); \
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} while (0)
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#endif
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