mirror of
https://gitlab.com/qemu-project/qemu.git
synced 2026-10-28 14:04:39 +08:00
Zephyr Li
9b6fc2a751
vsepc is the VS-mode counterpart of sepc and is a WARL register, but
unlike mepc and sepc its accessors do not mask the low address bits
according to IALIGN. As a result, values with invalid low bits can be
observed through vsepc.
Apply get_xepc_mask() to both vsepc reads and writes, matching the
existing mepc/sepc handling.
Add a TCG regression test covering both IALIGN=16 and IALIGN=32.
Fixes: 8747c9eeb2 ("target/riscv: Add Hypervisor virtual CSRs accesses")
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/4420
Signed-off-by: Zephyr Li <fritchleybohrer@gmail.com>
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>
Message-ID: <20260915024945.32329-1-fritchleybohrer@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
105 lines
2.8 KiB
Meson
105 lines
2.8 KiB
Meson
tests = []
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# Multi arch tests are not supported
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# tests += tcg_tests['multiarch-softmmu']['tests']
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link_script = files('../semihost.ld')[0]
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cflags = ['-nostdlib',
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'-ffreestanding',
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'-Wa,--noexecstack',
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'-Wl,-T', link_script]
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qemu_args = ['-M', 'virt',
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'-display', 'none',
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'-serial', 'stdio',
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'-semihosting',
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'-bios']
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setup = {'cflags': cflags, 'qemu_args': qemu_args}
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tests += {
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'doubletrap.S': setup + {'plugin_test': {'plugin': 'discons'}},
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'interruptedmemory.S': setup + {'plugin_test': {'plugin': 'discons'}},
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'issue1060.S': setup,
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'test-mepc-masking.S': setup,
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'test-crc32.S': setup + {'qemu_args': ['-cpu', 'rv64,xlrbr=true', qemu_args]},
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'test-minstret-ecall.S': setup + {'qemu_args': ['-icount', 'shift=1', qemu_args]},
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'test-minstret-wfi.S': setup + {'qemu_args': ['-icount', 'shift=1', qemu_args]},
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'test-misa-w.S': setup + {'qemu_args': ['-cpu', 'rv64,x-misa-w=true,c=true,v=true', qemu_args]},
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'test-zvabd.S': setup + {'qemu_args': ['-cpu', 'rv64,v=true,vlen=256,x-zvabd=true', qemu_args]},
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'test-vsepc-masking.S': setup + {
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'test_name': 'test-vsepc-masking-c',
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'qemu_args': ['-cpu', 'rv64,h=true,c=true', qemu_args],
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},
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}
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tests += {
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'test-vsepc-masking.S': {
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'test_name': 'test-vsepc-masking-no-c',
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'qemu_args': ['-cpu', 'rv64,h=true,c=false,zca=false', qemu_args],
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},
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}
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tests += {
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'test-rv128-mstatus.S': {
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'cflags': cflags,
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'qemu_args': ['-cpu', 'x-rv128', qemu_args],
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}
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}
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tests += {
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'test-rv128-sstatus.S': {
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'cflags': cflags,
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'qemu_args': ['-cpu', 'x-rv128', qemu_args],
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}
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}
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tests += {
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'test-vle32ff.S': {
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'cflags': cflags + ['-march=rv64gcv'],
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'qemu_args': ['-cpu', 'rv64,v=true', qemu_args],
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}
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}
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tests += {
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'test-zicclsm.S': {
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'cflags': cflags + ['-march=rv64gcv_zfh'],
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'qemu_args': ['-cpu', 'rv64,v=true,zfh=true,zicclsm=true', qemu_args],
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}
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}
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tests += {
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'test-zicclsm.S': {
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'exe_name': 'test-zicclsm-off',
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'cflags': cflags + ['-march=rv64gcv_zfh', '-DZICCLSM_DISABLED'],
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'qemu_args': ['-cpu', 'rv64,v=true,zfh=true,zicclsm=false', qemu_args],
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}
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}
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tests += {
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'test-sdext-sigill.S': {
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'exe_name': 'test-sdext-sigill',
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'cflags': cflags + ['-march=rv64gcv'],
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'qemu_args': ['-cpu', 'rv64,sdtrig=true,sdext=true', qemu_args],
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}
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}
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tests += {
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'test-xsfvqmacc.S': {
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'cflags': cflags,
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'qemu_args': ['-cpu', 'rv64,v=true,vlen=256,xsfvqmaccdod=true,xsfvqmaccqoq=true', qemu_args],
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}
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}
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if 'qemu-system-riscv64' in emulators
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tcg_tests += {
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'riscv64-softmmu': {
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'cc': 'riscv64-linux-gnu-gcc',
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'cc_alt': ['riscv64-redhat-linux-gnu-gcc', 'riscv64-elf-gcc'],
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'cc_dockerfile': 'debian-all-test-cross',
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'folder': 'riscv64',
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'gdb_arch': 'riscv64',
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'qemu': emulators['qemu-system-riscv64'],
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'tests': tests,
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}
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}
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endif
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