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Peter Maydell c513597761 Merge tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu into staging

semihosting, fix exc/int, icinva, TLB, htid

# -----BEGIN PGP SIGNATURE-----
#
# iQIzBAABCgAdFiEEPWaq5HRZSCTIjOD4GlSvuOVkbDIFAmqXqBoACgkQGlSvuOVk
# bDL0Tw/9EL4g0nvPQKWbFAbs29GId6RVVS3fNRiHPFgSJSULqYDEkvbTip44gsJ5
# Km4rwJy7nRI6d0tdVZYATLGcP/d+OTWxHxQM4/D7WemK3QEYfSMLLnX0d2aGhuH/
# Okncy0j7b5ogUi+ALbCf5MPeUzrK8x7YFqw7utzeE9QYkyeSorhcpLfLSiHm4ECy
# PoWH2kkFZwrEWdXfTTdHeRLIE1FXVGLL0SYh3vatE5kvh9kBnuyKpHR7Cq7zT+A9
# Fh84i9U7afDsRKrpvPArICqvcybdYFw+wBFgIMMea5jkx1+aHTwJ7NdvIZzjTDx+
# RjVdcm3DlucW+y7qEM+d3kGbLcBSG0Q+yJ02LYqLIp9nBELP4rdKVRC0csegZM03
# zj8EFH4QilrVLSsq4KqhLIBiOMqlz6THWVDxEq8xGCvb9vpAUP5c70BsCY5IF9TZ
# XL2ZhgQ+gkQJ4aPV+XOlkC8hn4dbovNu/0cME76v8MNX1iwQrMwC4GJ/N1qfC4jY
# 3EEkmaW3HGXvFvlAFO5T9eLfXUGmVK+tNLc8pZLV/rDLWiQjs6HYD8XZeq9Goo8N
# gIoa//9ZhgjXKNF+e06BCcqvfaaXXLkaX7n5a5NXQVvebB4FsF53myM3mTwGVmgx
# N5I32V15sAJGMgd0/rrgwKhWoDZcOLZGVLCtqI7i2vT178e+pqA=
# =zqar
# -----END PGP SIGNATURE-----
# gpg: Signature made Wed Sep  2 05:37:46 2026 BST
# gpg:                using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown]
# gpg:                 aka "Brian Cain <bcain@kernel.org>" [full]
# gpg:                 aka "Brian Cain (QuIC) <bcain@quicinc.com>" [full]
# gpg:                 aka "Brian Cain (CAF) <bcain@codeaurora.org>" [full]
# gpg:                 aka "bcain" [full]
# gpg:                 aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF  49E0 175C 464E 541B 6D47
#      Subkey fingerprint: 3D66 AAE4 7459 4824 C88C  E0F8 1A54 AFB8 E564 6C32

* tag 'pull-hex-20260901' of https://github.com/qualcomm/qemu: (28 commits)
  hw/hexagon: decode an empty TLB size field as 4KB
  hw/hexagon: assign a distinct htid to each DSP machine CPU
  tests/tcg/hexagon: add icinva test
  target/hexagon: invalidate translated code for user icinva
  tests/functional/hexagon: update to v0.2.12, +test_{interrupts, sys_regs}
  target/hexagon: fix iassign{r, w} to cover all threads
  target/hexagon: implement direct-to-guest interrupt delivery
  target/hexagon: raise imprecise exception on multi-TLB match
  target/hexagon: read UTIMERLO/UTIMERHI from the global timer
  target/hexagon: gate GPCYCLE guest register reads on SSR:CE
  target/hexagon: take BQL when reading the system pcycle count
  target/hexagon: guard writes to unimplemented guest registers
  hw/intc: clear pending bit on l2vic de-assertion
  tests/tcg/hexagon: check priv instructions raise SIGILL
  target/hexagon: align exceptions for user/sysemu
  tests/functional: Add hexagon semihosting systests
  python/machine: support routing semihosting output to the test console
  target/hexagon: Add an errno mapping
  target/hexagon: add COREDUMP semihosting operation
  target/hexagon: add main arch-specific semihosting operations
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>

# Conflicts:
#	hw/hexagon/hexagon_tlb.c

2026-09-02 17:59:30 +01:00