mirror of
https://gitlab.com/qemu-project/qemu.git
synced 2026-10-28 11:54:41 +08:00
Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com> Acked-by: Alistair Francis <alistair.francis@wdc.com> Link: https://lore.kernel.org/qemu-devel/20261024061616.27381-2-pierrick.bouvier@oss.qualcomm.com Signed-off-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
128 lines
2.1 KiB
C
128 lines
2.1 KiB
C
/*
|
|
* QEMU target info helpers
|
|
*
|
|
* Copyright (c) Linaro
|
|
*
|
|
* SPDX-License-Identifier: GPL-2.0-or-later
|
|
*/
|
|
|
|
#include "qemu/osdep.h"
|
|
#include "qemu/target-info.h"
|
|
#include "qemu/target-info-qapi.h"
|
|
#include "qemu/target-info-def.h"
|
|
#include "qapi/error.h"
|
|
|
|
const char *target_name(void)
|
|
{
|
|
return target_info()->target_name;
|
|
}
|
|
|
|
unsigned target_long_bits(void)
|
|
{
|
|
return target_info()->long_bits;
|
|
}
|
|
|
|
SysEmuTarget target_arch(void)
|
|
{
|
|
return target_info()->target_arch;
|
|
}
|
|
|
|
const char *target_cpu_type(void)
|
|
{
|
|
return target_info()->cpu_type;
|
|
}
|
|
|
|
EndianMode target_endian_mode(void)
|
|
{
|
|
return target_info()->endianness;
|
|
}
|
|
|
|
bool target_big_endian(void)
|
|
{
|
|
return target_endian_mode() == ENDIAN_MODE_BIG;
|
|
}
|
|
|
|
bool target_heterogeneous(void)
|
|
{
|
|
/* For now, we only run a single target at a time */
|
|
return false;
|
|
}
|
|
|
|
bool target_base_arm(void)
|
|
{
|
|
switch (target_arch()) {
|
|
case SYS_EMU_TARGET_ARM:
|
|
case SYS_EMU_TARGET_AARCH64:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool target_arm(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_ARM;
|
|
}
|
|
|
|
bool target_aarch64(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_AARCH64;
|
|
}
|
|
|
|
bool target_m68k(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_M68K;
|
|
}
|
|
|
|
bool target_hexagon(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_HEXAGON;
|
|
}
|
|
|
|
bool target_or1k(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_OR1K;
|
|
}
|
|
|
|
bool target_base_ppc(void)
|
|
{
|
|
switch (target_arch()) {
|
|
case SYS_EMU_TARGET_PPC:
|
|
case SYS_EMU_TARGET_PPC64:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool target_ppc(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_PPC;
|
|
}
|
|
|
|
bool target_ppc64(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_PPC64;
|
|
}
|
|
|
|
bool target_s390x(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_S390X;
|
|
}
|
|
|
|
bool target_base_riscv(void)
|
|
{
|
|
switch (target_arch()) {
|
|
case SYS_EMU_TARGET_RISCV32:
|
|
case SYS_EMU_TARGET_RISCV64:
|
|
return true;
|
|
default:
|
|
return false;
|
|
}
|
|
}
|
|
|
|
bool target_riscv64(void)
|
|
{
|
|
return target_arch() == SYS_EMU_TARGET_RISCV64;
|
|
}
|