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Richard Henderson
d29412cca5
RISC-V PR for 11.2 * Add experimental Zvabd extension support * Mask vsepc according to IALIGN * Reset vCPU on VM reset via MP_STATE_INIT_RECEIVED * Improve modeling of the Atlantis UART * Fix IOMMU entry leak with ioatc-limit=0 * Fix integer handling issues in k230_gsdma and k230_decomp_gzip * Reclaim invalidated IOATC entries for IOMMU * Duct tape fix for QMP and RV profiles introspection * Move RISC-V 'Z' CPU properties section to removed features * Use TSO barriers instead of full barriers for Ztso * Make mnstatus.MNPELP writable with Zicfilp * Gate envcfg CBO fields on extensions * Fix stale PMP state across reset * Use 1ULL for a value we're going to shift by 63 * Remove unused IMISC macro * Encode debug translation ranges in IOMMU * Allow regular mstatus MPV/GVA writes again * Fix uninitialised upper half in pmu_timer_trigger_irq * Fix CPU state access on big-endian hosts # -----BEGIN PGP SIGNATURE----- # # iQIzBAABCgAdFiEEaukCtqfKh31tZZKWr3yVEwxTgBMFAmrgREAACgkQr3yVEwxT # gBPBHxAAmIzV1LXJAxQTvU46+1j+4+mSvGr37byb1iU8yg+dJCNtYpFLHKdNjF0Q # Fn+5uBL+QJC3rEA0Xbq6iF4EP2GO8t/Qm4rElLmWCw1xzraj7RAZrNJHWCebLp1j # PLS53gINaQNIuE6DC91mwcuWanKo7q+tvOiwcShaVyUH771J1+1xVOkpcbkQaVrZ # a54IfHIcs4TIsKrpmxCJPkEuBcL4VtaK5JwcqbeCQQ68v7L7qQpec75t9idr3o25 # Pn/BOsHwkXoJ1qxFuY61JGhUpFKUzZIqd6HKqwv4SENZY+O87J79R9X/HU9H17xh # B75+h91ZFSZ2luNd2vZCCMx4vOXuCa+YE/m0ZmyyjJnGLA4LHRoeFRmUUu5Dxzkn # kP+psnaeUfcI6W71d8Dcqov1g1O7MBdVrQD1hzK8IeAuYL438cLZpo9WT6TVX5cn # /DRCyDR4f6uzf8Lnh0wItJGzSUlW2xadFLu357KsJ0+lpytpmYolOBxUGJXtJu2g # BSfgQX9y9xhszCbFopngunu3guOlDoHZEJ9l29+tXicezvJxXw+FRyc4EU3onRtz # zXGWa7sN4XGifzoDorbVcWGpOT2w2LI1himS4N9qXWNCZ4s115xENMVCMDRt6a9Z # aZRyBib2nbrrgnO4JJbxBUe/MViBfQlc+AuqMmEwrwdP3LRBbZA= # =qxZ6 # -----END PGP SIGNATURE----- # gpg: Signature made Tue 27 Oct 2026 01:27:12 AM CDT # gpg: using RSA key 6AE902B6A7CA877D6D659296AF7C95130C538013 # gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 6AE9 02B6 A7CA 877D 6D65 9296 AF7C 9513 0C53 8013 * tag 'pull-riscv-to-apply-20261027' of https://github.com/alistair23/qemu: (29 commits) target/riscv: Fix CPU state access on big-endian hosts target/riscv: fix uninitialised upper half in pmu_timer_trigger_irq() target/riscv/csr.c: allow regular mstatus MPV/GVA writes again hw/riscv/riscv-iommu: encode debug translation ranges include/hw/intc/riscv_imsic.h: remove unused macro target/riscv: Use 1ULL for a value we're going to shift by 63 target/riscv: pmp: reset the derived PMP bounds and rule count target/riscv: pmp: clear A and L on every implemented PMP entry at reset target/riscv: gate envcfg CBO fields on extensions target/riscv: make mnstatus.MNPELP writable with Zicfilp target/riscv: Use TSO barriers instead of full barriers for Ztso docs: Move RISC-V 'Z' CPU properties section to removed features target/riscv/cpu.c: duct tape fix for QMP + RV profiles introspection hw/riscv/riscv-iommu: reclaim invalidated IOATC entries hw/riscv/riscv-iommu: serialize IOATC accesses hw/dma: fix k230_gsdma integer handling issues qtest: fix k230_decomp_gzip test integer handling issues hw/misc: use hwaddr for the k230_decomp_gzip input address hw/misc: fix calculating input address overflow in k230_decomp_gzip hw/misc: fix calculating output address overflow in k230_decomp_gzip ... Signed-off-by: Richard Henderson <richard.henderson@linaro.org>