From 4dff005e1d9354730863149945e443868c775df1 Mon Sep 17 00:00:00 2001 From: Brian Cain Date: Thu, 22 Oct 2026 16:00:43 -0700 Subject: [PATCH] hw/hexagon: add the SM8975 NSP machine Reviewed-by: Pierrick Bouvier Signed-off-by: Brian Cain --- hw/hexagon/Kconfig | 6 ++ hw/hexagon/machine_cfg_sm8975_nsp.h.inc | 55 +++++++++++++ hw/hexagon/meson.build | 1 + hw/hexagon/sm8975_nsp.c | 102 ++++++++++++++++++++++++ include/hw/hexagon/hexagon.h | 1 + tests/qtest/l2vic-test.c | 2 + tests/qtest/qcom-dsp-test.c | 17 ++++ tests/qtest/qct-qtimer-test.c | 2 + 8 files changed, 186 insertions(+) create mode 100644 hw/hexagon/machine_cfg_sm8975_nsp.h.inc create mode 100644 hw/hexagon/sm8975_nsp.c diff --git a/hw/hexagon/Kconfig b/hw/hexagon/Kconfig index bcf368cb8b..177d87f7f9 100644 --- a/hw/hexagon/Kconfig +++ b/hw/hexagon/Kconfig @@ -54,3 +54,9 @@ config HEX_SA8797P_NSP0 default y depends on HEX_DSP && FDT select HEX_QCOM_DSP + +config HEX_SM8975_NSP + bool + default y + depends on HEX_DSP && FDT + select HEX_QCOM_DSP diff --git a/hw/hexagon/machine_cfg_sm8975_nsp.h.inc b/hw/hexagon/machine_cfg_sm8975_nsp.h.inc new file mode 100644 index 0000000000..b97e788093 --- /dev/null +++ b/hw/hexagon/machine_cfg_sm8975_nsp.h.inc @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +/* + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + */ + +/* Config table of the SM8975 NSP. */ +static const struct hexagon_machine_config sm8975_nsp = { + .ddr_base = 0x80000000, + .cfgbase = 0x24180000, + .l2tcm_size = 0x100000, + .l2vic_base = 0x26390000, + .l2vic_size = 0x1000, + .csr_base = 0x263a0000, + .qtmr_region = 0x263a1000, + .cfgtable = { + .l2tcm_base = 0x2400, + .subsystem_base = 0x2638, + .etm_base = 0x2419, + .l2cfg_base = 0x241a, + .l1s0_base = 0x2500, + .fastl2vic_base = 0x241e, + .jtlb_size_entries = 0x80, + .coproc_present = 0x1d, + .ext_contexts = 8, + .vtcm_base = 0x2500, + .vtcm_size_kb = 0x3000, + .l2tag_size = 0x400, + .l2ecomem_size = 0x400, + .thread_enable_mask = 0xfff, + .l2line_size = 0x80, + .l2itcm_base = 0x2400, + .dma_version = 0xc, + .hvx_vec_log_length = 7, + .coproc2_reg0 = 0x10, + .coproc2_reg1 = 8, + .coproc2_reg2 = 3, + .acd_preset = 1, + .mnd_preset = 1, + .l1d_size_kb = 0x40, + .l1i_size_kb = 0x40, + .l1d_write_policy = 2, + .vtcm_bank_width = 0x80, + .consistency_domain = 0xe0, + .capacity_domain = 0x80, + .axi3_lowaddr = 0x4000, + .corecfg_present = 0xd, + .coproc2_fp16_acc_exp = 3, + .AXIM_data_width = 0x100, + .l1d_ways = 8, + .l1i_ways = 4, + .l2way_num = 8, + .dma_jtlb_entries = 0x40, + }, +}; diff --git a/hw/hexagon/meson.build b/hw/hexagon/meson.build index 5a10ae694f..fa5bc5eb9f 100644 --- a/hw/hexagon/meson.build +++ b/hw/hexagon/meson.build @@ -11,5 +11,6 @@ hexagon_ss.add(when: 'CONFIG_HEX_QCS6490_CDSP', if_true: files('qcs6490_cdsp.c') hexagon_ss.add(when: 'CONFIG_HEX_SA8775P_CDSP', if_true: files('sa8775p_cdsp.c')) hexagon_ss.add(when: 'CONFIG_HEX_SC8480XP_NSP0', if_true: files('sc8480xp_nsp0.c')) hexagon_ss.add(when: 'CONFIG_HEX_SA8797P_NSP0', if_true: files('sa8797p_nsp0.c')) +hexagon_ss.add(when: 'CONFIG_HEX_SM8975_NSP', if_true: files('sm8975_nsp.c')) hw_arch += {'hexagon': hexagon_ss} diff --git a/hw/hexagon/sm8975_nsp.c b/hw/hexagon/sm8975_nsp.c new file mode 100644 index 0000000000..91790c8423 --- /dev/null +++ b/hw/hexagon/sm8975_nsp.c @@ -0,0 +1,102 @@ +/* + * sm8975-nsp machine. + * + * Models the Hexagon v85 NSP of the SM8975. + * + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "hw/core/boards.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/qcom_dsp.h" +#include "target/hexagon/cpu.h" + +#include "machine_cfg_sm8975_nsp.h.inc" + +#define TYPE_SM8975_NSP_MACHINE MACHINE_TYPE_NAME("sm8975-nsp") + +static const QcomDspRegion sm8975_nsp_regions[] = { + { "dspss-pub", 0x26300000, 0x10000 }, + { "wdog", 0x26384000 }, + { "turing-cc", 0x26008000, 0x14000 }, + { "pll", 0x26340000 }, + { "clkctl", 0x26344000, 0x4000 }, + { "compute-rsc", 0x260a4000 }, + { "qdsp6-rsc", 0x263c0000 }, + { "ipcc", 0x01100000 }, + { "tcsr", 0x26080000, 0x1f000 }, + { "turing-cc-pll", 0x26000000 }, + { "turing-cc-pll", 0x26001000 }, + { "turing-cc-pll", 0x26002000 }, + { "turing-cc-pll", 0x26003000 }, + { "turing-cc-pll", 0x26004000 }, + { "ahb2phy", 0x26006000, 0x2000 }, + { "ahbe-time", 0x260b7000 }, + { "nsp-noc", 0x260c0000, 0x21280 }, + { "ceng", 0x26260000, 0xc000 }, + { "ceng-irq", 0x2626c000 }, + { "ubwcd", 0x26280000, 0x10000 }, + { "vapss", 0x262c0000, 0x40000 }, + { "llm-isense", 0x26310000, 0x10000 }, + { "lpm-stats", 0x26320000, 0x10000 }, + { "mxu-pll", 0x26348000 }, + { "acd-mnd-dcc", 0x26350000, 0x800 }, + { "hmx-acd-mnd-dcc", 0x26350800, 0x800 }, + { "gcc", 0x00100000, 0x200000 }, + { "fuse", 0x221c8000 }, + { "hmx-swman", 0x2634a000, 0x400 }, + { "hmx-broadcast", 0x2634b000, 0x400 }, + { "hmx-cc", 0x2634c000, 0x4000 }, + { "ipcc-legacy", 0x26380000 }, + { "pinctrl", 0x0f100000, 0x0f00000 }, + { "llcc", 0x31800000, 0x200000 }, + { "llcc", 0x31c00000, 0x200000 }, + { "llcc", 0x32800000, 0x200000 }, + { "llcc", 0x32c00000, 0x200000 }, + { "llcc", 0x34800000, 0x200000 }, + { "llcc", 0x34c00000, 0x200000 }, + { "stmtrace", 0x16000000, 0x1000000 }, + { "stmcfg", 0x10002000 }, + { "etb", 0x11305000 }, + { "tpdm", 0x11181000, 0x2000 }, + { "tpdm", 0x11185000, 0x2000 }, + { "funnel", 0x10041000 }, + { "funnel", 0x11304000 }, + { "tpda", 0x11188000 }, +}; + +static void sm8975_nsp_init_devices(MachineState *ms) +{ + qcom_dsp_add_regions(ms, sm8975_nsp_regions, + ARRAY_SIZE(sm8975_nsp_regions)); + + qcom_soc_add_qup_geni_ports("sm8975", 0x08180000, 8, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x08280000, 8, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x01980000, 6, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x01a80000, 5, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x00a80000, 8, 0x4000); + qcom_soc_add_qup_geni_ports("sm8975", 0x00880000, 5, 0x4000); +} + +static const QcomDspMachineInfo sm8975_nsp_info = { + .desc = "SM8975 NSP", + .cpu_type = HEXAGON_CPU_TYPE_NAME("v85"), + .cpus = 12, + .rev = v85_sm8975_rev, + .cfg = &sm8975_nsp, + .kernel_addr = 0xa0000000, + .init_devices = sm8975_nsp_init_devices, +}; + +static const TypeInfo sm8975_nsp_types[] = { + { + .name = TYPE_SM8975_NSP_MACHINE, + .parent = TYPE_QCOM_DSP_MACHINE, + .class_init = qcom_dsp_class_init, + .class_data = &sm8975_nsp_info, + }, +}; + +DEFINE_TYPES(sm8975_nsp_types) diff --git a/include/hw/hexagon/hexagon.h b/include/hw/hexagon/hexagon.h index 1e565d6165..f3aee4a42e 100644 --- a/include/hw/hexagon/hexagon.h +++ b/include/hw/hexagon/hexagon.h @@ -34,6 +34,7 @@ typedef enum { v81dgb_1_rev = 0xcc81, v85qa_1_rev = 0x8185, v85na_1_rev = 0x8085, + v85_sm8975_rev = v85na_1_rev, } Rev_t; #define HEXAGON_LATEST_REV v85 #define HEXAGON_LATEST_REV_UPPER V85 diff --git a/tests/qtest/l2vic-test.c b/tests/qtest/l2vic-test.c index 4cd0319e8b..82f93fd58f 100644 --- a/tests/qtest/l2vic-test.c +++ b/tests/qtest/l2vic-test.c @@ -12,6 +12,7 @@ #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sm8975_nsp.h.inc" #include "hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" @@ -53,6 +54,7 @@ static const L2VICMachineCfg l2vic_machines[] = { { "sa8775p-cdsp", &SA8775P_cdsp0 }, { "sc8480xp-nsp0", &sc8480xp_nsp0 }, { "sa8797p-nsp0", &sa8797p_nsp0 }, + { "sm8975-nsp", &sm8975_nsp }, }; static uint32_t l2vic_read32(uint64_t base, uint32_t offset) diff --git a/tests/qtest/qcom-dsp-test.c b/tests/qtest/qcom-dsp-test.c index def389a0e9..9cca6a835d 100644 --- a/tests/qtest/qcom-dsp-test.c +++ b/tests/qtest/qcom-dsp-test.c @@ -9,6 +9,8 @@ #include "qemu/osdep.h" #include "libqtest.h" #include "libqtest-single.h" +#include "hw/hexagon/hexagon.h" +#include "hw/hexagon/machine_cfg_sm8975_nsp.h.inc" #define QCOM_DSP_UART_BASE 0x37000000 #define QCOM_DSP_VIRTIO_BASE 0x37010000 @@ -27,6 +29,7 @@ static const char *const qcom_dsp_machines[] = { "sa8775p-cdsp", "sc8480xp-nsp0", "sa8797p-nsp0", + "sm8975-nsp", }; static void test_console(const void *machine) @@ -76,6 +79,18 @@ static void test_default_drive(const void *machine) qtest_end(); } +static void test_tcm(const void *unused) +{ + uint64_t base = (uint64_t)sm8975_nsp.cfgtable.l2tcm_base << 16; + + qtest_start("-machine sm8975-nsp"); + writel(base, 0xdeadbeef); + writel(base + sm8975_nsp.l2tcm_size - 4, 0xcafef00d); + g_assert_cmphex(readl(base), ==, 0xdeadbeef); + g_assert_cmphex(readl(base + sm8975_nsp.l2tcm_size - 4), ==, 0xcafef00d); + qtest_end(); +} + int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); @@ -92,5 +107,7 @@ int main(int argc, char **argv) qtest_add_data_func(path, name, test_default_drive); } + qtest_add_data_func("/qcom-dsp/sm8975-nsp/tcm", NULL, test_tcm); + return g_test_run(); } diff --git a/tests/qtest/qct-qtimer-test.c b/tests/qtest/qct-qtimer-test.c index 21870de564..b4c1b9e37f 100644 --- a/tests/qtest/qct-qtimer-test.c +++ b/tests/qtest/qct-qtimer-test.c @@ -13,6 +13,7 @@ #include "hw/hexagon/machine_cfg_v68n_1024.h.inc" #include "hw/hexagon/machine_cfg_v66g_1024.h.inc" #include "hw/hexagon/machine_cfg_qcs6490_cdsp.h.inc" +#include "hw/hexagon/machine_cfg_sm8975_nsp.h.inc" #include "hw/hexagon/machine_cfg_sa8797p_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sc8480xp_nsp0.h.inc" #include "hw/hexagon/machine_cfg_sa8775_cdsp0.h.inc" @@ -350,6 +351,7 @@ static const QtimerMachineCfg qtimer_machines[] = { { "sa8775p-cdsp", &SA8775P_cdsp0 }, { "sc8480xp-nsp0", &sc8480xp_nsp0 }, { "sa8797p-nsp0", &sa8797p_nsp0 }, + { "sm8975-nsp", &sm8975_nsp }, }; static void test_qtimer_on_machine(gconstpointer data)