hw/hexagon: add hex-subsys

The virt and DSP machine models build the same core subsystem, let's
abstract out that part.  Start with the DDR and config table ROM setup.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>
Link: https://lore.kernel.org/qemu-devel/20260806042723.3785369-2-brian.cain@oss.qualcomm.com
Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>

hw/hexagon/hex-subsys.c

@@ -0,0 +1,32 @@
+/*
+ * Hexagon subsystem helpers shared between the machine models.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#include "hw/hexagon/hex-subsys.h"
+#include "hw/core/loader.h"
+#include "system/address-spaces.h"
+
+void hex_subsys_create(HexagonCommonMachineState *hms,
+                       const struct hexagon_machine_config *m_cfg)
+{
+    MachineState *machine = MACHINE(hms);
+    MemoryRegion *sysmem = get_system_memory();
+
+    /* Main DDR at the reset vector. */
+    memory_region_init_ram(&hms->ram, NULL, "ddr.ram", machine->ram_size,
+                           &error_fatal);
+    memory_region_add_subregion(sysmem, 0x0, &hms->ram);
+
+    /* Config-table ROM and the blob that backs it. */
+    memory_region_init_rom(&hms->cfgtable_rom, NULL, "config_table.rom",
+                           sizeof(m_cfg->cfgtable), &error_fatal);
+    memory_region_add_subregion(sysmem, m_cfg->cfgbase, &hms->cfgtable_rom);
+    rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable,
+                          sizeof(m_cfg->cfgtable), m_cfg->cfgbase,
+                          &address_space_memory);
+}

hw/hexagon/hexagon_dsp.c

@@ -14,6 +14,7 @@
 #include "hw/core/boards.h"
 #include "hw/core/qdev-properties.h"
 #include "hw/hexagon/hexagon.h"
+#include "hw/hexagon/hex-subsys.h"
 #include "hw/hexagon/hexagon_globalreg.h"
 #include "hw/hexagon/hexagon_tlb.h"
 #include "hw/core/loader.h"
@@ -108,7 +109,6 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
 {
     HexagonCommonMachineState *hms = HEXAGON_COMMON_MACHINE(machine);
     HexagonDspMachineState *dms = HEXAGON_DSP_MACHINE(machine);
-    MemoryRegion *address_space;
     DeviceState *glob_regs_dev;
     DeviceState *tlb_dev;
 
@@ -120,16 +120,7 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
 
     machine->enable_graphics = 0;
 
-    address_space = get_system_memory();
-
-    memory_region_init_rom(&hms->cfgtable_rom, NULL, "config_table.rom",
-                           sizeof(m_cfg->cfgtable), &error_fatal);
-    memory_region_add_subregion(address_space, m_cfg->cfgbase,
-                                &hms->cfgtable_rom);
-
-    memory_region_init_ram(&hms->ram, NULL, "ddr.ram",
-                           machine->ram_size, &error_fatal);
-    memory_region_add_subregion(address_space, 0x0, &hms->ram);
+    hex_subsys_create(hms, m_cfg);
 
     glob_regs_dev = qdev_new(TYPE_HEXAGON_GLOBALREG);
     object_property_add_child(OBJECT(machine), "global-regs",
@@ -162,10 +153,6 @@ static void hexagon_common_init(MachineState *machine, Rev_t rev,
                                  OBJECT(tlb_dev), &error_fatal);
         qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal);
     }
-
-    rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable,
-                          sizeof(m_cfg->cfgtable), m_cfg->cfgbase,
-                          &address_space_memory);
 }
 
 static void init_mc(MachineClass *mc)

hw/hexagon/meson.build

@@ -1,6 +1,7 @@
 hexagon_ss = ss.source_set()
 hexagon_ss.add(files('hexagon_tlb.c'))
 hexagon_ss.add(files('hexagon_globalreg.c'))
+hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hex-subsys.c'))
 hexagon_ss.add(when: 'CONFIG_HEX_DSP', if_true: files('hexagon_dsp.c'))
 hexagon_ss.add(when: 'CONFIG_HEX_VIRT', if_true: files('virt.c'))
 

hw/hexagon/virt.c

@@ -13,6 +13,7 @@
 #include "hw/core/clock.h"
 #include "hw/core/sysbus-fdt.h"
 #include "hw/hexagon/hexagon.h"
+#include "hw/hexagon/hex-subsys.h"
 #include "hw/hexagon/hexagon_globalreg.h"
 #include "hw/hexagon/hexagon_tlb.h"
 #include "hw/core/loader.h"
@@ -244,9 +245,7 @@ static void virt_init(MachineState *ms)
     vms->apb_clk = clock_new(OBJECT(ms), "apb-pclk");
     clock_set_hz(vms->apb_clk, 24000000);
 
-    memory_region_init_ram(&vms->parent_obj.ram, NULL, "ddr.ram",
-                           ms->ram_size, &error_fatal);
-    memory_region_add_subregion(vms->sys, 0x0, &vms->parent_obj.ram);
+    hex_subsys_create(&vms->parent_obj, m_cfg);
 
     if (m_cfg->l2tcm_size) {
         memory_region_init_ram(&vms->tcm, NULL, "tcm.ram", m_cfg->l2tcm_size,
@@ -255,11 +254,6 @@ static void virt_init(MachineState *ms)
                                     &vms->tcm);
     }
 
-    memory_region_init_rom(&vms->parent_obj.cfgtable_rom, NULL,
-                           "config_table.rom", sizeof(m_cfg->cfgtable),
-                           &error_fatal);
-    memory_region_add_subregion(vms->sys, m_cfg->cfgbase,
-                                &vms->parent_obj.cfgtable_rom);
     fdt_add_hvx(vms, m_cfg);
 
     gsregs_dev = qdev_new(TYPE_HEXAGON_GLOBALREG);
@@ -302,10 +296,6 @@ static void virt_init(MachineState *ms)
     clk_phandle = fdt_add_clocks(vms);
     fdt_add_uart(vms, VIRT_UART0, clk_phandle);
 
-    rom_add_blob_fixed_as("config_table.rom", &m_cfg->cfgtable,
-                          sizeof(m_cfg->cfgtable), m_cfg->cfgbase,
-                          &address_space_memory);
-
     hexagon_load_fdt(vms);
 }
 

include/hw/hexagon/hex-subsys.h

@@ -0,0 +1,17 @@
+/*
+ * Hexagon subsystem helpers shared between the machine models.
+ *
+ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef HW_HEXAGON_HEX_SUBSYS_H
+#define HW_HEXAGON_HEX_SUBSYS_H
+
+#include "hw/hexagon/hexagon.h"
+
+/* Create the subsystem shared by every Hexagon machine. */
+void hex_subsys_create(HexagonCommonMachineState *hms,
+                       const struct hexagon_machine_config *m_cfg);
+
+#endif /* HW_HEXAGON_HEX_SUBSYS_H */