mirror of
https://github.com/numpy/numpy.git
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Sayed Adel
822665c9c3
**IMPORTANT NOTE**: The default setting for `cpu-baseline`` on x86 has been raised to `x86-64-v2` microarchitecture.
This can be changed to `cpu-baseline=none` during build time to support older CPUs, though manual SIMD optimizations for pre-2009 processors are no longer supported.
This patch reorganizes CPU build options by replacing individual x86 features with microarchitecture levels.
This change aligns with the Google Highway requirements and common Linux distribution practices.
This patch:
- Removes all individual x86 features and replaces them with three microarchitecture
levels (`X86_V2`, `X86_V3`, `X86_V4`) commonly used by Linux distributions
- Raises the baseline to microarchitecture level 2 (replacing `SSE3`) since all known
x86 CPUs since 2009 support it. This improves performance and
reduces binary size
- Updates documentation to to reflect these changes and to fit the current meson build system.
- Corrects the behavior of the `-` operator, which now excludes successor features
that imply the excluded feature
- Adds redirection via meson for removed feature names to avoid breaking builds
- Removes compiler compatibility workarounds, so features like AVX512 without full mask operations
will be considered unsupported rather than providing fallbacks
Detailed CPU features changes:
- Removes individual features (`SSE`, `SSE2`, `SSE3`, `SSSE3`, `SSE4_1`, `SSE4_2`,
`POPCNT`) which are now part of the new group `X86_V2`
- Removes AMD legacy features (`XOP`, `FMA4`)
- Removes Xeon Phi support (`AVX512_KNL`, `AVX512_KNM`) which Intel has discontinued
- Removes individual features (`AVX`, `AVX2`, `FMA3`, `F16C`) which are now part
of the new group `X86_V3`
- Removes individual features `AVX512F`, `AVX512CD` as a result of dropping Xeon Phi support
- Renames group `AVX512_SKX` to `x86_v4` to align with microarchitecture level naming
- Removes groups `AVX512_CLX` and `AVX512_CNL` (features available via `AVX512_ICL`)
- Updates `AVX512_ICL` to include features (`VAES`, `GFNI`, `VPCLMULQDQ`) for alignment
with Highway
New Feature Group Hierarchy:
```
Name | Implies | Includes
--------------|-------------|-----------------------------------------------------------
X86_V2 | | SSE SSE2 SSE3 SSSE3 SSE4_1 SSE4_2 POPCNT CX16 LAHF
X86_V3 | X86_V2 | AVX AVX2 FMA3 BMI BMI2 LZCNT F16C MOVBE
X86_V4 | X86_V3 | AVX512F AVX512CD AVX512VL AVX512BW AVX512DQ
AVX512_ICL | X86_V4 | AVX512VBMI AVX512VBMI2 AVX512VNNI AVX512BITALG
| | AVX512VPOPCNTDQ AVX512IFMA VAES GFNI VPCLMULQDQ
AVX512_SPR | AVX512_ICL | AVX512FP16
```
These groups correspond to CPU generations:
- `X86_V2`: x86-64-v2 microarchitectures (CPUs since 2009)
- `X86_V3`: x86-64-v3 microarchitectures (CPUs since 2015)
- `X86_V4`: x86-64-v4 microarchitectures (AVX-512 capable CPUs)
- `AVX512_ICL`: Intel Ice Lake and similar CPUs
- `AVX512_SPR`: Intel Sapphire Rapids and newer CPUs
Note: On 32-bit x86, `cx16` is excluded from `X86_V2`.
65 lines
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65 lines
2.8 KiB
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Test features "X86_V2" : Supported
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Test features "X86_V3" : Supported
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Test features "X86_V4" : Supported
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Test features "AVX512_ICL" : Supported
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Test features "AVX512_SPR" : Supported
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Configuring npy_cpu_dispatch_config.h using configuration
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Message:
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CPU Optimization Options
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baseline:
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Requested : min
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Enabled : X86_V2
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dispatch:
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Requested : max
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Enabled : X86_V3 X86_V4 AVX512_ICL AVX512_SPR
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Generating multi-targets for "_umath_tests.dispatch.h"
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Enabled targets: X86_V3, baseline
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Generating multi-targets for "argfunc.dispatch.h"
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Enabled targets: X86_V4, X86_V3, baseline
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Generating multi-targets for "x86_simd_argsort.dispatch.h"
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Enabled targets: X86_V4, X86_V3
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Generating multi-targets for "x86_simd_qsort.dispatch.h"
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Enabled targets: X86_V4, X86_V3
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Generating multi-targets for "x86_simd_qsort_16bit.dispatch.h"
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Enabled targets: AVX512_SPR, AVX512_ICL
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Generating multi-targets for "highway_qsort.dispatch.h"
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Enabled targets:
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Generating multi-targets for "highway_qsort_16bit.dispatch.h"
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Generating multi-targets for "loops_arithm_fp.dispatch.h"
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Enabled targets: X86_V3, baseline
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Generating multi-targets for "loops_arithmetic.dispatch.h"
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Enabled targets: X86_V4, X86_V3, baseline
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Generating multi-targets for "loops_comparison.dispatch.h"
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Enabled targets: X86_V4, X86_V3, baseline
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Generating multi-targets for "loops_exponent_log.dispatch.h"
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Enabled targets: X86_V4, X86_V3, baseline
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Generating multi-targets for "loops_hyperbolic.dispatch.h"
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Enabled targets: X86_V4, X86_V3, baseline
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Generating multi-targets for "loops_logical.dispatch.h"
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Enabled targets: X86_V4, X86_V3, baseline
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Generating multi-targets for "loops_minmax.dispatch.h"
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Generating multi-targets for "loops_modulo.dispatch.h"
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Enabled targets: baseline
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Generating multi-targets for "loops_trigonometric.dispatch.h"
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Enabled targets: X86_V4, X86_V3, baseline
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Generating multi-targets for "loops_umath_fp.dispatch.h"
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Enabled targets: X86_V4, baseline
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Generating multi-targets for "loops_unary.dispatch.h"
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Enabled targets: X86_V4, baseline
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Generating multi-targets for "loops_unary_fp.dispatch.h"
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Generating multi-targets for "loops_unary_fp_le.dispatch.h"
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Enabled targets: baseline
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Generating multi-targets for "loops_unary_complex.dispatch.h"
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Enabled targets: X86_V3, baseline
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Generating multi-targets for "loops_autovec.dispatch.h"
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Enabled targets: X86_V3, baseline
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Generating multi-targets for "loops_half.dispatch.h"
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Enabled targets: AVX512_SPR, X86_V4, baseline
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WARNING: Project targets '>=1.5.2' but uses feature deprecated since '1.3.0': Source file src/umath/svml/linux/avx512/svml_z0_acos_d_la.s in the 'objects' kwarg is not an object..
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Generating multi-targets for "_simd.dispatch.h"
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Enabled targets: X86_V3, X86_V4, baseline
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