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Carl RitsonandKonstantina Mitropoulou
c01b6605b5
Allow targets to add an MachineScheduler before PHI elimination, i.e. in SSA mode. Add initial support in AMDGPU backend for using SSA Machine Scheduler instead of normal Machine Scheduler. (This behaviour is disabled by default.) Also add basic "kick the tyres" demonstrator tests. This change is intended to support the introduction of a pre-RA spilling pass which runs prior to PHI elimination. Machine scheduler has a significant impact on register pressure and as such is best run before this new spilling pass. Co-authored-by: Konstantina Mitropoulou <KonstantinaMitropoulou@amd.com>
79 lines
2.5 KiB
C++
79 lines
2.5 KiB
C++
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file This file describes the general parts of a Subtarget.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/TargetSubtargetInfo.h"
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#include "llvm/IR/Intrinsics.h"
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using namespace llvm;
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TargetSubtargetInfo::TargetSubtargetInfo(
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const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
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StringTable PN, ArrayRef<SubtargetFeatureKV> PF,
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ArrayRef<SubtargetSubTypeKV> PD, ArrayRef<SubtargetSubTypeAliasKV> PA,
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const MCSchedModel *PSM, const MCWriteProcResEntry *WPR,
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const MCWriteLatencyEntry *WL, const MCReadAdvanceEntry *RA,
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const InstrStage *IS, const unsigned *OC, const unsigned *FP)
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: MCSubtargetInfo(TT, CPU, TuneCPU, FS, PN, PF, PD, PA, PSM, WPR, WL, RA,
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IS, OC, FP) {}
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TargetSubtargetInfo::~TargetSubtargetInfo() = default;
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bool TargetSubtargetInfo::isIntrinsicSupported(unsigned IntrinsicID) const {
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StringRef RequiredFeatures = Intrinsic::getRequiredTargetFeatures(
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static_cast<Intrinsic::ID>(IntrinsicID));
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if (RequiredFeatures.empty())
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return true;
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auto [It, Inserted] = IntrinsicSupportCache.try_emplace(IntrinsicID);
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if (Inserted)
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It->second = checkFeatureExpression(RequiredFeatures);
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return It->second;
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}
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bool TargetSubtargetInfo::enableAtomicExpand() const {
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return true;
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}
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bool TargetSubtargetInfo::enableIndirectBrExpand() const {
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return false;
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}
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bool TargetSubtargetInfo::enableMachineScheduler() const {
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return false;
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}
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bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
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return enableMachineScheduler();
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}
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bool TargetSubtargetInfo::enableRALocalReassignment(
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CodeGenOptLevel OptLevel) const {
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return true;
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}
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bool TargetSubtargetInfo::enablePostRAScheduler() const {
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return getSchedModel().PostRAScheduler;
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}
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bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
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return enableMachineScheduler() && enablePostRAScheduler();
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}
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bool TargetSubtargetInfo::enableSSAMachineScheduler() const { return false; }
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bool TargetSubtargetInfo::useAA() const {
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return false;
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}
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void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }
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