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https://github.com/llvm/llvm-project.git
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Nick Desaulniers
9428f1b09f
Change `TargetRegisterInfo::getRegAllocationHints` and all target overrides to accept `SmallSetVector<MCPhysReg, 16> &Hints` instead of `SmallVectorImpl`, structurally preventing duplicate register allocation hints while preserving insertion order. Assisted-by: Gemini Link: #190139 Link: #193011 Link: #219007 Link: #224448 Link: #224451 Link: #224742
106 lines
4.0 KiB
C++
106 lines
4.0 KiB
C++
//===-- llvm/CodeGen/AllocationOrder.cpp - Allocation Order ---------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements an allocation order for virtual registers.
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//
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// The preferred allocation order for a virtual register depends on allocation
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// hints, anti-hints, and target hooks. The AllocationOrder class encapsulates
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// all of that.
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//
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//===----------------------------------------------------------------------===//
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#include "AllocationOrder.h"
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#include "llvm/ADT/BitVector.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterClassInfo.h"
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#include "llvm/CodeGen/VirtRegMap.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "regalloc"
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static void getBitVecRegAntiHints(Register VReg, BitVector &AntiHintedRegUnits,
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const VirtRegMap &VRM,
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const MachineRegisterInfo &MRI,
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const TargetRegisterInfo &TRI) {
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assert(VReg.isVirtual() && "Anti-hints are only for virtual registers");
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for (Register AntiHintVReg : MRI.getRegAllocationAntiHints(VReg)) {
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// Check if the anti-hinted register has been allocated.
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if (!VRM.hasPhys(AntiHintVReg))
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continue;
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// Delay until first allocated anti-hinted register so unused cases keep
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// default empty BitVector.
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if (AntiHintedRegUnits.empty())
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AntiHintedRegUnits.resize(TRI.getNumRegUnits());
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for (MCRegUnit Unit : TRI.regunits(VRM.getPhys(AntiHintVReg)))
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AntiHintedRegUnits.set(static_cast<unsigned>(Unit));
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}
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}
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// Compare VirtRegMap::getRegAllocPref().
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AllocationOrder AllocationOrder::create(Register VirtReg, const VirtRegMap &VRM,
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const RegisterClassInfo &RegClassInfo,
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const LiveRegMatrix *Matrix) {
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const MachineFunction &MF = VRM.getMachineFunction();
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const TargetRegisterInfo *TRI = &VRM.getTargetRegInfo();
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg));
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// Get Hints.
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SmallSetVector<MCPhysReg, 16> Hints;
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bool HardHints =
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TRI->getRegAllocationHints(VirtReg, Order, Hints, MF, &VRM, Matrix);
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// HintsAndCustomOrder holds Hints first followed by the custom order if the
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// anti-hints reorders it.
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SmallVector<MCPhysReg, 16> HintsAndCustomOrder = Hints.takeVector();
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const int NumHints = static_cast<int>(HintsAndCustomOrder.size());
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// HintsAndCustomOrder only holds Hints (custom order is not added yet).
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LLVM_DEBUG({
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if (NumHints) {
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dbgs() << "hints:";
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for (MCPhysReg Hint : HintsAndCustomOrder)
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dbgs() << ' ' << printReg(Hint, TRI);
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dbgs() << '\n';
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}
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});
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// Get anti-hints.
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BitVector AntiHintedRegUnits;
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getBitVecRegAntiHints(VirtReg, AntiHintedRegUnits, VRM, MRI, *TRI);
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LLVM_DEBUG({
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if (AntiHintedRegUnits.any()) {
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dbgs() << "anti-hints:";
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for (Register AntiHintVReg : MRI.getRegAllocationAntiHints(VirtReg)) {
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if (!VRM.hasPhys(AntiHintVReg))
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continue;
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dbgs() << ' ' << printReg(VRM.getPhys(AntiHintVReg), TRI);
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}
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dbgs() << '\n';
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}
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});
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if (AntiHintedRegUnits.any())
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TRI->applyRegAllocationAntiHints(VirtReg, Order, HintsAndCustomOrder,
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NumHints, AntiHintedRegUnits, MF, Matrix,
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&RegClassInfo);
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// Create allocation order object.
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AllocationOrder AO(std::move(HintsAndCustomOrder), NumHints, Order,
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HardHints);
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assert(all_of(AO.hints(),
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[&](MCPhysReg Hint) { return is_contained(AO.Order, Hint); }) &&
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"Target hint is outside allocation order.");
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return AO;
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}
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